EEL 4301L Instructor: Masood Ejaz

EXPERIMENT # 5
DIRECT-COUPLED MULTISTAGE
AMPLIFIERS
THEORETICAL BACKGROUND

• Practically all integrated-circuit amplifiers require more than one stage of

amplification. For example, the operational amplifier needs differential input stage,
an output buffer to enable it to derive low resistance loads and an intermediate
amplifier with open loop gain in the order of 105 or more
• In this experiment a three-stage amplifier will be studied and designed. Some of the
common problems encountered in designing and testing of multistage amplifiers will
also be considered.
• Since in the integrated circuits large value capacitors cannot be used, multistage
amplifiers are connected directly with each other without DC isolating capacitors.
Hence the bias values of each stage of amplifier cannot be set independently.
Therefore the design and setting the bias points become more COMPLICATED
(Expect the lab to be long!!)
• Circuit # 1 shows a three-stage direct-coupled amplifier. The first two stages are
common emitter inverting amplifiers and the last stage is the emitter follower circuit.

Circuit # 1

• The overall gain of this amplifier can either be obtained using the Thevnin block
method as mentioned in lab # 1 or by deriving an expression from its small signal
model. The gains and input and output small signal resistances for the three stages
can be given as follows

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EEL 4301L Instructor: Masood Ejaz

Stage # 1

vout1 − β o1 RC1 R
a v1 = = ≈ − C1 (1)
vin1 ( β o1 + 1) RE1 + rπ 1 R E1

rin1 = R1 || R2 || [( β o1 + 1) RE1 + rπ 1 (2)

rout1 = RC1 (3)

Stage # 2

vout 2 − β o 2 RC 2 RC 2
av 2 = = ≈− (4)
vin 2 ( β o 2 + 1)( RE 2 || R3 ) + rπ 2 RE 2 || R3

rin 2 = ( β o 2 + 1)( RE 2 || R3 ) + rπ 2 ≈ β o 2 ( RE 2 || R3 ) (5)

rout 2 = RC 2 (6)

Stage # 3

vout 3 ( β o 3 + 1) RE 3
av3 = = ≈1 (7)
vin 3 ( β o 3 + 1) RE 3 + rπ 3

rin 3 = ( β o 3 + 1) RE 3 + rπ 3 ≈ β o 3 R E 3 (8)

rπ 3 + RC 2 rπ 3 + RC 2
rout 3 = RE 3 || ≈ (9)
β o3 + 1 β o3 + 1

All the approximate values are shown for high values of βo

• The total gain of the amplifier from the input of Q1 to the load (connected to the
output of Q3) will be given by

vL rin 2 rin 3 RL
av = = a v1 a v 2 a v 3 (10)
vin1 rin 2 + rout1 rin 3 + rout 2 RL + rout 3

PRELAB (2% of the Total Grade)

• Draw and label the small signal model of circuit # 1 in the mid-frequency band (no
capacitances included). You just have to draw and label the model, don’t have to
derive different quantities

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EEL 4301L Instructor: Masood Ejaz

• Draw an equivalent block diagram of the three-stage amplifier (similar to circuit # 2

of lab # 1) and prove that the total gain of the amplifier can be given by (10)

• Design circuit # 1 for av1 = -10 and av2 = -10. As shown in circuit # 1, the biasing
voltages for the three stages are VC1 = 5V, VC2 = 8V and VE3 = 7.3V respectively.
Values of VCEs for the three transistors are also shown in the figure. Assume VBE =
0.7 and βο = 180 for all the transistors. Use valid approximations to simplify your
design calculations.

Hints:
RC1
Since av1 = -10 is required, ≈ 10 , hence choose RC1 approximately 10 times
R E1
greater than RE1 (say RC1 = 10KΩ and RE1 = 1KΩ). Once you choose RC1 you will
know the approximate value of IC1 to give a voltage of 5V at the collector of Q1 (Note
that the current through RC1 is not really IC1, it is the sum of IC1 + IB2 but since in
active region the base currents are assumed to be much smaller than the collector
currents, hence in the calculations you can assume the current through each collector
resistance RC to be IC which in turns will be almost equal to the emitter current IE).
Once you figure out the value of IC1, you can calculate the approximate value of IB1
I
using C1 . To calculate R1 and R2, first make a Thevenin equivalent circuit at the
βo
input of transistor Q1 as you did in lab # 1, i.e., make a Thevenin equivalent of VCC,
R1 and R2, and then assume a suitable value for either R1 or R2 and solve for the other
resistance using circuit laws and available information.

For stage 2 of the amplifier, again you need a gain of -10, which results in the ratio
RC 2
of ≈ 10 . Note that for stage # 2 when you do the DC analysis R3 will be open
R E 2 || R3
circuit since it is connected through a capacitor. Hence a good way to calculate the
values will be to choose a value for R3 (say 1 KΩ) and then solve the circuit using
circuit laws and transistor relations to find out the values of RC2, RE2, and IC2 (IE2)
[You will need three equations with three unknowns to solve for RC2, RE2, and IC2
once you choose R3]. Once you calculate the resistance values, make sure to calculate
the voltage at the collector of Q1 again by adding the drop across RE2 and VBE2. If it
won’t result in close to 5V you have to change the resistance value(s) for stage # 2.

Once you will calculate the collector currents (or emitter currents) for stage # 1 and
stage # 2, you will observe that each subsequent stage has lower value of collector or
emitter currents, i.e., stage # 1 has highest, stage # 2 is lower than stage 1. This
pattern will go on for stage # 3 and the collector or emitter current has the smallest
value of all the stages (for example, if the value of your IC1 is around 1 mA then IC3
will be around 0.75 mA). Observing the pattern of IC1 and IC2, choose a suitable value
of RE3 that will result in the output biasing voltage of around 7.3 V. As long as
transistor is in active region the collector current value will not change hence if the
resistance you chose would not result in the voltage drop you are looking for, you can

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EEL 4301L Instructor: Masood Ejaz

just switch the resistance with another value without effecting the collector current
value until you get your desired voltage drop. This stage is easiest to set if the first
two stages are already set.

Avoid using very small and very big values of resistances. Better to use values of
resistances up to 10 KΩ but you can exceed this limit if it will satisfy your design.

• Once you design the circuit, simulate it using PSpice or Electronic Workbench and
confirm all the voltages and currents (DC values). Attach your simulation in your
notebook.

PROCEDURE

• For the circuit that you designed in the prelab, add a 100KΩ load resistor (RL) at the
output with a 100µF DC isolating capacitor and then measure the following DC bias
values:
o IC1, IC2, IC3, VC1, VC2, VE3, VCE1, VCE2, VCE3

If the values of VC1, VC2 and VE3 are close to the one shown in circuit # 1 and
transistor 1, 2 and 3 are in the active region, move to the next step, otherwise change
the values of some resistors (start from stage # 1 and move towards right) to get as
close values as possible. Once stage # 1 is set, rest of the circuit is easy to set.
• Now add a small signal input voltage vin = 10 KHz, 50mV sinusoidal source and
measure the small signal output volatage vout (you need to set the function generator
at HIGH Z and include a voltage divider to get a 50mV signal)
• Measure the small signal input resistance of the circuit by placing a variable resistor
across XX’ and change its value until the output voltage gets halved (As you did in
lab # 1)
• Measure the small signal output resistance by placing a variable resistor across YY’
and change its value until the output gets halved.

DATA ANALYSIS

• Analyze and compare your measured gain value to the calculated value from equation
(10)
• Analyze and compare the measured value of small signal input resistance of the
circuit to the calculated value from equation (2)
• Analyze and compare the measured value of small signal output resistance of the
circuit to the calculated value from equation (9)