Topic: I/O Module

(Computer Organization and Architecture )

KCS-302
 I/O Module • I/O Module interfaces to the system bus or central switch
to control peripheral devices.
 Generic Model • It contains logic for performing a communication
function between the peripheral and system bus

[1]
 An external device connected to a I/O module is
I/O Module often referred to peripheral device.
Peripheral devices helps users to access and use the
 Peripheral Device functionality of computer system. E.g. keyboard,
 Introduction mouse, printer etc.
 Classification of External device is attached to computer through a
external devices. link to I/O module, this link is used to exchange
control, status and data bits.
There are three classification of external devices:
1. Human Readable: Monitors, printers
2. Machine readable: tapes, sensors, actuators
3. Communication devices: other computer, or
remote machine readable device
 • There are a wide variety of peripherals
I/O Module making it impractical to incorporate the
 Need of Separate necessary logic within the processor
I/O Module
• The data transfer rate of peripherals is
often much slower than that of the
memory or processor. Synchronization is
required.

• Peripherals often use different data

formats and word lengths than the
computer to which they are attached.
 I/O Module
 Functions of I/O Control & Timing
Module
CPU Communication
Device Communication
Data Buffering
Error Detection
 I/O Module
•Interface supervises and synchronize all input/output transfers
 I/O Interface •Each peripheral device uses interface unit from I/O Module
•Interface Decode address and control received from I/O
•To communicate processor put device address on address lines,
Each interface monitors address lines, if matched activates path.

[2]
 I/O Module •All devices with non matching address are disabled through
corresponding interface.
 I/O Interface(2)
• The selected interface respond to function code and is referred
to as I/O Command

•Interpretation of command depends on peripheral

• There could be four types of commands

1. Control: Used to activate a peripheral and tell it what to do

2. Test/Status: Used to test various status conditions
3. Read: Enables the I/O module to obtain data from peripheral
4. Write: Enables the I/O module to take data (byte or word)
from the data bus and transmit that data item to the
peripheral
 I/O Module
 I/O Interface
Example

[2]
 I/O Module There are three methods which can used in computer system for
Memory or I/O transfer
 I/O vs Memory Bus
1. Use separate buses memory and I/O

2. Use common buses with separate control line for each

3. Use one common bus for memory and I/O transfer with
common control lines.(Mostly Used)
 A connection point that act as interface
I/O Module between computer and external devices.
 I/O Ports
Types:
1. Internal Ports: Used to connect internal
devices like hard disk drive, CD Drive etc.
with motherboard
2. External Ports: Used to connect
motherboard to external devices like
mouse, printer, flash drive etc.
  I/O module with enhance capability of I/O
Input execution are termed as I/O channel.
output
channel I/O Channel greatly reduced the Main
and processor burden as I/O operations are
processors performed through it without much CPU
involvement

A special processor in I/O channel execute

I/O instructions.
Types of I/O channel
1. Selector
2. A Multiplexor Channel
 Controls multiple high speed devices &
I/O channel uses one at a time
 Selector Channel I/O channel controls the corresponding I/O
control at place of CPU

[1]
 Can handle number of devices at a time.
I/O channel
For slow devices byte multiplexing is used
 Multiplexor E.g. if we have three devices having
Channel
following stream of bytes
B1, B2, B3….. Data from device 1
C1,C2,C3…….. Data from Device-2
D1,D2,D3……. Data from Device-3

In this case byte multiplexer will send data as

B1C1D1B2C2D2……
 A signal to processor by
hardware/Software stating immediate
 Introduction - attention
Interrupts Kind of high priority alert to CPU to
interrupt its ongoing activity
In this case CPU stores current state, and
handles the interrupt through handler
Once the interrupt is handled CPU resumes
its normal execution
Actually most of the operation are being
performed through interrupts e.g. using
keyboard, mouse, playing any file
 Hardware Interrupts such as pressing key from the
keyboard
a) Maskable( Lower priority)
 Types of Interrupts
b) Non Maskable (Higher Priority)

 Software Interrupts such as arithmetic overflow,

division by zero, illegal machine instruction
a) Normal interrupts: Through Software instructions
b) Exceptions: divide by zero (unplanned)
 Based on Period
• Periodic ( e.g. periodic polling after fix interval)
 Further • Unpredictable
Classification Based on time
• Asynchronous (Independent of clock)
• Synchronous (Based on clock pulse)
 Based on CPU & Address Availability
• Vectored(ISR is known in advance through bus and
I/O interface, CPU Check IVT and execute
corresponding ISR.
• Non Vectored( No ISR is sent by interrupting device,
CPU Jumps to specific address in hardware, to know
status each device needs to be polled.
 Processing cycle of
Interrupt

[1]
 If multiple devices interrupts at same time then
Certain arbitration mechanism is used by CPU
a) CPU with Shared interrupt request Line
 Interrupt
• Bus arbitration technique like daisy chain is used
Selection
• All devices are scanned on receiving interrupt
signal by scanning corresponding ports
a) CPU with independent interrupt request line
• Easily identifies corresponding interrupting
device.
• Priority mechanism is used in this case
• This approach waste many lines of system bus for
initiating interrupt
Modes of
Data
Data transfer between central computer
Transfer and I/O can be handled in different ways:
1. Programmed I/O
2. Interrupt Initiated I/O
3. Direct Memory Access

In these techniques CPU may / May not be

involved partially or completely
 Programme •CPU has direct control over I/O
d I/O 1. Sensing status
2. Read/write commands
 Concept
3. Transferring data
 Process •CPU waits for I/O module to
complete operation
•Wastes CPU time
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU
directly
• I/O module does not interrupt
CPU
• CPU may wait or come back later
 In shared bus scenario where CPU, memory
Programme and IO share same Bus two types of
d I/O addressing are used
 Memory • Memory mapped I/O
Mapped I/O • Devices and memory share same address space
 Isolated I/O • Processor Uses the same machine instructions to
access both memory and I/O devices
• I/O looks just like memory read/write
• No special commands for I/O
• Isolated I/O
• Separate address spaces for I/O and Memory
Devices
• Need I/O or memory select lines with address
• Special commands for I/O
 Programme
d I/O
 Memory
Mapped vs
Isolated I/O
Example
 Interrupt
• Overcomes CPU waiting
Driven I/O
• No repeated CPU checking of device
 Introduction
• I/O module interrupts when ready
 Basic Operation

CPU issues read command to I/O module

I/O module gets data from peripheral
whilst CPU does other work
I/O module interrupts CPU
CPU requests data
I/O module transfers data
 Interrupt
• Issue read command
Driven I/O
• Do other work
 Basic Process
from CPU point • Check for interrupt at end of each
of view instruction cycle
• If interrupted:-
• Save context (registers)
• Process interrupt
• Fetch data & store
 Interrupted
Driven I/O
 Basic Process

[1]
 Summary
Programmed I/O Interrupt Driven I/O

It can be implemented without Additional hardware is required to

any additional Hardware circuit handle interrupt

 A Comparison
It is simple and used in low-end Most of high-end systems are
system where cost is important interrupt driven where speed is
factor important factor
Busy waiting is involved CPU switches to other jobs while
I/O is going on

Only one I/O Can be handled at Multiple I/O activity can be

time handled in overlapped Fashion
 DMA
Transfer
Third approach of I/O data Transfer
 Introduction
DMA: Direct Memory Transfer
• In transfer of data between storage device
such as magnetic disc and memory if we
are able to remove the CPU and let the
peripheral manage the transfer directly
would be called as DMA.
• During DMA transfer , CPU is idle and has
no control of the buses. This control is
transferred to DMA controller.
 DMA
Can be done through two control signals
• Bus Request : Used by DMA controller to
 Making CPU Idle inform the CPU to relinquish the control of
buses.

• Bus Grant: Is used to inform the DMA

controller that request has been accepted
and CPU has released the control of buses.
 DMA
• When DMA takes control of Buses. It
communicates directly with memory.
 Burst Transfer • Burst Transfer means a block sequence of
vs. Cycle
stealing Transfer memory words is transferred in continuous
method burst without giving control back to CPU.
• Cycle Stealing allows the DMA controller
to transfer one data word at a time and
then return control to CPU.
• CPU leaves one cycle intentionally free for
each DMA Transfer alternatively
DMA • In addition to usual circuit it needs an address register, a
word count register, and a set of address lines
• Word count register is used to mention number of words
 CPU Bus
signal for • When the BG =0, the CPU can communicate with the DMA
DMA transfer registers through the data bus to read/write DMA register
• When BG = 1, the CPU has relinquished the buses and the
DMA can communicate directly with the memory by
specifying an address in the address bus through
activating the RD or WR control
 •Register in DMA are selected by CPU by enabling DS and RS
DMA through address bus
•DMA communicates with peripheral through request & ack line
using handshake procedure.
 Block Diagram •DMA controller is initialized with starting address, word count,
of DMA RD/WR control and DMA enable control
Controller
 DMA • First Peripheral device sends DMA request.
• DMA controller activates BR line.
Transfer • CPU respond with BG line indicating disabling of Bus by CPU.
 Making CPU Idle • DMA puts the current value of AR into Add. Bus. And initiates RD
or WR signal
• DMA Send DMA ack to peripheral
• After Receiving the DMA ack . Peripharal puts a word in data
bus(for write) or read a word from data bus(for read).
• Now the peripheral unit can directly communicate memory
through data bus till the CPU is momentarily disabled.
• For Each word that is transferred DMA Increments its address
register and decrements its word count register.
• If the word count register reaches zero, the DMA stops any
further tranfer and removes its bus request. And control of buses
is taken back by CPU.
 DMA

 DMA Transfer in
computer
system

[1]
 Contents
• Serial Communication

• Modes of serial communication

• Synchronous and Asynchronous Communication

• Difference between Synchronous and Asynchronous

Communication
Serial vs. Parallel Transmission

The transfer of data between two units may be:

• Parallel
• Serial
 Serial vs. Parallel
• In parallel data transfer, the entire message is transmitted at one time.

• n-bit message is transmitted in parallel through n separate conductor

paths.

• In serial data transmission, each bit in the message is sent in sequence, one
at a time.
Serial vs. Parallel
 Modes of Serial Communication:
• Serial data can be transmitted
between two points in three
different modes:
• Simplex
• Half Duplex
• Full Duplex
A simplex line carries information in one direction only.
Examples : Radio and television broadcasting
A half-duplex transmission system is capable of transmitting in both
directions, but in only one direction at a time.
Example: walkie talkie
A full-duplex transmission system can send and receive data in both
directions simultaneously.
Example: Telephone communication
Types of Serial Communication:
• The serial transmission of data can be:
• Synchronous
• Asynchronous
Synchronous Transmission
• In synchronous transmission, the two units share
a common clock frequency

• and bits are transmitted continuously at the rate

dictated by the clock pulses.

• In long distant serial transmission, each unit is

driven by a separate clock of the same frequency.

• Synchronization signals are transmitted

periodically between the two units to keep their
clocks in step with each other.
Asynchronous Transmission
• In asynchronous transmission, binary
information is sent only when it is
available.

• In serial asynchronous data transmission

technique special bits are inserted at
both ends of the character code.

• With this technique, each character

consists of three parts: a start bit, the
character bits, and stop bits.
• So the typical Data Format (known as
“FRAME”) for Asynchronous
Communication.
 Asynchronous Transmission
The transmitter rests at the 1-state when no
characters are transmitted.
The first bit, called the start bit, is always a
0 and is used to indicate the beginning of
a character.

The last bit called the stop bit is always a 1.

• Sends constant ‘1’ for idle
• Sends a ‘0’ for start and “1” for stop
bits
Difference between Synchronous and
Asynchronous Serial Communication
Synchronous Asynchronous

The rates determined by the clock The transmission can occur at any
rates time
In Synchronous transmission, time In asynchronous transmission, time
interval of transmission is constant. interval of transmission is not
constant, it is random.
Synchronous transmission needs Asynchronous transmission have no
precisely synchronized clocks for the need of synchronized clocks
information of new bytes.
Synchronous transmission is fast. Asynchronous transmission is slow.

This method is used for high volume This method is used for low volume
of data of data
 Contents
• Serial Interface

• Parallel interface

• Point-to-Point and Multipoint Configurations

• Ethernet
Types of Interfaces:
• One major characteristic of the interface is whether it is serial or
parallel.
• Parallel Interface
• Serial Interface
 Parallel Interface
• In a parallel interface, there are multiple
lines connecting the I/O module and the
peripheral.

• Multiple bits are transferred

simultaneously.

• A parallel interface has traditionally

been used for higher-speed peripherals,
such as tape and disk.
 Serial Interface
• In a serial interface, there is only one
line used to transmit data.

• Bits must be transmitted one at a time.

• The serial interface has traditionally

been used for serial printers and
terminals.
Point-to-Point and Multipoint Configurations
• The connection between an I/O module in a computer system and
external devices can be:
• Point-To-Point
• Multipoint
 Point-To-Point vs. Multipoint
• A point-to-point interface provides a dedicated line between the I/O module and
the external device.

• On small systems (PCs, workstations), typical point-to-point links include those to

the keyboard, printer, and external modem.

• A typical example of such an interface is the EIA-232 specification .

• In a multipoint connection, the link is between a sender and multiple receivers.

Multipoint external interfaces are used to support external mass storage devices
(disk and tape drives) and multimedia devices.
 Serial Interfaces
• Well-‐established standard, developed by
• To connect a system to a voice-grade the EIA (Electronics Industry Association)
modem in 1960s

• On PCs, a “serial interface” implies a • Originally intended as an electrical

“COM port”, or “communications port” specification to connect computer
• – COM1, COM2, COM3, etc. terminals to modems

• COM ports conform to the RS‐232C • Defines the interface between a DTE and
interface standard a DCE

• DTE = Data Terminal Equipment (terminal)

• DCE = Data Communications Equipment
(modem)
 Serial Interfaces
• – A “terminal” is anything at the “terminus” of the connection
• VDT (video display terminal), computer, printer, etc.
• Data rate
– Maximum specified data rate is 20 Kbits/s with a maximum cable length of 15 meters
• It is common to “push” an RS232C interface to higher data rates
• Data rates to 1 Mbit/s can be achieved (with short cables!)

• Configuration
• – Serial, point-to-point
 Parallel Interfaces • – Improvements
• EPP (Enhanced Parallel Port)
• In the context of PCs, a “parallel interface”
implies a Centronics- compatible printer • Enshrined in the standard IEEE-1284 (1994)
interface • – “Standard Signalling Method for a Bi-
directional Parallel Peripheral Interface for
Personal Computers”
• Originally developed by printer company,
Centronics • – Includes Centronics /LPT mode, EPP mode,
• and…
• Introduced on the IBM PC (1981) as an LPT • – ECP mode (Enhanced Capability Port)
(“line printer Terminal”) port • Data Rate – 150 Kbytes/s (LPT) to1.5
Mbytes/s (ECP)
• Configuration
• – Parallel, point-‐to-‐point
 Ethernet • Fast
• To connect a system to a high-speed network • Ethernet
• In 1980, Xerox, Digital Equipment Corporation • Specified in IEEE 802.3u (100Base-TX)
(DEC, now Compaq), and Intel published a
specification for an “Ethernet” LAN (local area • Data Rate
network)
• – 10 Mbits/s for Ethernet (10Base-T)
• Now exists as a standard
• – 100 Mbits/s for Fast Ethernet
• IEEE 802.3 (100Base-T)
• Physical Interface uses either coax cable with • – 1000 Mbits/s for Gigabit Ethernet
BNC connectors or twisted pair cable with RJ‐45 (1000Base-‐T)
connectors (10Base‐T)
• Configuration
• Serial, multi-‐point (token ring or
token bus)