True Multi-Touch Capacitive Touch Panel Controller

FT5x06
True Multi-Touch
Capacitive Touch Panel Controller
INTRODUCTION
The FT5x06 Series ICs are single-chip capacitive touch panel controller ICs with a built-in 8 bit Micro-controller unit (MCU).They
adopt the mutual capacitance approach, which supports true multi-touch capability. In conjunction with a mutual capacitive touch
panel, the FT5x06 have user-friendly input functions, which can be applied on many portable devices, such as cellular phones, MIDs,
netbook and notebook personal computers.
The FT5x06 series ICs include FT5206/FT5306/FT5406, the difference of their specifications will be listed individually in this
datasheet.
FEATURES
z Capable of Driving Single Channel (transmit/receive) Re-
z Mutual Capacitive Sensing Techniques
sistance: Up to15K Ω
z True Multi-touch with up to 10 Points of Absolution X and
z Capable of Supporting Single Channel (transmit/receive)
Y Coordinates
Capacitance: 60 pF
z Immune to RF Interferences
z Optimal Sensing Mutual Capacitor: 1pF~4pF
z Auto-calibration: Insensitive to Capacitance and Environ-
z 12-Bit ADC Accuracy
mental Variations
z Built-in MCU with 28KB Program Memory, 6KB Data
z Supports up to 28 Transmit Lines and 16 Receive Lines
Memory and 256B Internal Data Space
z Supports up to 8.9” Touch Screen
z 11 Internal Interrupt Sources and 2 External Interrupt
z Full Programmable Scan Sequences with Individual Ad- Sources
justable Receive Lines and Transmit Lines to Support
z 3 Operating Modes
Various Applications
¾ Active
z High Report Rate: More than 100Hz
¾ Monitor
z Touch Resolution of 100 Dots per Inch (dpi) or above -- ¾ Hibernate
depending on the Panel Size z Operating Temperature Range: -40°C to +85°C
z Optional Interfaces :I2C/SPI
z 2.8V to 3.6V Operating Voltage
z Supports 1.8V/AVDD IOVCC
管制文件
2011.03.07
文管中心
FocalTech Systems Co., Ltd · www.focaltech-systems.com · [email protected]
Document Number: D-FT5x06-1005 (Version: 0.4) Revised DEC 20, 2010
From No.: F-OI-RD01-03-03-B

FT5x06
DATASHEET
\\
TABLE OF CONTENTS
INTRODUCTION..........................................................................................................................................................I
FEATURES ....................................................................................................................................................................I
1 OVERVIEW .............................................................................................................................................................. 1
1.1 TYPICAL APPLICATIONS ....................................................................................................................................... 1
2 FUNCTIONAL DESCRIPTION ................................................................................................................................. 1
2.1 ARCHITECTURAL OVERVIEW................................................................................................................................. 1
2.2 MCU ................................................................................................................................................................ 2
2.3 OPERATION MODES ............................................................................................................................................ 2
2.4 HOST INTERFACE ................................................................................................................................................ 3
2.5 SERIAL INTERFACE ............................................................................................................................................. 3
2.5.1 I2C ........................................................................................................................................................... 3
2.5.2 SPI........................................................................................................................................................... 4
3 ELECTRICAL SPECIFICATIONS .................................................................................................................................... 8
3.1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................................. 8
3.2 DC CHARACTERISTICS ............................................................................................................................................. 9
3.3 AC CHARACTERISTICS ............................................................................................................................................. 9
3.4 I/O PORTS CIRCUITS ............................................................................................................................................ 10
3.5 POWER ON/RESET/WAKE SEQUENCE .................................................................................................................... 11
4 PIN CONFIGURATIONS ............................................................................................................................................. 12
5 PACKAGE INFORMATION.......................................................................................................................................... 15

5.1 PACKAGE INFORMATION OF QFN-5X5-40L PACKAGE .................................................................................................... 15
5.4 ORDER INFORMATION ............................................................................................................................................ 18
FocalTech Systems Co., Ltd · www.focaltech-systems.com · [email protected]
Document Number: D-FT5x06-1005 (Version: 0.4) Revised DEC 20, 2010
From No.: F-OI-RD01-03-03-B

FT5x06
DATASHEET
1 OVERVIEW
1.1 Typical Applications
FT5x06 accommodate a wide range of applications with a set of buttons up to a 2D touch sensing device, their typical applications
are listed below.
z Mobile phones, smart phones
z MIDs
z Netbook
z Navigation systems, GPS
z Game consoles
z Car applications
z POS (Point of Sales) devices
z Portable MP3 and MP4 media players
z Digital cameras
FT5x06 Series ICs support 2.8”~8.9” Touch Panel, users may find out their target IC from the specs. listed in the following table,
Panel Package
Model Name Touch Panel Size
TX RX Type Pin Size
FT5206GE1 15 10 QFN5*5 40 0.75-P0.4 2.8"～3.8"
FT5306DE4 20 12 QFN6*6 48 0.75-P0.4 4.3"～7"
FT5406EE8 28 16 QFN8*8 68 0.75-P0.4 7"～8.9"
2 FUNCTIONAL DESCRIPTION
2.1 Architectural Overview
Figure2-1 shows the overall architecture for the FT5x06.
Figure 2-1 FT5x06 System Architecture Diagram
The FT5x06 is comprised of five main functional parts listed below,
FocalTech Systems Co., Ltd Version 0.4︱Page 1 of 21

FT5x06
DATASHEET
z Touch Panel Interface Circuits

The main function for the AFE and AFE controller is to interface with the touch panel. It scans the panel by sending AC signals to the
panel and processes the received signals from the panel. So, it supports both Transmit (TX) and Receive (RX) functions. Key pa-
rameters to configure this circuit can be sent via serial interfaces, which will be explained in detail in a later section.
z 8051-based MCU
This MCU is 8051 compatible with some enhancements. For instant, larger program and data memories are supported. In addition, a
Multiplication-Division unit (MDU) is implemented to speed up the touch detection algorithms. Furthermore, a Flash ROM is
implemented to store programs and some key parameters.
Complex signal processing algorithms are implemented with firmware running on this MCU to process further the received signals in
order to detect the touches reliably. Communication protocol software is also implemented on this MCU to exchange data and
control information with the host processor.
z External Interface
¾ I2C/SPI: an interface for data exchange with host
¾ INT: an interrupt signal to inform the host processor that touch data is ready for read
¾ WAKE: an interrupt signal for the host to change F5x06 from Hibernate to Active mode
¾ /RST: an external low signal reset the chip.
z A watch dog timer is implemented to ensure the robustness of the chip.
z A voltage regulator to generate 1.8V for digital circuits from the input VDD3 supply
2.2 MCU
This section describes some critical features and operations supported by the 8051 compatible MCU.
Figure 2-2 shows the overall structure of the MCU block. In addition to the 8051 compatible MCU core, we have added the following
circuits,
z MDU: A 16x8 Multiplier and A 32/32 Divider
z Program Memory: 28KB Flash
z Data Memory: 6KB SRAM
z Real Time Clock (RTC): A 32KHz RC Oscillator
z Timer: A number of timers are available to generate different clocks
z Master Clock: 24/ 48MHz from a 48MHz RC Oscillator
z Clock Manager: To control various clocks under different operation conditions of the system
Figure 2-2 MCU Block Diagram

2.3 Operation Modes
FT5x06 operates in the following three modes:
z Active Mode
When in this mode, FT5x06 actively scans the panel. The default scan rate is 60 frames per second. The host processor can configure
FT5x06 to speed up or to slow down.

FT5x06
DATASHEET
z Monitor Mode
When in this mode, FT5x06 scans the panel at a reduced speed. The default scan rate is 25 frames per second and the host processor
can increase or decrease this rate. When in this mode, most algorithms are stopped. A simpler algorithm is being executed to de-
termine if there is a touch or not. When a touch is detected, FT5x06 shall enter the Active mode immediately to acquire the touch
information quickly. During this mode, the serial port is closed and no data shall be transferred with the host processor.
z Hibernate Mode
In this mode, the chip is set in a power down mode. It shall only respond to the “WAKE” or “RESET” signal from the host processor.
The chip therefore consumes very little current, which help prolong the standby time for the portable devices.
2.4 Host Interface

Figure 2-3 shows the interface between a host processor and FT5x06. This interface consists of the following three sets of signals:
z Serial Interface
z Interrupt from FT5x06 to the Host
z Wake-up Signal from the Host to FT5x06
TP Module
Serial
Interface
TX
TP FT5x06 Host
RX
/INT
/WAKE
Figure 2-3 Host Interface Diagram
The serial interfaces of FT5x06 is I2C or SPI. The details of this interface are described in detail in Section 2.5. The interrupt signal
(/INT) is used for FT5x06 to inform the host that data are ready for the host to receive. The /WAKE signal is used for the host to wake
up FT5x06 from the Hibernate mode. After exiting the Hibernate mode, FT5x06 shall enter the Active mode.
2.5 Serial Interface

FT5x06 supports the I2C or SPI interfaces, which can be used by a host processor or other devices.
2.5.1 I2C
The I2C is always configured in the Slave mode. The data transfer format is shown in Figure 2-4.
Figure 2-4 I2C Serial Data Transfer Format

FT5x06
DATASHEET
Figure 2-5 I2C master write, slave read
Figure 2-6 I2C master read, slave write
Table 2-1 lists the meanings of the mnemonics used in the above figures.
Table 2-1 Mnemonics Description
Mnemonics Description
S I2C Start or I2C Restart
Slave address
A[6:0] A[6:4]: 3’b011
A[3:0]: data bits are identical to those of I2CCON[7:4] register.
W 1’b0: Write
R 1’b1: Read
A(N) ACK(NACK)
STOP: the indication of the end of a packet (if this bit is missing, S will indicate the end
P
of the current packet and the beginning of the next packet)
I2C Interface Timing Characteristics is shown in Table 2-2.
Table 2-2 I2C Timing Characteristics
Parameter Unit Min Max

SCL frequency KHz 0 400
Bus free time between a STOP and START condition us 4.7 \
Hold time (repeated) START condition us 4.0 \
Data setup time ns 250 \
Setup time for a repeated START condition us 4.7 \
Setup Time for STOP condition us 4.0 \
2.5.2 SPI
SPI is a 4 wire serial interface. The following is a list of the 4 wires:
z SCK: serial data clock
z MOSI: data line from master to slave
z MISO: data line from slave to master
z SLVESEL: active low select signal
SPI transfers data at 8bit packets. The phase relationship between the data and the clock can be defined by the two registers: phase
and polck. Some data transfer examples can be found in Figure 2-7 to Figure 2-10.

FT5x06
DATASHEET
Figure 2-7 SPI Data Transfer Format (Phase=0, POLCK=0)
Figure 2-8 SPI Data Transfer Format (PHASE=0, POLCK=1)
PHASE=1 POLE=0
SCK
MISO/MOS
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
I
MSB
SLVSEL

SPI can be configured into either Master or Slave mode via the MAS bit of the SPI0CON register. When in the Master mode, the SPI
needs to supply the data clock, whose frequency relationship with the Master clock can be set by CLKDVD bits of the SPI0CON
register. When it is configured in the Slave mode, the clock, SCK, is supplied by the external Master. The maximum data clock
Fmclk
frequency must not be higher than .
8
SPI Interface Timing Characteristics is shown in the following Figure2-11,Figure2-12, Figure2-13, Figure2-14 and Table 2-3.

FT5x06
DATASHEET
PHASE=0
Tmckh Tmckl
SCK(POLCK=0
)
SCK(POLCK=1
)
Tmh Tmo
MOSI
MISO
Tsd Tmsr
SLVSEL c
Tmsf
c
Figure 2-11 SPI master Timing PHASE =0
PHASE=1
Tmck
Tmckl
h
SCK(POLCK=0
)
SCK(POLCK=1
)
Tmh Tmo
MOSI
MISO
Tmsr
SLVSEL c
Tmsfc
Figure 2-12 SPI master Timing PHASE =1

FT5x06
DATASHEET
Figure 2-13 SPI slave Timing PHASE = 0
PHASE=1
Tsck
Tsckl
h
SCK(POLCK=0
)
SCK(POLCK=1
) T
Th
s
MOSI
MISO
To
Tsr
SLVSEL c
Tsfc
Figure 2-14 SPI slave Timing PHASE = 1
Table 2-3 SPI Timing Parameters
Parameter Description Min Max Units

Master Mode timing (see figure 2-11,2-12)
Tmckh sck high time 4×Tsysclk -- ns
Tmckl sck low time 4×Tsysclk -- ns
Tmo sck shift edge to mosi data change 0 -- ns
Tmh mosi data valid to sck shift edge 3×Tsysclk -- ns
Tsd slvsel falling edge to mosi data valid 4×Tsysclk -- ns
Tmsfc slvsel falling edge to first sck edge (Tmckh+Tmckl)/2 -- ns

FT5x06
DATASHEET
Tmsrc last sck edge to slvsel rising edge (Tmckh+Tmckl)/2 -- ns
Slave mode timing(See figure 2-13,2-14)

Tsckh sck high Time 4×Tsysclk -- ns
Tsckl sck low Time 4×Tsysclk -- ns
Tsd slvsel falling edge to Miso valid data time 0 4xTsysclk ns
Ts Mosi Data valid to sck sample edge 0 -- ns
Th sck sample edge to Mosi data change 4×Tsysclk -- ns
To sck shift edge to Miso data change 0 4xTsysclk ns
Tsfc slvsel falling edge to first sck edge 4×Tsysclk -- ns
Tsrc last sck edge to slvsel rising edge 4×Tsysclk -- ns
*Tsysclk is equal to one period of the device system clock
3 ELECTRICAL SPECIFICATIONS
3.1 Absolute Maximum Ratings
Table 3-1 Absolute Maximum Ratings
Item Symbol Unit Value Note

Power Supply Voltage 1 VDDA - VSSA V -0.3 ~ +3.6 1, 2
Power Supply Voltage 2 VDD3 – VSS V -0.3 ~ +3.6 1, 3
I/O Power Supply Voltage Vt V -0.3 ~ IOVCC + 0.3 1,4
Operating Temperature Topr ℃ -40 ~ +85 1
Storage Temperature Tstg ℃ -55 ~ +125 1
Notes
1.If used beyond the absolute maximum ratings, FT5x06 may be permanently damaged. It is strongly recommended that the device
be used within the electrical characteristics in normal operations. If exposed to the condition not within the electrical characteristics,
it may affect the reliability of the device.
2.Make sure VDDA(high)≥VSSA (low)
3.Make sure VDD (high)≥VSS (low)
4.IOVCC is set to VDD3 or VDDD by software configuration.

FT5x06
DATASHEET
3.2 DC Characteristics
Table 3-2 DC Characteristics (VDDA=VDD3=2.8~3.6V, Ta=-40~85℃)
Item Symbol Unit Test Condition Min. Typ. Max. Note

Input high-level voltage VIH V 0.7 x IOVCC -- IOVCC
Input low -level voltage VIL V -0.3 -- 0.3 x IOVCC
Output high -level voltage VOH V IOH=-0.1mA 0.7 x IOVCC -- --
Output low -level voltage VOL V IOH=0.1mA -- -- 0.3 x IOVCC
I/O leakage current ILI μA Vin=0~VDDA -1 -- 1

Current consumption VDDA=VDD3 = 2.8V
Iopr mA -- 6 --
（Normal operation mode） Ta=25℃ MCLK=24MHz
Imon mA -- 4 --
（Monitor mode） Ta=25℃ MCLK=24MHz
Islp mA -- 0.03 --
（Sleep mode） Ta=25℃ MCLK=24MHz
Step-up output voltage VDD5 V VDDA=VDD3= 2.8V 5 5.25 5.6
VDDA
Power Supply voltage V 2.7 2.8~3.6 3.7
VDD3
3.3 AC Characteristics
Table 3-3 AC Characteristics of Oscillators
Item Symbol Unit Test Condition Min. Typ. Max. Note

VDD3 = 2.8V
OSC clock 1 fosc1 MHz 43 48 52
Ta=25℃
VDD3 = 2.8V
OSC clock 2 fosc2 KHz 29 32 36
Ta=25℃
Table 3-4 AC Characteristics of TX & RX

Item Symbol Unit Test Condition Min Typ Max Note
TX acceptable clock ftx KHz 100 150 270
TX output rise time Ttxr nS -- 20 --
TX output fall time Ttxf nS -- 20 --
RX input voltage Trxi V 1.2 -- 1.6
FocalTech Systems Co., Ltd Version 0.3 ︱Page 9 of 21

FT5x06
DATASHEET
3.4 I/OPortsCircuits
Figure 3-1 Digital Input & Output Port Circuits Figure 3-2 Digital In/Out Port Circuit
Figure 3-3 Reset Input Port Circuits Figure 3-4 Wake Input Port Circuits
Figure 3-5 INT output Port Circuits Figure 3-6 SCL/SDA Port Circuits

FT5x06
DATASHEET
3.5 POWER ON/Reset/Wake Sequence
The GPIO such as Wake, INT and I2C should be pulled down to be low before powering on. The signal of waking up should be set
to be high after powering on. INT signal will be sent to the host after initializing all parameters and then start to report points to the
host.
Tr i s
P o we r
Figure 3-7 Power on time
Tpon
Power
Wakeup
I NT
I 2C/ SPI
Figure 3-8 Power on Sequence

Reset time must be enough to guarantee reliable reset, The time of starting to report point after resetting approach to the time of
starting to report point after powering on.
Tr s i
Tr s t
Power
RESET
I NT
I 2C/ SPI
Figure 3-8 Reset Sequence

Wake time must be enough to wake up the system, The time of starting to report point after waking approach to the time of starting
to report point after powering on

FT5x06
DATASHEET
Twai
Twak
Power
Wa k eup
I NT
I 2C/ SPI
Figure 3-8 Wake Sequence
Table 3-5 Power on/Reset/Wake Sequence Parameters
Parameter Description Min Max Units

Tris Rise time from 0.1VDD to 0.9VDD -- 10 ms
Tpon Time of starting to report point after powering on 300 -- ms
Trsi Time of starting to report point after resetting 300 -- ms
Trst Reset time 5 -- ms
Twai Time of starting to report point after waking 300 -- ms
Twak Wake up time 5 -- ms
4 PIN CONFIGURATIONS
Pin List of FT5x06
Table 4-1 Pin Definition of FT5x06
Pin No.
Name Type Description
FT5206GE1 FT5306DE4 FT5406EE8
VSSA 40 1 1 PWR Analog ground
NC 1 2 2 Not connected
NC 48 3 Not connected
TX28 4 O Transmit output pin
TX20 3 12 O Transmit output pin
TX15 2 8 17 O Transmit output pin

FT5x06
DATASHEET

internal generated 5V power supply， A 1μF ceramic
VDD5 17 23 32 PWR
capacitor to ground is required.
VDD3 18 24 33 PWR Analog power supply
VSS 19 25 34 PWR Analog ground
Digital power supply (1.8V), generated internal. A 1μF
VDDD 20 26 35 PWR
ceramic capacitor to ground is required.
TEST_EN 21 27 36 I Test mode enabled at high and float in normal mode
GPIO0 37 I/O General Purpose Input/Output port
SSEL/SCL 22 28 41 I/O SPI Slave mode, chip select, active low / I2C clock input
SCK 23 29 42 I SPI Slave mode, clock input
MOSI/SDA 24 30 43 I/O SPI Slave mode, data input / I2C data input and output
MISO 25 31 44 O SPI Slave mode, data output
/RST 26 32 45 I External Reset, Low is active
WAKE 27 33 46 I External interrupt from the host
INT 28 34 47 O External interrupt to the host
NC 48 Not connected
NC 49 Not connected
NC 50 Not connected
NC 51 Not connected
VDDA 30 35 52 PWR Analog power supply
RX1 29 36 53 I Receiver input pins

FT5x06
DATASHEET
RX11 46 63 I Receiver input pins

RX12 47 64 I Receiver input pins
RX13 65 I Receiver input pins
FT5206GE1 Package Diagram FT5306DE4 Package Diagram

VDDA
RX15
RX14
RX12
RX11
RX10
RX16
RX13
RX2
RX1
RX9
RX8
RX7
RX6
RX5
RX4
RX3
63
62
61
60
57
56
55
54
68
67
66
65
64
59
58
53
52
VSSA 1 51 NC
NC 2 50 NC
NC 3 49 NC
TX28 4 48 NC
TX27 5 47 INT
TX26 6 46 WAKE
TX25 7 45 /RST
TX24 8 44 MISO
TX23 9 43 MOSI/SDA
TX22 10 42 SCK
TX21 11 41 SSEL/SCL
TX20 12 40 GPIO3
TX19 13 39 GPIO2
TX18 14 38 GPIO1
TX17 15 37 GPIO0
TX16 16 36 TEST_EN
TX15 17 35 VDDD
20
21
22
23
26
27
28
29
33
34
18
19
24
25
30
31
32
TX13
TX14
TX12
TX11
TX10
VDD5
VDD3
TX9
TX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
VSS
FT5406EE8 Package Diagram

FT5x06
DATASHEET
5 PACKAGE INFORMATION
5.1 Package Information of QFN-5x5-40L Package
Millimeter
Item Symbol
Min Typ Max
Total Thickness A 0.7 0.75 0.8
Stand Off A1 0 0.035 0.05
Mold Thickness A2 ---- 0.55 0.57
L/F Thickness A3 0.203 REF
Lead Width b 0.15 0.20 0.25
D 5 BSC
Body Size
E 5 BSC
Lead Pitch e 0.4 BSC
J 3.5 3.6 3.7
EP Size
K 3.5 3.6 3.7
Lead Length L 0.35 0.4 0.45
Package Edge Tolerance aaa 0.1
Mold Flatness bbb 0.1
Co Planarity ccc 0.08
Lead Offset ddd 0.1
Exposed Pad Offset eee 0.1

FT5x06
DATASHEET
Millimeter
Item Symbol
Min Typ Max
Stand Off A1 0 0.035 0.05
Lead Width b 0.15 0.20 0.25
D 6 BSC
Body Size
E 6 BSC
J 4.1 4.2 4.3
EP Size
K 4.1 4.2 4.3
Co Planarity ccc 0.08
Lead Offset ddd 0.1

FT5x06
DATASHEET
Millimeter
Item Name Symbol
Min Typ Max
Stand Off A1 0 0.035 0.05
Lead Width b 0.15 0.20 0.25
D 8 BSC
Body Size
E 8 BSC
J 6.1 6.2 6.3
EP Size
K 6.1 6.2 6.3
Coplanarity ccc 0.08
Lead Offset ddd 0.1

FT5x06
DATASHEET
5.4 Order Information
QFN
Package Type 40Pin(5 * 5 )/48Pin( 6 * 6 )/68Pin ( 8 * 8 )
0.75 - P0.4
Product Name FT5206GE1/ FT5306DE4/FT5406EE8
Note:
1). The last two letters in the product name indicate the package type and lead pitch and thickness.
2). The second last letter indicates the package type.

D : QFN-6*6 , E : QFN-8*8, G : QFN-5*5
3). The last letter indicates the lead pitch and thickness.
E : 0.75 - P0.4
T: Track Code
F: ”F” for Lead Free process. F T 5x06xxx
TFYWWSV
Y: Year Code
WW: Week Code
Product Name Package Type # TX Pins # RX Pins
FT5206GE1 QFN-40L 15 10
FT5306DE4 QFN-48L 20 12
FT5406EE8 QFN-68L 28 16

FT5x06
DATASHEET
REVISION HISTORY
DDCN# Version Revisions Date
DC-1006004 0.1 First draft 2010-06-11
DC-1006006 0.2 Change FT5206GE1 Package Diagram 2010-06-21
DC-1012001 0.3 Modify block figure, timing and I/O figure 2010-12-20
END OF DATASHEET
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO FOCALTECH SYSTEMS CO.,LTD., AND MAY NOT BE
REPRODUCED, DISCLOSED OR USED IN WHOLE OR PART WITHOUT THE EXPRESS WRITTEN PERMISSION OF
FOCALTECH SYSTEMS CO.,LTD.
Copyright © 2011, FocalTech Systems CO.,Ltd

All rights reserved
Confidential
Application Note for CTPM
Application Note for CTPM

Project name Touch panel
Document ref [Document ref]
Version 0.8
Release date 18 Aug 2010
Owner Xiaoxu Du
Classification Confidential
Distribution List [Distribution list]
Approval
This document contains information proprietary to FocalTech Systems, Ltd., and may not be reproduced,
disclosed or used in whole or part without the express written permission of FocalTech Systems, Ltd.
Copyright © 2010, FocalTech Systems, Ltd

All rights reserved
R3-B4-A, South Area, Shenzhen Hi-Tech Industrial Park,

Shenzhen, Gungdong, P.R. China
ZIP :518057
T +86 755 26588222
F +86 755 26712499
E [email protected]
www.focaltech-systems.com
Confidential
CTPM Application Note
Revision History
Date Version List of changes Author + Signature
18 Jan, 2010 0.1 Initial draft Xiaoxu Du
17 Mar,2010 0.2 Add raw data protocol Xiaoxu Du
22 Mar,2010 0.3 Add system information protocol Xiaoxu Du
26 Mar,2010 0.4 Add calibration related parameters Xiaoxu Du
08 May,2010 0.5 Add information to operating mode Xinming Wang
07 Jul, 2010 0.6 Change Protocol and add information Yunfeng Yuan
18 Aug, 2010 0.7 Modified to release version Xiaoxu Du
22 Dec, 2010 0.8 Modify explanation for register 0xA4 Xiaoxu Du
ii
FocalTech Systems, Ltd. Confidential
Table of Contents
1 I2C Interface .................................................................................................................................... 2
1.1 CTPM interface to Host .................................................................................................................. 2
1.2 I2C Read/Write Interface description .............................................................................................. 2
1.3 Interrupt signal from CTPM to Host ............................................................................................... 3
1.4 Wakeup signal from Host to CTPM ................................................................................................ 4
2 CTP Register Mapping.................................................................................................................... 4
2.1 Operating Mode .............................................................................................................................. 4
2.1.1 DEVICE_MODE ................................................................................................................... 7
2.1.2 GEST_ID ............................................................................................................................... 7
2.1.3 TD_STATUS .......................................................................................................................... 8
2.1.4 TOUCHn_XH (n:1-5) ............................................................................................................ 8
2.1.5 TOUCHn_XL (n:1-5)............................................................................................................. 8
2.1.6 TOUCHn_YH (n:1-5) ............................................................................................................ 9
2.1.7 TOUCHn_YL (n:1-5) ............................................................................................................. 9
2.1.8 ID_G_THGROUP ................................................................................................................. 9
2.1.9 ID_G_THPEAK ..................................................................................................................... 9
2.1.10 ID_G_ THCAL....................................................................................................................... 9
2.1.11 ID_G_ THWATER ................................................................................................................. 9
2.1.12 ID_G_ THTEMP ................................................................................................................... 9
2.1.13 ID_G_ THDIFF ................................................................................................................... 10
2.1.14 ID_G_ CTRL ....................................................................................................................... 10
2.1.15 ID_G_ TIMEENTERMONITOR .......................................................................................... 10
2.1.16 ID_G_ PERIODACTIVE ..................................................................................................... 10
2.1.17 ID_G_ PERIODMONITOR ................................................................................................. 10
2.1.18 ID_G_ AUTO_CLB_MODE ................................................................................................ 10
2.1.19 ID_G_ LIB_VERSION_H .................................................................................................... 11
2.1.20 ID_G_ LIB_VERSION_L ..................................................................................................... 11
2.1.21 ID_G_ CIPHER ................................................................................................................... 11
2.1.22 ID_G_ MODE ..................................................................................................................... 11
2.1.23 ID_G_ PMODE ................................................................................................................... 11
2.1.24 ID_G_ FIRMWARE_ID ....................................................................................................... 11
2.1.25 ID_G_ STATE...................................................................................................................... 11
2.1.26 ID_G_ FT5201ID ................................................................................................................ 12
2.1.27 ID_G_ ERR.......................................................................................................................... 12
2.1.28 ID_G_ CLB.......................................................................................................................... 12
2.2 Test Mode ..................................................................................................................................... 12
2.2.1 DEVICE_MODE ................................................................................................................. 14
2.2.2 ROW_ADDR ........................................................................................................................ 14
2.2.3 ROWDATAN_H ................................................................................................................... 14
2.2.4 ROWDATAN_L.................................................................................................................... 15
2.3 System information Mode ............................................................................................................. 16
2.3.1 DEVICE_MODE ................................................................................................................. 17
2.3.2 BIST_COMM ....................................................................................................................... 17
iii
2.3.3 BIST_STAT .......................................................................................................................... 17

2.3.4 BL_VERH ............................................................................................................................ 17
2.3.5 BL_VERL ............................................................................................................................. 18
2.3.6 FTS_IC_VERH .................................................................................................................... 18
2.3.7 FTS_IC_VERL ..................................................................................................................... 18
2.3.8 APP_IDH............................................................................................................................. 18
2.3.9 APP_IDL ............................................................................................................................. 18
2.3.10 APP_VERH ......................................................................................................................... 19
2.3.11 APP_VERL .......................................................................................................................... 19
2.3.12 CID_n(n:0-4) ....................................................................................................................... 19
3 CTPM Application Introduction ................................................................................................... 20
3.1 Standard Application information of FT5X06 .............................................................................. 20
3.1.1 Standard application circuit of FT5206GE1 ....................................................................... 20
3.1.2 Standard application circuit of FT5306DE4 ....................................................................... 21
3.1.3 Standard application circuit of FT5206EE8 ....................................................................... 22
4 Communication between host and CTPM .................................................................................... 22
4.1 Communication Contents .............................................................................................................. 22
4.2 I2C Example Code ........................................................................................................................ 23
iv
Terminology
CTP – Capacitive touch panel
CTPM – Capacitive touch panel module
1
1 I2C Interface
1.1 CTPM interface to Host
Figure 1-1 shows how CTPM communicates with the Host，there are three kind of communication between
CTPM and Host，we will introduce each communication in this section.
Transfer the data via I2C
Send interrupt when there is a valid touch
Host send Wakeup signal to CTPM
Serial
Interface
TX
CTP
CTP MCU Host
Controller /INT
RX
/WAKE
Figure 1-1 CTPM and Host connection

The Power Supply voltage of CTPM is 2.8V~3.3V, interface supply voltage is 2.8V~3.3V. There are Control
Interface and Data Interface. As
Figure 1-1 demonstrates, Serial interface is the data interface, /INT and /WAKE are
the control interface. For the detail, please refer to Table 1-1.
Table 1-1 Description for TP module and Host interface
Port Name Voltage Polar Description
Serial 2.8~3.3V Serial interface is for data transfer between Host and CTPM.
interface CTPM support both I2C and SPI interface
/INT 2.8~3.3V LOW The interrupt from the CTPM to the Host
/WAKE* 2.8~3.3V LOW Wakeup signal from host to the CTPM
1.2 I2C Read/Write Interface description

Write N bytes to I2C slave
Slave Addr Data Address[X] Data [X] Data [X+N-1]
A A A A A A A R R R R R R R R R D D D D D D D D D D D D D D D D
S A A A … A P
6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
START
WRITE
STOP
ACK
ACK
ACK
ACK
Set Data Address
2
Slave Addr Data Address[X]

A A A A A A A R R R R R R R R R
S A A P
6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0
START
WRITE
STOP
ACK
ACK
Read X bytes from I2C Slave
Slave Addr Data [N] Data [X+N-1]
A A A A A A A R D D D D D D D D D D D D D D D D
S A A … A P
6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
START
STOP
ACK
ACK
ACK
Read
1.3 Interrupt signal from CTPM to Host

As for standard CTPM, host need to use both interrupt control signal and serial data interface to get the touch
data. There are two kind of method to use interrupt: interrupt trigger and interrupt query.
Here is the timing to get touch data.
Touch Start Touch End
/INT
Serial
Data
Data Packet Data Packet Data Packet
Blank …… Blank
0 1 N
Figure 1-2 Interrupt query mode
Touch Start Touch End
/INT
Serial
Data
Data Packet Data Packet Data Packet
Blank …… Blank
0 1 N
Figure 1-3 Interrupt trigger mode
Host use general I2C protocol to read the touch data or the information from CTPM . CTPM will send host a
interrupt signal when there is a valid touch. Then host can use the serial data interface to get the touch data. If
there is no valid touch detected, the /INT will not be pulled up, the host do not need to read the touch data.
NOTE: “valid touch” may have different definition in various systems. For example, in some systems, the valid
touch is defined as there is one more valid touch point. But in some other systems, the valid touch is defined as
one more valid touch with valid gestures. In usual, /INT will be pulled up when there is a valid touch point, and
to be low when a touch finishes.
As for interrupt trigger mode, /INT signal will be low if there is a touch detected. But for per update of valid
touch data, CTPM will produce a valid pulse for /INT signal, host can read the touch data periodically according
to the frequency of this pulse. In this mode, the pulse frequency is the touch data update frequency.
3
1.4 Wakeup signal from Host to CTPM

Host can use the Wakeup Signal to wakeup the I2C slave device.
This pin should be connected to GND when flash programming while in normal running mode it should not be
connected to GND.
2 CTP Register Mapping

This chapter describes the standard FTS Capacitive Touch Panel products communication registers in address
order for each device mode. The most detailed descriptions of the Standard Products communication registers
are in the Register Definitions section of each chapter. The device modes are listed in the table below, along
with each mode’s register prefix.
Device Mode Prefix Val Description
Operating Op 000b Read touch point and gesture
Test Te 100b Read raw data
System Information Sy 001b Read system information related
Reserved
2.1 Operating Mode

In this mode the CTP is fully functional as a touch screen controller. Read and write access address is just
logical address which is not enforced by hardware or firmware. Here is the operating mode register map.
Operating Mode Register Map
Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Host
Access
Op,00h DEVIDE_MODE Device Mode[2:0] RW
Op,01h GEST_ID Gesture ID[7:0] R
Op,02h TD_STATUS Number of R
touch points[3:0]
Op,03h TOUCH1_XH 1stEvent 1st Touch R
Flag X Position[11:8]
Op,04h TOUCH1_XL 1st Touch X Position[7:0] R
Op,05h TOUCH1_YH 1st Touch ID[3:0] 1st Touch R
Y Position[11:8]
Op,06h TOUCH1_YL 1st Touch Y Position[7:0] R
Op,07h
Op,08h
Op,09h TOUCH2_XH 2ndEvent 2ndTouch R
4
Op,0Ah TOUCH2_XL 2nd touch X Position[7:0] R
nd nd
Op,0Bh TOUCH2_YH 2 Touch ID[3:0] 2 Touch R
Y Position[11:8]
Op,0Ch TOUCH2_YL 2nd Touch Y Position[7:0] R
Op,0Dh R
Op,0Eh R
Op,0Fh TOUCH3_XH 3rdEvent 3rd Touch R
Op,10h TOUCH3_XL 3rd Touch X Position[7:0] R
Op,11h TOUCH3_YH 3rd Touch ID[3:0] 3rd Touch R
Y Position[11:8]
Op,12h TOUCH3_YL 3rd Touch Y Position[7:0] R
Op,13h R
Op,14h R
th th
Op,15h TOUCH4_XH 4 Event 4 Touch R
Op,16h TOUCH4_XL 4th Touch X Position[7:0] R
Op,17h TOUCH4_YH 4th Touch ID[3:0] 4th Touch R
Y Position[11:8]
Op,18h TOUCH4_YL 4th Touch Y Position[7:0] R
Op,19h R
Op,1Ah R
th th
Op,1Bh TOUCH5_XH 5 Event 5 Touch R
Op,1Ch TOUCH5_XL 5thTouch X Position[7:0] R
th th
Op,1Dh TOUCH5_YH 5 Touch ID[3:0] 5 Touch R
Y Position[11:8]
Op,1Eh TOUCH5_YL 5th Touch Y Position[7:0] R
Op,1Fh R
Op,20h R
Op,21h Reserved
… …
Op,7Fh Reserved
Op,80h ID_G_THGROUP valid touching detect threshold. R/W
Op,81h ID_G_THPEAK valid touching peak detect threshold. R/W
5
Op,82h ID_G_THCAL the threshold when calculating the focus of touching. R/W
Op,83h ID_G_THWATER the threshold when there is surface water. R/W
Op,84h ID_G_THTEMP the threshold of temperature compensation. R/W
Op,85h R/W
Op,86h ID_G_CTRL Power R/W
control
mode[1:0]
Op,87h ID_G_TIME_ENTER The timer of entering monitor status R/W
_MONITOR
Op,88h ID_G_PERIODACTIVE Period Active[3:0] R/W
Op,89h ID_G_PERIOD The timer of entering idle while in monitor status R/W
MONITOR
Op,8Ah R/W
Op,8Bh R/W
Op,8Ch R/W
Op,8Dh R/W
Op,8Eh R/W
Op,8Fh R/W
Op,90h R/W
Op,91h R/W
Op,92h R/W
Op,93h R/W
Op,94h R/W
Op,95h R/W
Op,96h R/W
Op,97h R/W
Op,98h R/W
Op,99h R/W
Op,9Ah R/W
Op,9Bh R/W
Op,9Ch R/W
Op,9Dh R/W
Op,9Eh R/W
Op,9Fh R/W
Op,A0h ID_G_AUTO_CLB auto calibration mode R/W
_MODE
6
Op,A1h ID_G_LIB_ Firmware Library Version H byte R

VERSION_H
Op,A2h ID_G_LIB Firmware Library Version L byte R
_VERSION_L
Op,A3h ID_G_CIPHER Chip vendor ID R
Op,A4h ID_G_MODE the interrupt status to host R
Op,A5h ID_G_PMODE Power Consume Mode
Op,A6h ID_G_FIRMID Firmware ID R
Op,A7h ID_G_STATE Running State
Op,A8h ID_G_FT5201ID CTPM Vendor ID R
Op,A9h ID_G_ERR Error Code R
Op,AAh ID_G_CLB Configure TP module during calibration in Test Mode R/W
Op,ABh R/W
Op,ACh R/W
Op,ADh R/W
Op,AEh ID_G_B_AREA_TH The threshold of big area R/W
Op,AFh R/W
… …
Op,FDh Reserved
Op,FEh LOG_MSG_CNT The log MSG count R
Op,FFh LOG_CUR_CHA Current character of log message, will point to the next R
character when one character is read.
2.1.1 DEVICE_MODE
This register is the device mode register, configure it to determine the current mode of the chip.
Address Bit Address Register Name Description
Op,00h 6:4 Device Mode 000b Normal operating Mode
[2:0] 001b System Information Mode (Reserved)
100b Test Mode – read raw data (Reserved)
2.1.2 GEST_ID
This register describes the gesture of a valid touch.
Op,01h 7:0 Gesture ID Gesture ID
[7:0] 0x10 Move UP
7
0x14 Move Left

0x18 Move Down
0x1C Move Right
0x48 Zoom In
0x49 Zoom Out
0x00 No Gesture
2.1.3 TD_STATUS
This register is the Touch Data status register.
Op,02h 3:0 Number of touch How many points detected.
points[3:0] 1-5 is valid.
7:4
2.1.4 TOUCHn_XH (n:1-5)

This register describes MSB of the X coordinate of the nth touch point and the corresponding event flag.
Op,03h 7:6 Event Flag 00b: Put Down
~ 01b: Put Up
Op,39h 10b: Contact
11b: Reserved
5:4 Reserved
3:0 Touch X Position MSB of Touch X Position in pixels
[11:8]
2.1.5 TOUCHn_XL (n:1-5)

This register describes LSB of the X coordinate of the nth touch point.
Op,04h 7:0 Touch X Position LSB of the Touch X Position in pixels
~ [7:0]
Op,3Ah
8
2.1.6 TOUCHn_YH (n:1-5)

This register describes MSB of the Y coordinate of the nth touch point and corresponding touch ID.
Op,05h 7:4 Touch ID[3:0] Touch ID of Touch Point
~
3:0 Touch X Position MSB of Touch Y Position in pixels
Op,3Bh
[11:8]
2.1.7 TOUCHn_YL (n:1-5)

This register describes LSB of the Y coordinate of the nth touch point.
Op,06h 7:0 Touch X Position LSB of The Touch Y Position in pixels
~ [7:0]
Op,3Ch
2.1.8 ID_G_THGROUP
This register describes valid touching detect threshold.
Op,80h 7:0 ID_G_THGROUP The actual value will be 4 times of the register’s
value. Default:280/4
2.1.9 ID_G_THPEAK
This register describes valid touching peak detect threshold.
Op,81h 7:0 ID_G_ THPEAK Default:60
2.1.10 ID_G_ THCAL

This register describes threshold when calculating the focus of touching.
Op,82h 7:0 ID_G_ THCAL Default:16
2.1.11 ID_G_ THWATER

This register describes threshold when there is surface water.
Op,83h 7:0 ID_G_ THWATER Default:60
2.1.12 ID_G_ THTEMP

This register describes threshold of temperature compensation.
9

Op,84h 7:0 ID_G_ THTEMP Default:10
2.1.13 ID_G_ THDIFF

This register describes threshold whether the coordinate is different from the original.
Op,85h 7:0 ID_G_ THDIFF The actual value must be 32timers of
the register’s value. Default :20
2.1.14 ID_G_ CTRL

This register describes the run mode of microcontroller controlled by host
Op,86h 0 ID_G_ CTRL 0: not auto jump 1:auto jump
2.1.15 ID_G_ TIMEENTERMONITOR

This register describes the time delay value when entering monitor status.
Op,87h 7:0 ID_G_TIME Default :2
ENTERMONITOR
2.1.16 ID_G_ PERIODACTIVE

This register describes the period of active status, it should not less than 12
Op,88h 4:0 ID_G_ PERIOD Range form 3 to 14,default 12
ACTIVE
7:4
2.1.17 ID_G_ PERIODMONITOR

This register describes period of monitor status, it should not less than 30.
Op,89h 7:0 ID_G_ PERIOD Default:40
MONITOR
2.1.18 ID_G_ AUTO_CLB_MODE

This register describes auto calibration mode.
Op, A0h 7:0 ID_G_ AUTO_ 8’h 00: enable auto calibration
10
CLB_MODE 8’h ff: disable auto calibration
2.1.19 ID_G_ LIB_VERSION_H

This register describes library version high byte.
Op, A1h 7:0 ID_G_LIB_VERSION_H R: xx
2.1.20 ID_G_ LIB_VERSION_L

This register describes library version low byte.
Op, A2h 7:0 ID_G_ LIB_VERSION_L R: xx
2.1.21 ID_G_ CIPHER

This register describes vendor’s chip id.
OP, A3h 7:0 ID_G_ CIPHER R: xx
2.1.22 ID_G_ MODE

This register describes the interrupt status to host.
Op,A4h 7:0 ID_G_ MODE 0: Polling mode
1: Trigger mode
2.1.23 ID_G_ PMODE

This register describes the power consumption mode of the TPM when in running status.
Op,A5h 7:0 ID_G_ PMODE 0: active
1: monitor
3: hibernate(deep sleep)
2.1.24 ID_G_ FIRMWARE_ID

This register describes the firmware id of the application.
Op,A6h 7:0 ID_G_ FIRMWARE_ID R: xx
2.1.25 ID_G_ STATE

This register is used to configure the run mode of TPM.
11
Op,A7h 7:0 ID_G_ STATE 0: configure

1: work
2: calibration
3: factory
4: auto calibration
2.1.26 ID_G_ FT5201ID

This register describes vendor’s chip id
Op,A8h 7:0 ID_G_ R: xx
FT5201ID
2.1.27 ID_G_ ERR

This register describes the error code when the TPM is running.
Op,A9h 7:0 ID_G_ ERR ERR Code
8’h00:OK
8’h03:chip register writing inconsistent with
reading
8’h05:chip start fail
8’h1A:no match among the basic input(such as
TX_ORDER) while calibration
2.1.28 ID_G_ CLB

This register is used to configure the TPM when Calibration
Op,AAh 7:0 ID_G_ CLB Mapping the Array of G_Bank1, total length is
NUM_TX+NUM_RX+1. the array address
increases 1 after every write.
2.2 Test Mode

In this mode, CTP will provide some panel related information. Host can get the following information in this
mode
Raw data of touch panel
Panel configure related information
Test Mode Register Map
Access
Te,00h DEVIDE_MODE Data Device Mode[2:0] RW
Read
Toggle
12
Te,01h ROW_ADDR The address of the row to be read RW

Te,02h START_SCAN Start the scan command, the value stands for the scan frequency, RW
will be set to zero when scan finishes
Te,03h ROW_NUM Panel row number RW
Te,04h COL_NUM Panel column number RW
Te,05h DRIVER_VOL Driver voltage of chip RW
Te,06h START_RX Setting the RX start number RW
Te,07h GAIN Control the difference value for touching RW
Te,08h ORIGIN_XH High byte of origin X coordinate RW
Te,09h ORIGIN_XL Low byte of origin X coordinate RW
Te,0Ah ORIGIN_YH High byte of origin Y coordinate RW
Te,0Bh ORIGIN_YL Low byte of origin Y coordinate RW
Te,0Ch RES_WH High byte of width of resolution RW
Te,0Dh RES_WL Low byte of width of resolution RW
Te,0Eh RES_HH High byte of height of resolution RW
Te,0Fh RES_HL Low byte of height of resolution RW
Te,10h RAWDATA0_H High byte of raw data 0 R
Te,11h RAWDATA0_L Low byte of raw data 0 R
Te,12h RAWDATA1_H High byte of raw data 1 R
Te,13h RAWDATA1_L Low byte of raw data 1 R
… … …
Te,4Ah RAWDATA29_H High byte of raw data 29 R
Te,4Bh RAWDATA29_L Low byte of raw data 29 R
Te,4Ch TH_POINT_NUM Touch point number support RW
Te,4Dh Reserved
Te,4Eh Reserved
Te,4Fh Reserved
Te,50h TX_ORDER_0 TX Order, start from zero RW
Te,51h TX_ORDER_1 RW
… … … RW
Te,77h TX_ORDER_39 RW
Te,78h ROW0_CAC Charge Amplifier feedback Capacitance of ROW0 RW
Te,79h ROW1_CAC Charge Amplifier feedback Capacitance of ROW1 RW
… … …
Te,9Fh ROW39_CAC Charge Amplifier feedback Capacitance of ROW39 RW
13
Te,A0h COL0_CAC Charge Amplifier feedback Capacitance of COL0 RW

… … …
Te,BEh COL29_CAC Charge Amplifier feedback Capacitance of COL29 RW
Te,BFh ROW0_1_OFFSET Offset of ROW1 Offset of ROW0 RW
… … … …
Te,D2h ROW38_39_OFFSET Offset of ROW39 Offset of ROW38 RW
Te,D3h COL0_1_OFFSET Offset of COL1 Offset of COL0 RW
… … … …
Te,E1h COL28_29_OFFSET Offset of COL29 Offset of COL28 RW
… …
Te,FEh LOG_MSG_CNT The log MSG count R
Te,FFh LOG_CUR_CHA Current character of log message, will point to the next character R
when one character is read.
2.2.1 DEVICE_MODE
Te,00h 7 Data Read Toggle This bit is toggled by the Host only when a data
transfer between the Host and TrueTouch
device
requires register based handshaking.
6:4 Device Mode[2:0] 000b Normal operating Mode
001b System Information Mode (Reserved)
2.2.2 ROW_ADDR
Te,01h 7:0 Row address The address of the row to be read
Please delay for more than 100us, then read the
raw data
2.2.3 ROWDATAN_H
Te,(10+2n)h 7:0 High byte of raw data N High byte of raw data N
14
If N exceeds the column number will return

0xff
2.2.4 ROWDATAN_L
Te,(10+2n+1)h 7:0 Low byte of raw data N Low byte of raw data N
If N exceeds the column number will return
0xff
15
2.3 System information Mode

This mode provides access to all of the one-time system information. The system information is either written
by the host to permanently configure the device (for example, power timers), or is written to the device at
compile time for the host to read (for example, application version). To enter BIST (built in self test) mode write
the BIST command required into the BIST_COMM register.
Read and write access is theoretical and is not enforce by hardware or firmware. Words have their MSB at lower
address.
System Information Mode Register Map

Access
Sy,00h DEVIDE_MODE Data Device Mode[2:0] RW
Read
Toggle
Sy,01h BIST_COMM BIST Command[7:0] W
Sy,02h BIST_STAT BIST Status[7:0] R
Sy,03h Unused
Sy,04h Unused
Sy,05h Unused
Sy,06h Unused
Sy,07h UID_0 Unique Silicon ID #0[7:0] R
Sy,0Ah UID_3 Unique Silicon ID #3[7:0] R
Sy,0Bh UID_4 Unique Silicon ID #4[7:0] R
Sy,0Ch UID_5 Unique Silicon ID #5[7:0] R
Sy,0Dh UID_6 Unique Silicon ID #6[7:0] R
Sy,0Eh UID_7 Unique Silicon ID #7[7:0] R
Sy,0Fh BL_VERH Bootloader version[15:8] R
Sy,10h BL_VERL Bootloader version[7:0] R
Sy,11h FTS_IC_VERH Focal Tech IC Version[15:8] R
Sy,12h FTS_IC_VERL Focal Tech IC Version[7:0] R
Sy,13h APP_IDH Application ID[15:8] R
Sy,14h APP_IDL Application ID[7:0] R
Sy,15h APP_VERH Application Version[15:8] R
Sy,16h APP_VERL Application Version[7:0] R
Sy,17h Unused
Sy,18h Unused
16
Sy,19h Unused
Sy,1Ah Unused
Sy,1Bh CID_0 Custom ID #0[0:7] R
Sy,1Ch CID_1 Custom ID #1[0:7] R
Sy,1Dh CID_2 Custom ID #2[0:7] R
Sy,1Eh CID_3 Custom ID #3[0:7] R
Sy,1Fh CID_4 Custom ID #4[0:7] R
… …
Sy,FEh LOG_MSG_CNT The log MSG count R
Sy,FFh LOG_CUR_CHA Current character of log message, will point to the next character when R
one character is read.
2.3.1 DEVICE_MODE
Sy,00h 6:4 Device Mode[2:0] 000b Normal operating Mode
001b System Information Mode (Reserved)
2.3.2 BIST_COMM
This register is the BIST command register. The BIST (built in self test) function to perform is set here.
Sy,01h 7:0 BIST Command[7:0] BIST command to perform.
2.3.3 BIST_STAT
This register reports the status of BIST (built in self test) functions either in progress or the last function
completed.
Sy,02h 7:0 BIST Command[7:0] Status of the last BIST function started.
2.3.4 BL_VERH
This register contains the MSB of the bootloader version specified by the application.
Sy,0Fh 7:0 Bootloader version[15:8] R:xx
17
2.3.5 BL_VERL
This register contains the LSB of the bootloader version specified by the application.
Sy,10h 7:0 Bootloader version[7:0] R:xx.
2.3.6 FTS_IC_VERH
This is the FTS IC version register. This register contains the MSB of the FTS IC version. The value is BCD
value, for example
FT5201 – FTS_IC_VERH(0x52), FTS_IC_VERL(0x01)
Sy,11h 7:0 Focal Tech IC version Focal Tech IC Version MSB
[15:8]
2.3.7 FTS_IC_VERL
This is the FTS IC version register. This register contains the MSB of the FTS IC version. The value is BCD
value, for example
Sy,12h 7:0 Focal Tech IC version [7:0] Focal Tech IC Version LSB
2.3.8 APP_IDH
This is the application ID register. This register contains the MSB of the application ID. This value is set to
designate the individual project.

Sy,13h 7:0 Application Version [15:8] R:xx
2.3.9 APP_IDL
This is the application ID register. This register contains the MSB of the application ID. This value is set to
designate the individual project.
18

2.3.10 APP_VERH
This is the application version register. This register contains the MSB of the application version. This value
should be incremented on each internal or external release of the project.

2.3.11 APP_VERL
This is the application version register. This register contains the LSB of the application version. This value
should be incremented on each internal or external release of the project.
Address Bit Addr. Reg. Name Description

2.3.12 CID_n(n:0-4)
These are Custom ID registers. These regitsters contain user defined Custom ID identifiers for the FT TPM.
Address Bit Addr. Reg. Name Description

Sy,1Bh~1Fh 7:0 Application Version [7:0] R:xx
19
3 CTPM Application Introduction
3.1 Standard Application information of FT5X06

Figure3-1,Figure3-2,Figure3-3 demonstrate the typical FT5x06 application schematic. It consists of FT’s
Capacitive Touch Panel(CTP), FT5X06 chip, and some peripheral components. According to the size of CTPM,
you can choose the numbers of TX and RX needed.
3.1.1 Standard application circuit of FT5206GE1
Figure 3-1 FT5206GE1 typical application schematic
20
3.1.2 Standard application circuit of FT5306DE4
Figure 3-2 FT5306DE4 typical application schematic
21
3.1.3 Standard application circuit of FT5206EE8
Figure 3-3 FT5406EE8 typical application schematic
4 Communication between host and CTPM
4.1 Communication Contents

The data Host received from the CTPM through serial interface are different depend on the configuration in
Device Mode Register of the CTPM. Please refer to Section 2---CTP Register Mapping.
22
4.2 I2C Example Code

/////////////////////////////////////////////////////////////////
// I2C write bytes to device.
//
// Arguments: ucSlaveAdr - slave address
// ucSubAdr - sub address
// pBuf - pointer of buffer
// ucBufLen - length of buffer
/////////////////////////////////////////////////////////////////
void i2cBurstWriteBytes(BYTE ucSlaveAdr, BYTE ucSubAdr, BYTE *pBuf, BYTE ucBufLen)
{
BYTE ucDummy; // loop dummy
ucDummy = I2C_ACCESS_DUMMY_TIME;
while(ucDummy--)
{
if (i2c_AccessStart(ucSlaveAdr, I2C_WRITE) == FALSE)
continue;
if (i2c_SendByte(ucSubAdr) == I2C_NON_ACKNOWLEDGE) // check non-acknowledge
continue;
while(ucBufLen--) // loop of writting data
{
i2c_SendByte(*pBuf); // send byte
pBuf++; // next byte pointer
} // while
break;
} // while
i2c_Stop();
}
/////////////////////////////////////////////////////////////////
// I2C read bytes from device.
//
// ucSubAdr - sub address
/////////////////////////////////////////////////////////////////
void i2cBurstReadBytes(BYTE ucSlaveAdr, BYTE ucSubAdr, BYTE *pBuf, BYTE ucBufLen)
{
while(ucDummy--)
23
{
if (i2c_AccessStart(ucSlaveAdr, I2C_WRITE) == FALSE)
continue;
if (i2c_SendByte(ucSubAdr) == I2C_NON_ACKNOWLEDGE) // check non-acknowledge
continue;
if (i2c_AccessStart(ucSlaveAdr, I2C_READ) == FALSE)
continue;
while(ucBufLen--) // loop to burst read
{
*pBuf = i2c_ReceiveByte(ucBufLen); // receive byte
} // while
break;
} // while
i2c_Stop();
}
/////////////////////////////////////////////////////////////////
// I2C read current bytes from device.
//
/////////////////////////////////////////////////////////////////
void i2cBurstCurrentBytes(BYTE ucSlaveAdr, BYTE *pBuf, BYTE ucBufLen)
{
while(ucDummy--)
{
if (i2c_AccessStart(ucSlaveAdr, I2C_READ) == FALSE)
continue;
while(ucBufLen--) // loop to burst read
{
*pBuf = i2c_ReceiveByte(ucBufLen); // receive byte
} // while
break;
} // while
i2c_Stop();
}
24

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FT5x06

FocalTech Systems Co., Ltd · www.focaltech-systems.com · [email protected]

Document Number: D-FT5x06-1005 (Version: 0.4) Revised DEC 20, 2010

From No.: F-OI-RD01-03-03-B

5 PACKAGE INFORMATION.......................................................................................................................................... 15

FocalTech Systems Co., Ltd · www.focaltech-systems.com · [email protected]

Document Number: D-FT5x06-1005 (Version: 0.4) Revised DEC 20, 2010

From No.: F-OI-RD01-03-03-B

Figure2-1 shows the overall architecture for the FT5x06.

Figure 2-1 FT5x06 System Architecture Diagram

The FT5x06 is comprised of five main functional parts listed below,

FocalTech Systems Co., Ltd Version 0.4︱Page 1 of 21

z Touch Panel Interface Circuits

Figure 2-2 MCU Block Diagram

FocalTech Systems Co., Ltd Version 0.4︱Page 2 of 21

2.4 Host Interface

Figure 2-3 Host Interface Diagram

2.5 Serial Interface

Figure 2-4 I2C Serial Data Transfer Format

FocalTech Systems Co., Ltd Version 0.4︱Page 3 of 21

Figure 2-5 I2C master write, slave read

Figure 2-6 I2C master read, slave write

Table 2-1 Mnemonics Description

I2C Interface Timing Characteristics is shown in Table 2-2.

Table 2-2 I2C Timing Characteristics

Parameter Unit Min Max

FocalTech Systems Co., Ltd Version 0.4︱Page 4 of 21

Figure 2-7 SPI Data Transfer Format (Phase=0, POLCK=0)

Figure 2-8 SPI Data Transfer Format (PHASE=0, POLCK=1)

Figure 2-10 SPI Data Transfer Format (Phase=1, POLCK=1)

FocalTech Systems Co., Ltd Version 0.4︱Page 5 of 21

Figure 2-12 SPI master Timing PHASE =1

FocalTech Systems Co., Ltd Version 0.4︱Page 6 of 21

Figure 2-13 SPI slave Timing PHASE = 0

Figure 2-14 SPI slave Timing PHASE = 1

Table 2-3 SPI Timing Parameters

Parameter Description Min Max Units

FocalTech Systems Co., Ltd Version 0.4︱Page 7 of 21

Tmsrc last sck edge to slvsel rising edge (Tmckh+Tmckl)/2 -- ns

Slave mode timing(See figure 2-13,2-14)

Item Symbol Unit Value Note

FocalTech Systems Co., Ltd Version 0.4︱Page 8 of 21

Table 3-2 DC Characteristics (VDDA=VDD3=2.8~3.6V, Ta=-40~85℃)

Item Symbol Unit Test Condition Min. Typ. Max. Note

Input low -level voltage VIL V -0.3 -- 0.3 x IOVCC

Output high -level voltage VOH V IOH=-0.1mA 0.7 x IOVCC -- --

Output low -level voltage VOL V IOH=0.1mA -- -- 0.3 x IOVCC

I/O leakage current ILI μA Vin=0~VDDA -1 -- 1

Step-up output voltage VDD5 V VDDA=VDD3= 2.8V 5 5.25 5.6

Item Symbol Unit Test Condition Min. Typ. Max. Note

Table 3-4 AC Characteristics of TX & RX

TX output rise time Ttxr nS -- 20 --

TX output fall time Ttxf nS -- 20 --

RX input voltage Trxi V 1.2 -- 1.6

FocalTech Systems Co., Ltd Version 0.3 ︱Page 9 of 21

FocalTech Systems Co., Ltd Version 0.3 ︱Page 10 of 21

3.5 POWER ON/Reset/Wake Sequence

Figure 3-7 Power on time

Figure 3-8 Power on Sequence