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Design of Digital Clock Calendar Using FPGA

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IETE 45th Mid Term Symposium on Broadband-Technologies and Services for Rural India MTS 14, 4th and 5th April, 2014

Design of Digital Clock Calendar Using FPGA

M. Senthil Sivakumar, R. Thandaiah Prabu and I. Jayanandan

Abstract---A design of digital clock calendar is a popular billions of bits of information in a relatively small space. The
research work that exploited to digitize the life perfectly. Various Clock-Calendar Design is developed to using counters,
design methods are employed in the design of digital clock calendar comparators, decoders and multiplexers together. In this
to improve the performance with reduced power dissipation. This FPGA based digital clock calendar instead of using ready
paper proposes the new technique that improve the performance and
reduce the power dissipation of the digital clock calendar. The
components for counters, comparator, decoder and
proposed digital clock calendar design is enhanced using the digital multiplexers are used. The ready module units have been
blocks: counter, comparator, multiplier and a decoder. The digital redesigned so that instructive capacities of examples have
blocks have been implemented with Verilog HDL and synthesized in been increased.
Xilinx design tool using 90nm technology file. The outputs are Ref. [1] reports on a series of qualitative interviews
verified and demonstrated in Spartan®-6 FPGA SP605 Evaluation conducted as an exploratory research effort to understand the
Kit.
motivations behind knowledge workers’ usage of mobile
digital calendars. To find the report of digital calendar Semi-
Keywords---Digital System, Clock Calendar, FPGA, HDL.
structured interviews were conducted by the authors with
fifteen professionals who are regular users of mobile digital
I. INTRODUCTION
calendars, and have been using their system of choice. In [2],
PGAS (Field Programmable Gate Arrays) are popularly
F used in the digital design laboratories to develop and
reconfigure various applications. The special procedures
authors have been compared the digital clock approach with
the SOP which was proposed by National Institute of
Standards and Technology (NIST). Finally, they found that
used in design of digital system using FPGA made it as an the use of trusted third party forensics tools is important to
attractive demonstration kit for Electronics, IC and collect, analyze and examine digital evidences.
communication engineers and universities over in the world. An all-digital clock generator for dynamic frequency
Also it is perfectly matching in the design of high scaling is presented by using a cyclic clock multiplier. It
performance digital systems and their demonstrations. The realizes the fractional or multiplied output clock within four
instructive devices like clock calendar, CPU, digital reference clock cycles. The authors of [3] were proposed the
calculators, digital telephone, digital computer, etc are some clock generator for dynamic clock generator scaling. A
important examples for FPGA based system designs. The portable clock generator, which solves the duty ratio and jitter
extreme importance of high performance, low power and problems of the input clock, has been developed. In the
flexibility in the design of digital systems can be achieved by proposed clock generator, the complementary delay line
driving the technology into the leap of invention in integrated generates a series of multiphase clocks. The realization of
circuits using FPGA. Normally, the special blocks of a system digital clock generator was obtained by the authors of [4] in a
are implemented separately using Hardware Description 0.18-mum CMOS process technology. The integration of
Language (HDL). And then they are verified using the design digital clock generator, counter, comparator and multiplexer
tools like Xilinx, Cadence, etc. The designed sub blocks are provides the better performance FPGA based digital clock
integrated together to demonstrate on FPGA. calendar. The design of FPGA based clock manager was
The advances in digital technology have been phenomenal obtained in [5] for sub-nanosecond phase shifts for lidar
over the years and that giving birth to digital system design applications. Segmented Digital Clock Manager- FPGA based
which continue to serve as a great source of succour and Digital Pulse Width Modulator Technique is realized in [6] in
comfort to mankind in many ways. These days, numerous virtex-4 FPGA board. This can be applied to achieve various
applications in Electronics and other technologies are using number of bits for the DPWM resolution.
digital techniques to perform operations that were once FPGA implementation of a fully digital CDR for
performed by analogue methods. The digital systems owe the plesiochronous clocking systems were implemented and
versatility and superiority over analogue methods to the fact demonstrated in [7] for digital clock and recovery system.
that they do not get affected by spurious fluctuations in Window-Masked Segmented Digital Clock Manager-FPGA-
voltage; have greater precision and accuracy; and can store Based Digital Pulse width Modulator Technique was proposed
in [8]. The proposed digital pulse width modulator (DPWM)
M. Senthil Sivakumar, National Institute of Technology, Puduchery, E- architecture is first simulated, implemented, and
Mail: [email protected]
R. Thandaiah Prabu, Department of ECE, Prathyusha Institute of experimentally verified on a Virtex-4 FPGA board. A
Technology and Management E-Mail: [email protected], prototype clock system is developed in [9] for Water
I. Jayanandan, Department of ECE, Prathyusha Institute of Technology and Cherenkov Detector Array (WCDA) in the Large High
Management E-Mail: [email protected],

ISBN 978-1-941505-03-8 © 2014 Published by Coimbatore Institute of Information Technology

IETE 45th Mid Term Symposium on Broadband-Technologies and Services for Rural India MTS 14, 4th and 5th April, 2014

Altitude Air Shower Observatory (LHAASO) project. The present state. Then for each count of maximum minute one
experiment was demonstrated by the use of virtex-4 FPGA hour will be increased by assigning minutes to 0 back. When
board. We have proposed the new architecture for digital hour reached to maximum value 24 day will be incremented.
clock calendar which consists of only counter, multiplexer, Days get incremented by one from the previous value every
comparator and a decoder. The use of simple functional block time the hour reaches to 24 and the hour will be assigned by 0
increases the system performance with less clock delay and that starts count from beginning with seconds, and minutes.
reduces the size with smaller area. The block diagram and In the digital calendar increment of day must be defined
logic implementation of proposed digital clock calendar is carefully since the months are incorporated different number
illustrated detail in following sections of days with it. When the days are reaching to the maximum
number in the month then the day has to be initiated by 0 with
II. DIGITAL CLOCK CALENDAR the increment in a month. Month increases whenever the day’s
The block diagram of Digital Clock Calendar is shown in reaches to the maximum number defined for the particular
Fig 1. It consists of a counter, comparator, multiplexer and month. The total delay between the months is defined by the
decoder. In the clock calendar, counter performs the clock delay of seconds/minutes/hours/days. When the months are
count with constant frequency/time period. The time period is reaching to the maximum number 12 then the month will be
defined by the clock generator that employed inside the initiated to 0 with the increment in a year. Year increases
counter. The clock generator generates the pulse of signal with whenever the months reach to the maximum number defined
rise and fall time transitions with described time interval. The for year (12). The total delay between the years is defined by
counter can be defined to count the rise time or fall time the delay of seconds/ minutes/ hours/ days/ months.
transition of the clock pulse. For every rice/fall time transition The logic multiplexer present in the digital clock calendar
the counter increases one with the present value. In this selects the count part seconds/ minutes/ hours/ days/ months/
proposed design the counter is defined to count the rise time years that to be incremented at the rise edge of clock pulse.
transition i.e., for every change of clock signal from logic 0 to The selection line defines which line has to be incremented by
logic 1 the counter increases the value by one, which helps to the counter for the response of rise time transition of clock
fix the second count of the circuit. Each second increment in signal.
the digital calendar is defined by increasing the count. The Comparator present in the digital calendar identifies the
time delays between the seconds are defined by the time maximum allowable integer value for seconds/ minutes/
period of the clock signal. In this way the counter increases hours/ days/ months/ years. Based on the comparison result
the count by one for every rise edge of clock pulse. When the from the comparator the digital counter counts are initiated to
count value in second reaches the value 60, the second value 0 with the increment of next higher order parameter.
has been assigned back to 0 with the increment in minutes. The digital clock calendar counts seconds/ minutes/ hours/
Again the seconds counted from beginning to maximum value days/ months/ years for the response of rise edge transition of
and then the count will be fixed with initial value by clock signal. The outputs generated by the digital clock
increasing the minutes by one from the present state. calendar sent to the seven segment display through the
decoder. The decoder decodes the decimal input into binary
code and then load as input to the seven segment display. The
display shows the seconds/minutes/hours/days/months /years
that obtained from the clock calendar.
The logic blocks and logics are implemented using
hardware description language and simulated to verify the
logic output. The simulation results are described in the next
section that demonstrates the logic implementation of Digital
clock calendar.

III. RESULT ANALYSIS

The proposed functional blocks of FPGA based digital
Fig.1. Block diagram of Digital Clock Calendar clock calendar are implemented by using hardware description
language. And the outputs are analyzed by comparing with
Similarly to seconds, the minutes value has been increased theoretical portion that ensures the high performance digital
with the some constant time delay that described by 60 set of clock calendar operation as expected. The simulations have
seconds delay. When minute reaches to the maximum value been performed in Modelsim simulator that verifies the logic
60 then the minute value will be set into initial value 0 by outputs of digital clock calendar as shown in Fig
increasing one value in hour. Again the minutes counted from Fig 2(a) shows the simulation result of increment in second
beginning to maximum value and then the count will be fixed for the response of rise edge clock signal with constant time
with initial value by increasing the hour by one from the period. The second gets incremented for each rise edge of

ISBN 978-1-941505-03-8 © 2014 Published by Coimbatore Institute of Information Technology

IETE 45th Mid Term Symposium on Broadband-Technologies and Services for Rural India MTS 14, 4th and 5th April, 2014

clock by one. When it reaches the maximum number 60,

second will be assigned with initial value 0 with one
increment in minute.
Fig 2(b) shows the simulation result of increment in
minutes for the response of maximum allowable value of
second with constant time period. Minute gets incremented by
one for each maximum value of second at 60. When minute
reaches the maximum number 60, it will be assigned with
initial value 0 with one increment in hour.

(c) Simulation result for Increment of Hour

(a) Simulation result for Increment of Sec

(d) Simulation result for Increment of Days

Fig 2(e) shows the simulation result of increment in month
for the response of maximum allowable value of days with
constant time period. Month gets incremented by one for each
maximum value of day at 30. When month exceeds the
maximum number 12, it will be assigned with initial value 1
with one increment in year.

(b) Simulation result for Increment of Min

Fig 2(c) shows the simulation result of increment in hour

for the response of maximum allowable value of minute with
constant time period. Hour gets incremented by one for each
maximum value of minute at 60. When hour reaches the
maximum number 24, it will be assigned with initial value 0
with one increment in day.
Fig 2(d) shows the simulation result of increment in day for
the response of maximum allowable value of hour with
constant time period. Day gets incremented by one for each
maximum value of hour at 24. When day exceeds the
(e) Simulation result for Increment of Month
maximum number 30, it will be assigned with initial value 1
Fig 2(f) shows the simulation result of increment in year for
with one increment in month.
the response of maximum allowable value of month with
constant time period. Year gets incremented by one for each
maximum value of month at 12.

ISBN 978-1-941505-03-8 © 2014 Published by Coimbatore Institute of Information Technology

IETE 45th Mid Term Symposium on Broadband-Technologies and Services for Rural India MTS 14, 4th and 5th April, 2014

block are obtained as shown in Fig.3. Fig 3.(a) shows the

Synthesized output of Counter Block which consists of logic
gates, flip-flops and multiplexer. The input and output ports
are also illustrates as in the logic used to develop the HDL
program. The logic outputs are obtained from the parallel
connected flip-flops as represented in the figure.
Fig 3(b) shows the synthesized output of Counter circuit
with comparator which consists of logic gates, flip-flops,
counter and comparator. The input and output ports are also
illustrates as in the logic used to develop the HDL program.
(f) Simulation result for Increment of Year
The logic outputs are obtained from the parallel OR gate
Fig.2. Step by Step Simulation result of Digital clock calendar using through comparators and flip-flops as represented in the
Modelsim figure.

Fig.3(a). Synthesized output of Counter Block

Fig.3(c). Synthesized output of Counting Circuit of Digital Clock

Calendar
Fig 3(c) shows the synthesized output of counting circuit of
digital clock calendar which consists of series connected
conditional counter. The input and output ports are also
illustrates as in the logic used to develop the HDL program.
The logic outputs are obtained from the output terminals of
series connected counters as represented in the figure.
Fig 3(d) shows the synthesized output of full digital clock
calendar which consists of logic gates, flip-flops, counter,
multiplexer, comparator and series connected conditional
counter. The input and output ports are also illustrates as in
the logic used to develop the HDL program. The logic outputs
are obtained from the output terminals of series connected
counters as represented in the figure.
Fig.3(b). Synthesized output of Count Circuit with Comparison
operation IV. CONCLUSION
The HDL programs are synthesized using Xilinx design In this paper, the high performance digital clock calendar
tool to obtain the block diagram of each block. The logic design is proposed with reduced core area. The block diagram

ISBN 978-1-941505-03-8 © 2014 Published by Coimbatore Institute of Information Technology

IETE 45th Mid Term Symposium on Broadband-Technologies and Services for Rural India MTS 14, 4th and 5th April, 2014

of clock calendar is designed with the combination of REFERENCES

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ISBN 978-1-941505-03-8 © 2014 Published by Coimbatore Institute of Information Technology

IETE 45th Mid Term Symposium on Broadband-Technologies and Services for Rural India MTS 14, 4th and 5th April, 2014

Fig 3.(d). Synthesized output of Digital Clock Calendar

ISBN 978-1-941505-03-8 © 2014 Published by Coimbatore Institute of Information Technology

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