Leakage Current Mechanisms and Leakage

Reduction Techniques in Deep-Submicrometer

CMOS Circuits
KAUSHIK ROY, FELLOW, IEEE, SAIBAL MUKHOPADHYAY, STUDENT MEMBER, IEEE, AND
HAMID MAHMOODI-MEIMAND, STUDENT MEMBER, IEEE

Contributed Paper

High leakage current in deep-submicrometer regimes is be-

coming a significant contributor to power dissipation of CMOS
circuits as threshold voltage, channel length, and gate oxide thick-
ness are reduced. Consequently, the identification and modeling
of different leakage components is very important for estimation
and reduction of leakage power, especially for low-power appli-
cations. This paper reviews various transistor intrinsic leakage
mechanisms, including weak inversion, drain-induced barrier
lowering, gate-induced drain leakage, and gate oxide tunneling.
Channel engineering techniques including retrograde well and
halo doping are explained as means to manage short-channel
effects for continuous scaling of CMOS devices. Finally, the paper
explores different circuit techniques to reduce the leakage power
consumption.
Keywords—Channel engineering, CMOS, dynamic Vdd , dy-
namic Vth , gate leakage, leakage current, low-leakage memory, Fig. 1 Log (I ) versus V at two different drain voltages for 20
multiple Vdd , multiple Vth , scaling, stacking effect, subthreshold 2 0.4-m n-channel transistor in a 0.35-m CMOS process [2].
current, tunneling.

in the substantial increase of the subthreshold leakage

I. INTRODUCTION current [1].
To achieve higher density and performance and lower Fig. 1 shows a typical curve of drain current
power consumption, CMOS devices have been scaled for versus gate voltage (VG) in logarithmic scale [2]. It allows
more than 30 years. Transistor delay times decrease by more measurement of many device parameters such as ,
than 30% per technology generation, resulting in doubling , and subthreshold slope , that is, the slope of
of microprocessor performance every two years. Supply versus in the weak inversion state. Transistor off-state
voltage has been scaled down in order to keep the current is the drain current when the gate voltage
power consumption under control. Hence, the transistor is zero. The n-channel transistor in Fig. 1 has an of
threshold voltage has to be commensurately scaled 20 and 4 pA m at the drain voltage of 2.5 and 0.1 V,
to maintain a high drive current and achieve performance respectively. is influenced by the threshold voltage,
improvement. However, the threshold voltage scaling results channel physical dimensions, channel/surface doping
profile, drain/source junction depth, gate oxide thickness,
and . in long-channel devices is dominated by
Manuscript received July 10, 2002; revised November 5, 2002. This work leakage from the drain-well and well-substrate reverse-bias
was supported in part by Semiconductor Research Corporation, in part by
Defense Advanced Research Projects Agency, Intel, and IBM. pn junctions [2]. Short-channel transistors require lower
The authors are with the School of Electrical and Computer power supply levels to reduce their internal electric fields
Engineering, Purdue University, West Lafayette, IN 47907-1285 and power consumption. This forces a reduction in the
USA (e-mail: [email protected]; [email protected]; mah-
[email protected]). threshold voltage that causes a substantially large increase
Digital Object Identifier 10.1109/JPROC.2002.808156 in [1]. This increase is due to the weak inversion state

0018-9219/03$17.00 © 2003 IEEE

PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003 305

 (a)

(b)
Fig. 2 ITRS projections for transistor scaling trends and power consumption: (a) physical
dimensions and supply voltage and (b) device power consumption [6].

leakage and is a function of . In this paper, we explore leakage mechanism, resulting due to the depletion at the
all leakage mechanisms contributing to the off-state current drain surface below the gate-drain overlap region. Fig. 2
(not just the current from the drain terminal). Other leakage shows projections for transistor physical dimensions, supply
mechanisms are peculiar to the small geometries them- voltage, and device power consumption according to the
selves. As the drain voltage increases, the drain to channel International Technology Roadmap for Semiconductors
depletion region widens, resulting in a significant increase (ITRS) [6]. All the parameters are normalized to their
in the drain current. This increase in is typically due values in the year 2001. As shown in Fig. 2(b), due to the
to channel surface current caused by drain-induced barrier substantial increase in the leakage current, the static power
lowering (DIBL) or due to deep channel punchthrough consumption is expected to exceed the switching component
currents [3]–[5]. Moreover, as the channel width decreases, of the power consumption unless effective measures are
the threshold voltage and the off current both get modulated taken to reduce the leakage power.
by the width of the transistor, giving rise to significant Due to adverse SCEs, the channel length cannot be arbi-
narrow-width effect. All these adverse effects which cause trarily reduced even if allowed by lithography. For digital
threshold voltage reduction (leakage current increase) in applications, the most undesirable SCE is the reduced gate
scaled devices are called short-channel effects (SCE). To threshold voltage at which the device turns on, especially at
maintain a reasonable SCE immunity while scaling down high drain voltages. Therefore, to take the best advantage of
the channel length, oxide thickness has to be reduced nearly the new high-resolution lithographic techniques, new device
in proportion to the channel length. Decrease in oxide designs, structures, and technologies should be developed to
thickness results in increase in the electric field across the keep SCEs under control at very small dimensions. In ad-
gate oxide. The high electric field and low oxide thickness dition to gate oxide thickness and junction scaling, another
result in considerable current flowing through the gate technique to improve short-channel characteristics is well en-
of a transistor. This current destroys the classical infinite gineering. By changing the doping profile in the channel re-
input impedance assumption of MOS transistors and thus gion, the distribution of the electric field and potential con-
affects the circuit performance severely. Major contributors tours can be changed. The goal is to optimize the channel
to the gate leakage current are gate oxide tunneling and profile to minimize the off-state leakage while maximizing
injection of hot carrier from substrate to the gate oxide. the linear and saturated drive currents. Supersteep retrograde
Gate-induced drain leakage (GIDL) is another significant wells and halo implants have been used as a means to scale

306 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

Fig. 3 Summary of leakage current mechanisms of Fig. 4 BTBT in reverse-biased pn junction [14].
deep-submicrometer transistors.

1) Band-to-Band Tunneling Current: High electric field

the channel length and increase the transistor drive current 10 V/cm across the reverse-biased pn junction causes
without causing an increase in the off-state leakage current significant current to flow through the junction due to tun-
[7]–[10]. neling of electrons from the valence band of the p region to
This paper is organized as follows. In Section II, different the conduction band of the n region, as shown in Fig. 4 [14].
leakage current components and mechanisms in deep-sub- From Fig. 4, it is evident that for the tunneling to occur, the
micrometer transistors are explained, which is essential to total voltage drop across the junction has to be more than the
guide solutions for reducing power and leakage per transistor. band gap. The BTBT current in silicon involves the emission
Device options for leakage reduction, which are based on or absorption of phonons, since silicon is an indirect band
channel engineering, are explained in the first part of Sec- gap semiconductor. The tunneling current density is given
tion III. The second part of Section III explores different cir- by [14]
cuit techniques for leakage control in logic and memory. Fi-
nally, the conclusion of the paper appears in Section IV.

II. TRANSISTOR LEAKAGE MECHANISMS

and (1)
We describe six short-channel leakage mechanisms as il-
lustrated in Fig. 3. is the reverse-bias pn junction leakage;
where is effective mass of electron; is the energy-band
is the subthreshold leakage; is the oxide tunneling cur-
gap; is the applied reverse bias; is the electric field at
rent; is the gate current due to hot-carrier injection; is
the junction; is the electronic charge; and is times
the GIDL; and is the channel punchthrough current. Cur-
Planck’s constant.Assuming a step junction, the electric field
rents , , and are off-state leakage mechanisms, while
at the junction is given by [14]
and occur in both ON and OFF states. can occur in the
off state, but more typically occurs during the transistor bias
states in transition. (2)

A. pn Junction Reverse-Bias Current where and are the doping in the p and n side, re-
Drain and source to well junctions are typically reverse spectively; is permittivity of silicon; and is the built
biased, causing pn junction leakage current. A reverse-bias in voltage across the junction. In scaled devices, high doping
pn junction leakage has two main components: one is concentrations and abrupt doping profiles cause significant
minority carrier diffusion/drift near the edge of the deple- BTBT current through the drain-well junction.
tion region; the other is due to electron-hole pair generation
in the depletion region of the reverse-biased junction [12]. B. Subthreshold Leakage
For an MOS transistor, additional leakage can occur between Subthreshold or weak inversion conduction current be-
the drain and well junction from gated diode device action tween source and drain in an MOS transistor occurs when
(overlap of the gate to the drain-well pn junctions) or carrier gate voltage is below [15]. The weak inversion region is
generation in drain to well depletion regions with influence seen in Fig. 1 as the linear region of the curve (semilog plot).
of the gate on these current components [13]. pn junction re- In the weak inversion, the minority carrier concentration is
verse-bias leakage is a function of junction area and small, but not zero. Fig. 5 shows the variation of minority
doping concentration [12]. If both n and p regions are heavily carrier concentration along the length of the channel for an
doped (this is the case for advanced MOSFETs using heavily n-channel MOSFET biased in the weak inversion region. Let
doped shallow junctions and halo doping for better SCE), us consider that the source of the n-channel MOSFET is
band-to-band tunneling (BTBT) dominates the pn junction grounded, , and the drain to source voltage
leakage [14]. This leakage mechanism is explained in Sec- V. For such weak inversion condition, drops almost
tion II-A1. entirely across the reverse-biased substrate-drain pn junction.

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 307
Fig. 5 Variation of minority carrier concentration in the channel
of a MOSFET biased in the weak inversion.

As a result, the variation of the electrostatic potential at Fig. 6 Subthreshold leakage in a negative-channel
the semiconductor surface along the channel (the axis) is metal–oxide–semiconductor (NMOS) transistor.
small. The component of the electric field vector ,
being equal to , is also small. With both the number of voltage are scaled down to enhance performance, power
mobile carriers and the longitudinal electric field small, the efficiency, and reliability, subthreshold characteristics may
drift component of the subthreshold drain-to-source current limit the scalability of the supply voltage. The parameter
is negligible. Therefore, unlike the strong inversion region is measured in millivolts per decade of the drain current.
in which the drift current dominates, the subthreshold con- For the limiting case of and at room temperature,
duction is dominated by the diffusion current. The carriers 60 mV/decade. Typical values for a bulk CMOS
move by diffusion along the surface similar to charge trans- process can range from 70 to 120 mV/decade. A low value
port across the base of bipolar transistors. The exponential for subthreshold slope is desirable. It can be noted from
relation between driving voltage on the gate and the drain the preceding expression that can be made smaller by
current is a straight line in a semilog plot of versus using a thinner oxide (insulator) layer to reduce or a
(see Fig. 6). Weak inversion typically dominates modern de- lower substrate doping concentration (resulting in larger
vice off-state leakage due to the low . The weak inversion ). Changes in operating conditions—namely, lower
current can be expressed based on the following [15]: temperature or a substrate bias—also modifies .
1) Drain-Induced Barrier Lowering: In long-channel
devices, the source and drain are separated far enough that
their depletion regions have no effect on the potential or
(3) field pattern in most part of the device. Hence, for such
devices, the threshold voltage is virtually independent of
where the channel length and drain bias. In a short-channel device,
however, the source and drain depletion width in the vertical
(4) direction and the source drain potential have a strong effect
on the band bending over a significant portion of the device.
where is the threshold voltage, and is the Therefore, the threshold voltage, and consequently the
thermal voltage. is the gate oxide capacitance; is the subthreshold current of short-channel devices, vary with the
zero bias mobility; and is the subthreshold swing coeffi- drain bias. This effect is referred to as DIBL. One way to
cient (also called body effect coefficient). is the max- describe it is to consider the energy barrier at the surface
imum depletion layer width, and is the gate oxide thick- between the source and drain, as shown in Fig. 7 [17]. Under
ness. is the capacitance of the depletion layer. off conditions, this potential barrier prevents electrons from
In long-channel devices, the subthreshold current is inde- flowing to the drain. For a long-channel device, the barrier
pendent of the drain voltage for larger than a few . On height is mainly controlled by the gate voltage and is not
the other hand, the dependence on the gate voltage is expo- sensitive to . However, the barrier of a short-channel
nential, as illustrated in Fig. 6 [16]. The inverse of the slope device reduces with an increase in the drain voltage, which
of the versus characteristic is called the sub- in turn increases the subthreshold current due to lower
threshold slope [15] and is given by threshold voltage.
DIBL occurs when the depletion regions of the drain and
the source interact with each other near the channel surface to
lower the source potential barrier. When a high drain voltage
is applied to a short-channel device, it lowers the barrier
(5) height, resulting in further decrease of the threshold voltage.
The source then injects carriers into the channel surface (in-
Subthreshold slope indicates how effectively the transistor dependent of gate voltage). DIBL is enhanced at high drain
can be turned off (rate of decrease of ) when is voltages and shorter channel lengths. The surface DIBL typ-
decreased below . As device dimensions and the supply ically occurs before the deep bulk punchthrough. Ideally,

308 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

 Fig. 9 n channel log(I ) versus V for six substrate biases on a
0.35-m logic process technology (V = 2.7 V) [11].

between the Fermi potential and the intrinsic potential in the

substrate. The slope of versus curve is therefore

Fig. 7 Lateral energy-band diagram at the surface versus distance

(normalized to the channel length L) from the source to the drain (7)
for: (a) long-channel MOSFET; (b) a short-channel MOSFET;
(c) a short-channel MOSFET at high drain bias. The gate voltage
is same for all three cases [17]. which is referred to as the substrate sensitivity. It can be seen
from (7) that the substrate sensitivity is higher for higher bulk
doping concentration, and the substrate sensitivity decreases
as the substrate reverse bias increases. At , the sub-
strate sensitivity is or (4). Therefore, is
also called body effect coefficient.
Fig. 9 shows suppression in n-channel drain current when
the well-to-source voltage is back biased from 0 to 5 V (the
back bias is the well voltage) [11]. Virtually no change is seen
in the subthreshold slope at different substrate biases. An
important observation from Fig. 9 is that as increases,
because of applied reverse substrate bias and a shift in the
– curve, decreases.
The subthreshold leakage of an MOS device including
weak inversion, DIBL, and body effect, can be modeled as
[21]
Fig. 8 n channel I vs. V showing DIBL, GIDL, weak
inversion, and pn junction reverse-bias leakage components [11].

(8)
DIBL does not change the subthreshold slope , but does
lower . Higher surface and channel doping and shallow
where
source/drain junction depths reduce the DIBL effect on the
subthrshold leakage current [17], [18]. Fig. 8 illustrates the
(9)
DIBL effect as it moves the curve up and to the
left as the drain voltage increases. DIBL can be measured at
constant as the change in for a change in [11]. is the zero bias threshold voltage, and is the
2) Body Effect: Reverse biasing well-to-source junction thermal voltage. The body effect for small values of source
of a MOSFET transistor widens the bulk depletion region and to bulk voltages is linear and is represented by the term
increases the threshold voltage [19]. The effect of body bias in (7), where is the linearized body effect coefficient. is
can be considered in the threshold voltage equation [20] the DIBL coefficient, is the gate oxide capacitance,
is the zero bias mobility, and is the subthreshold swing
coefficient of the transistor. is a term introduced to
account for transistor-to-transistor leakage variations.
(6) 3) Narrow-Width Effect: The decrease in gate width
modulates the threshold voltage of a transistor, and thereby
where is the flat-band voltage; is the doping density in modulates the subthreshold leakage. There are mainly three
the substrate; and is the difference ways that narrow width modulates the threshold voltage.

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 309
 (a) (b)

(c)
Fig. 10 Three types of device structures and associated inversion–depletion layer. (a)
Large-geometry MOSFET. (b) LOCOS gate MOSFET. (c) Trench isolated MOSFET [22].

First, let us consider the local oxide isolation (LOCOS) gate a higher voltage is needed to completely invert the channel
MOSFET. In the LOCOS gate MOSFET, the existence of [26].
the fringing field causes the gate-induced depletion region A more complex effect is seen in trench isolation devices,
to spread outside the defined channel width and under the known as inverse-narrow-width effect. In the case of trench
isolations as shown in Fig. 10(b). This results in an increase isolation devices, depletion layer cannot spread under the
of the total depletion charge in the bulk region above its oxide isolation [see Fig. 10(c)]. Hence, the total depletion
expected value. The threshold voltage of MOS can be charge in the bulk does not increase , thereby
defined using depletion approximation as [22] eliminating the increase in the threshold voltage. On the other
hand, due to the two-dimensional (2-D) field-induced edge-
fringing effect at the gate edge, formation of an inversion
(10) layer at the edges occurs at a lower voltage than the voltage
required at the center. Moreover, the overall gate capacitance
where is the flat-band voltage; is the surface potential; now includes the sidewall capacitance due to
is the capacitance across the oxide; and is the deple- overlap of the gate with the isolation oxide. This increases
tion charge in the bulk. Due to narrow-width effect, in- the overall gate capacitance [22]. Overall gate capacitance is
creases by as shown in Fig. 10(b). This effect becomes therefore given by , which is greater than
more substantial as the channel width decreases, and the de- given in (10). Hence, the overall reduces as shown
pletion region underneath the fringing field is comparable to in Fig. 11 [22]. A much more complex behavior can be ob-
the classical depletion formed by the vertical field. This re- served in the case of trench-isolated buried channel P-MOS-
sults in increase of threshold voltage due to narrow-channel FETs, where reduction of the width first decreases the
effect [23], [24]. This narrow-width effect can be modeled as until the width is 0.4 m. The width reduction below 0.4 m
an increase in by the amount given by [25] causes a sharp increase in Fig. 12 [27].
4) Effect of Channel Length and Rolloff: Threshold
voltage of MOSFET decreases as the channel length is re-
(11) duced. This reduction of threshold voltage with reduction
of channel length is known as rolloff. Fig. 13 shows
where is the substrate doping; is the maximum the reduction of threshold voltage with reduction in channel
vertical depletion width; is the capacitance across the length. The principal reason behind this effect is the pres-
oxide; is the effective width; is the oxide thickness; ence of 2-D field patterns in short-channel devices instead
and is the surface potential. A more accurate model can of one-dimensional (1-D) field patterns in long-channel de-
be found in [24]. vices. This 2-D field pattern originates from the proximity
The second way that narrow-width modulates the of source and drain regions [28]. There are depletion re-
threshold voltage is due to the fact that the channel doping gions surrounding the source and drain junctions. In long-
is higher along the width dimension in LOCOS gates. Due channel devices, since the source and drain are far apart, their
to the channel stop, dopants encroach under the gate. Hence, depletion regions do not have much effect on the potential

310 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

 Fig. 14 Schematic diagram for charge-sharing model explaining
the reduction of V due to the source/drain depletion regions. The
bulk charge that needs to be inverted is proportional to the area
under the trapezoidal region given by Q / W (L + L )=2,
which is less than the total depletion charge in the long-channel
Fig. 11 Variation of threshold voltage with gate width for uniform
doping [22].
case, which is Q / W (L) [28].

Fig. 15 I versus V showing temperature sensitivity of I

[18].

Fig. 12 Variation of threshold voltage with gate width in the

case of trench isolated buried channel P-MOSFET showing the pared with a long-channel one. Consequently, the threshold
anomalous behavior [27]. voltage is lower for a short-channel device. The effect of
the source drain depletion region is more severe at a high
drain bias. High drain bias results in more depletion charge
in the channel from the drain and source, resulting in fur-
ther decrease of the threshold voltage, and hence, larger sub-
threshold current.
5) Effect of Temperature: Temperature dependence of
the subthreshold leakage current is important, since digital
very large scale integration (VLSI) circuits usually operate
at elevated temperatures due to the power dissipation (heat
generation) of the circuit. versus shows a linear
change in subthreshold slope with temperature (see
Fig. 15) as predicted by the subthreshold current model
Fig. 13 Threshold voltage rolloff with change in channel length; [15]. In Fig. 15, varies from 58.2 to 81.9 mV/decade
V reduction is more severe at higher drain bias.
as the temperature increases from 50 C to 25 C in a
0.35- m technology. In this technology, the major com-
profile or field pattern in most parts of the channel. How- ponent of is the subthershold leakage; therefore, the
ever, in the case of short-channel devices, source-to-drain temperature dependence of represents the temperature
distance is comparable to the depletion width in the vertical dependence of the subthreshold leakage. The increase in
direction. As a result, source drain depletion width has a the is 0.45–160 pA for the 20- m-wide device (23
more pronounced effect on potential profiles and field pat- fA m to 8 pA m). increases by a factor of 356 for
terns. The source and drain depletion regions now penetrate this technology. Two parameters increase the subthreshold
more into the channel length, resulting in part of the channel leakage as temperature is raised: 1) linearly increases
being already depleted. Thus, gate voltage has to invert less with temperature; and 2) the threshold voltage decreases.
bulk charge to turn a transistor on (see Fig. 14). In other The temperature sensitivity of was measured to be about
words, for the same gate voltage, there is more band bending 0.8 mV C. The temperature sensitivity of can be used
in the Si–SiO interface in a short-channel device as com- to estimate at other temperatures.

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 311
 (a) (b)

(c)
Fig. 16 Tunneling of electrons through an MOS capacitor. (a) Energy-band diagram at flat-band
condition. (b) Energy-band diagram with positive gate bias showing tunneling of electron from
substrate to gate. (c) Energy-band diagram at negative gate bias showing tunneling of electron from
gate to substrate [29].

C. Tunneling into and Through Gate Oxide

Reduction of gate oxide thickness results in an increase in
the field across the oxide. The high electric field coupled with
low oxide thickness results in tunneling of electrons from
substrate to gate and also from gate to substrate through the
gate oxide, resulting in the gate oxide tunneling current.
To understand the phenomenon of tunneling, let us
consider an MOS capacitor with a heavily doped n+-type
polysilicon gate and a p-type substrate. Also, for sim- Fig. 17 FN tunneling of electrons.
plicity, let us now focus only on the electron tunneling. An
energy-band diagram in flat-band condition is shown in
Fig. 16(a), where is the Si-SiO interface barrier height Fig. 17 shows the FN tunneling of electrons from the inverted
for electrons. When a positive bias is applied to the gate, the surface to the gate. Ignoring the effect of finite temperature
energy-band diagram changes as shown in Fig. 16(b). Due and image-force-induced barrier lowering, the current den-
to the small oxide thickness, which results in a small width sity in the FN tunneling is given by [29]
of the potential barrier, the electrons at the strongly inverted
surface can tunnel into or through the SiO layer and hence (12)
give rise to the gate current. On the other hand, if a negative
gate bias is applied, electrons from the n+ polysilicon can
tunnel into or through the oxide layer and give rise to the where is the field across the oxide; is the barrier
gate current [see Fig. 16(c)] [29]. height for electrons in the conduction band; and is the ef-
The mechanism of tunneling between substrate and gate fective mass of an electron in the conduction band of silicon.
polysilicon can be primarily divided into two parts, namely: The FN current equation represents the tunneling through the
(1) Fowler–Nordheim (FN) tunneling; and (2) direct tun- triangular potential barrier and is valid for , where
neling. In the case of FN tunneling, electrons tunnel through a is the voltage drop across the oxide [30]. The measured
triangular potential barrier, whereas in the case of direct tun- value of FN tunneling current is very small; for example, at
neling, electrons tunnel through a trapezoidal potential bar- an oxide field of 8 MV/cm, the FN tunneling current den-
rier. The tunneling probability of an electron depends on the sity is about 5 10 A/cm [29]. Since eV,
thickness of the barrier, the barrier height, and the structure of short-channel devices mostly operate at . Thus, for
the barrier. Therefore, the tunneling probabilities of a single normal device operation, the FN tunneling current is negli-
electron in FN tunneling and direct tunneling are different, gible.
resulting in different tunneling currents. 2) Direct Tunneling: In very thin oxide layers (less than
1) Fowler–Nordheim Tunneling: In FN tunneling, elec- 3–4 nm), electrons from the inverted silicon surface, instead
trons tunnel into the conduction band of the oxide layer. of tunneling into the conduction band of SiO , directly tunnel

312 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

 current , part of which goes to the source and the
rest goes to the drain ; and the gate to the substrate
leakage current (see Fig. 21) [31], [32]. The modeling
of each of the components can be found in [31], [32].
c) Effect of quantization of substrate electron en-
ergy: Due to high substrate doping level and large electric
field at the Si–SiO surface, the quantization of carrier
energy occurs within the Si substrate (see Fig. 22). This
Fig. 18 Direct tunneling of electrons.
results in less occupied energy states from which electrons
can tunnel. Also due to the quantization effect, the carrier
to the gate through the forbidden energy gap of the SiO density in the substrate is different from the classical pre-
layer [29]. The direct tunneling phenomenon is explained diction. With the quantization, the carrier density peaks at a
in Fig. 18. In the case of direct tunneling, electrons tunnel little distance away from the surface and not at the surface as
through a trapezoidal potential barrier instead of a triangular predicted by classical physics. This can be considered as an
potential barrier. Hence, the direct tunneling occurs at effective increase in the oxide thickness. Thus, quantization
[30]. The equation governing the current density of the effect modulates the gate direct tunneling current [34].
direct tunneling is given by [30] d) Effect of image-force-induced barrier low-
ering: The emission of electron from Si to SiO causes
build up of image charge at the oxide side of the Si–SiO
(13) interface, which results in a reduction in the barrier height
at the Si–SiO interface from eV by an amount
given by
where and . Di-
rect tunneling current is significant for low oxide thicknesses. (15)
Fig. 19 shows the variation of the direct tunneling current
density with based on (13). where is the permittivity of SiO . This is called the
Potential drop across the oxide is obtained from the fact image-force-induced barrier-lowering effect [29]. Since
that applied gate voltage over the flat-band voltage drops it modulates the barrier height, it also modulates the gate
across the polysilicon depletion layer, gate oxide, and the rest tunneling current, as the tunneling exponentially depends
appear as surface potential. on .
(14) D. Injection of Hot Carriers from Substrate to Gate Oxide
where is the applied gate bias; is the surface potential;
and is the potential drop across the polysilicon deple- In a short-channel transistor, due to high electric field near
tion region given by , where is the the Si–SiO interface, electrons or holes can gain sufficient
doping concentration of polysilicon, is the permittivity of energy from the electric field to cross the interface potential
silicon, and is the permittivity of SiO . barrier and enter into the oxide layer (see Fig. 23). This ef-
a) Mechanisms of direct tunneling: There are three fect is known as hot-carrier injection. The injection from Si
major mechanisms for direct tunneling in MOS devices, to SiO is more likely for electrons than holes, as electrons
namely, electron tunneling from conduction band (ECB), have a lower effective mass than that of holes, and the barrier
electron tunneling from valence band (EVB), and hole tun- height for holes (4.5 eV) is more than that for electrons (3.1
neling from valance band (HVB) [31], [32] (see Fig. 20). In eV) [35].
NMOS, ECB controls the gate to channel tunneling current
in inversion, whereas gate-to-body tunneling is controlled E. Gate-Induced Drain Leakage
by EVB in depletion-inversion and ECB in accumulation. In GIDL is due to high field effect in the drain junction of an
positive-channel MOSs (PMOSs), HVB controls the gate to MOS transistor. When the gate is biased to form an accumu-
channel leakage in inversion, whereas gate-to-body leakage lation layer at the silicon surface, the silicon surface under the
is controlled by EVB in depletion-inversion and ECB in gate has almost same potential as the p-type substrate. Due to
accumulation [31], [32]. Since the barrier height for HVB presence of accumulated holes at the surface, the surface be-
(4.5 eV) is considerably higher than barrier height for ECB haves like a p region more heavily doped than the substrate.
(3.1 eV), the tunneling current associated with HVB is much This causes the depletion layer at the surface to be much nar-
less than the current associated with ECB. This results in rower than elsewhere [see Fig. 24(a)]. The narrowing of the
lower gate leakage current in PMOS than in NMOS [33]. depletion layer at or near the surface causes field crowding
b) Components of tunneling current: The gate direct or an increase in the local electric field, thereby enhancing
tunneling current can be divided into five major components, the high field effects near that region [36]. When the nega-
namely, parasitic leakage current through gate-to-S/D exten- tive gate bias is large (i.e., gate at zero or negative and drain
sion overlap region ( and ); gate to inverted channel at ), the n+ drain region under the gate can be depleted

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 313
Fig. 19 Simulated direct tunneling current density in thin-oxide polysilicon gate MOS devices.

Fig. 22 Quantization of electron energy levels in substrate.

Fig. 20 Three mechanisms for gate leakage [31], [32].

Fig. 23 Injection of hot electrons from substrate to oxide.

minority carriers, the minority carriers that have been accu-

Fig. 21 Components of tunneling current [31], [32].
mulated or formed at the drain depletion region underneath
the gate are swept laterally to the substrate, completing a path
and even inverted as shown in Fig. 24(b). This causes more for the GIDL [37]. Thinner oxide thickness and higher
field crowding and peak field increase, resulting in a dra- (higher potential between gate and drain) enhance the elec-
matic increase of high field effects such as avalanche mul- tric field and therefore increase GIDL. The impact of drain
tiplication and BTBT [36]. The possibility of tunneling via and well doping on GIDL is rather complicated. At low drain
near-surface traps also increases. As a result of all these ef- doping, the electric field is not high enough to cause tun-
fects, minority carriers are emitted in the drain region under- neling. At very high drain doping, the depletion width—and,
neath the gate. Since the substrate is at a lower potential for therefore, the tunneling volume—are limited, causing less

314 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

 increase in the drain voltage beyond the value required to es-
tablish the punchthrough lowers the potential barrier for the
majority carriers in the source. Thus, more of these carriers
cross the energy barrier and enter into the substrate, and the
drain collects some of them. The net effect is an increase
in the subthreshold current. Furthermore, punchthrough
degrades the subthreshold slope. The device parameter
commonly used to characterize the punchthrough is the
punchthrough voltage , which estimates the value of
for which the punchthrough occurs (i.e., the subthreshold
current reaches a particular value) at . It is roughly
estimated as the value of the for which the sum of the
widths of the drain and source depletion regions is equal to
effective channel length [38]
(a)
(16)

where is the doping concentration at the bulk; is the

channel length; and is the junction width.
The most suitable method for controlling the
punchthrough is to use additional implants. A layer of
higher doping at a depth equal to that of the bottom of the
junction depletion regions is one possible solution. Another
approach could be to form a halo implant at the leading
edges of the drain and source junctions [38].

III. LEAKAGE REDUCTION TECHNIQUES

For a CMOS circuit, the total power dissipation includes
dynamic and static components during the active mode of
(b) operation. In the standby mode, the power dissipation is due
Fig. 24 Condition of the depletion region near the drain-gate to the standby leakage current. Dynamic power dissipation
overlap region of an MOS transistor when (a) surface is consists of two components. One is the switching power due
accumulated with low negative gate bias; and (b) n+ region is to charging and discharging of load capacitance. The other
depleted or inverted with high negative gate bias.
is short circuit power due to the nonzero rise and fall time
of input waveforms. The static power of a CMOS circuit is
GIDL. Hence, GIDL is worse for moderate drain doping (in determined by the leakage current through each transistor.
between the extremes previously mentioned), where both the The dynamic (switching) power and leakage power
electric field and depletion width (tunneling volume) are con- are expressed as
siderable. Very high and abrupt drain doping is preferred for
minimizing GIDL, as it provides lower series resistance re- (17)
quired for high transistor drive currents [21]. (18)
F. Punchthrough where is the switching activity; is the operation fre-
In short-channel devices, due to the proximity of the drain quency; is the load capacitance; is the supply voltage;
and the source, the depletion regions at the drain-substrate and is the cumulative leakage current due to all the
and source-substrate junctions extend into the channel. As components of the leakage current described in Section II.
the channel length is reduced, if the doping is kept constant, Due to all the leakage mechanisms described in Section II,
the separation between the depletion region boundaries de- leakage current (power) increases dramatically in the scaled
creases. An increase in the reverse bias across the junctions devices. Particularly, with reduction of threshold voltage (to
(with increase in ) also pushes the junctions nearer to achieve high performance), leakage power becomes a sig-
each other. When the combination of channel length and nificant component of the total power consumption in both
reverse bias leads to the merging of the depletion regions, active and standby modes of operation (see Fig. 25 [39]).
punchthrough is said to have occurred. In submicrometer Hence, to suppress the power consumption in low-voltage
MOSFETs, a adjust implant is used to have a higher circuits, it is necessary to reduce the leakage power in both
doping at the surface than that in the bulk. This causes a the active and standby modes of operation. The reduction in
greater expansion of the depletion region below the surface leakage current has to be achieved using both process- and
(due to smaller doping there) as compared to the surface. circuit-level techniques. At the process level, leakage reduc-
Thus, the punchthrough occurs below the surface [38]. An tion can be achieved by controlling the dimensions (length,

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 315
Fig. 25 Power and delay dependence on threshold voltage (V )
[39].

oxide thickness, junction depth, etc.) and doping profile in

transistors. At the circuit level, threshold voltage and leakage
current of transistors can be effectively controlled by control-
Fig. 26 MOSFET constant-electric-field scaling [40].
ling the voltages of different device terminals [drain, source,
gate, and body (substrate)]. In this section, we first consider
major process techniques and then consider several circuit
techniques for leakage control and reduction. Though most
of the process and circuit techniques described here are used
to control the subthreshold leakage, some of them can be
used to control other leakage components, too. Reducing all
the components of leakage by both process- and circuit-level
techniques is of major interest.
Fig. 27 Graphical representation of different aspects of well
engineering [42].
A. Channel Engineering for Leakage Reduction
Based on constant field scaling [4], the SCE can be kept For a MOSFET, AR can be expressed as
under control by scaling down the vertical dimensions, for
example, gate insulator thickness, junction depth, along AR (21)
with the horizontal dimensions, while also proportionally
decreasing the applied voltages. The substrate doping con-
centration should increase to decrease the depletion width where and are silicon and oxide permittivities; and ,
proportionally. This is shown schematically in Fig. 26 [40]. , , and are channel length, gate oxide thickness,
The principle of constant field scaling lies in scaling the depletion depth, and junction depth, respectively. From (21),
device voltages and the device dimensions (both horizontal we can see that reducing , , and will reduce the
and vertical) by the same factor, , such that the elec- SCE of a MOSFET.
tric field remains unchanged. Constant electric field assures In addition to gate oxide thickness and junction scaling,
the reliability of the scaled device in terms of hot-carrier another technique to improve short-channel characteristics
injection. is well engineering. By changing the doping profile in the
A key parameter is the maximum gate depletion width, channel region, the distribution of the electric field and po-
, within which mobile carriers (holes in the case of tential contours can be changed. The goal is to optimize the
nMOSFETs) are swept away by the applied gate field. For channel profile to minimize the OFF-state leakage while max-
uniformly doped case imizing the linear and saturated drive currents. Supersteep
retrograde wells and halo implants have been used as a means
to scale the channel length and increase the transistor drive
current without causing an increase in the OFF-state leakage
(19) current [7]–[10]. Fig. 27 is a schematic representation of the
transistor regions that are affected by the different types of
well engineering [42]. Retrograde well engineering changes
where is the intrinsic carrier concentration. To minimize
the 1-D characteristics of the well profile by creating a ret-
SCEs, a sufficiently large aspect ratio (AR) of the device is
rograde profile toward the Si–SiO surface. The halo profile
required [41]. AR is defined as
creates a localized 2-D dopant distribution near the S/D ex-
tension regions. The use of these two techniques to increase
AR dimension the device performance, while keeping leakage to a tolerable
(20) limit, is discussed in Sections III-A1 and III-A2.
dimension

316 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

 Fig. 29 t W – design space. Some tradeoff among the various
factors can be made within the parameter space bounded by SCE,
body-effect, and oxide-field considerations [43].
Fig. 28 Band digrams (shown on top) at the threshold condition
for a uniformly doped and an extreme retrograde-doped channel
(doping profiles shown at bottom) [40].

1) Retrograde Doping: To maintain acceptable OFF-state

leakage with continually decreasing channel lengths, both
the oxide thickness and the gate-controlled depletion width
in silicon

(22)

must be reduced in proportion to the channel length to

offset the degradation in SCEs for extremely small devices.
This requires an increase in the channel-doping concentra- Fig. 30 Halo or nonuniform channel doping.
tion . This leads to a higher threshold voltage for a uni-
formly doped channel, according to the following: SCE, but increases substrate sensitivity and subthreshold
slope. Since both subthreshold slope, 2.3 mKT/q, and the
(23) substrate sensitivity, , degrade with
higher , should be kept close to 1. A larger also results
However, if the threshold voltage is not scaled, the device in a lower saturation current in the long-channel limit. Typi-
performance for low supply voltages will degrade due to the cally, it is required to have , or .
large reduction in gate drive. To reduce the gate-controlled These design considerations are illustrated in Fig. 29 [43].
depletion width while fulfilling the reduction trend, ret- The lower limit of is imposed by technology constraints
rograde doping can be used. to , where is the maximum oxide field.
Retrograde channel doping is a vertically nonuniform, For a given and , the allowable parameter space in
low-high channel doping. It is used to improve the SCEs a design plane is a triangular area bounded by
and to increase surface channel mobility by creating a low SCE, oxide field, and subthreshold slope (also substrate
surface channel concentration followed by a highly doped sensitivity) requirements.
subsurface region. The low surface concentration increases 2) Halo Doping: Halo doping or nonuniform channel
surface channel mobility by minimizing channel impurity profile in a lateral direction was introduced below 0.25- m
scattering while the highly doped subsurface region acts as technology node to provide another way to control the
a barrier against punchthrough. dependence of threshold voltage on channel length. For
Fig. 28 shows a schematic band-bending diagram at the n-channel MOSFETs, more highly p-type doped regions are
threshold condition of an extreme retrograde profile with an introduced near the two ends of the channel as shown in
undoped surface layer of thickness . For the same gate de- Fig. 30. Under the edges of the gate, in the vicinity of what
pletion width , the surface electric field and the total will eventually become the end of the channel, point defects
depletion charge of an extreme retrograde channel is one-half are injected during sidewall oxidation. These point defects
that of a uniformly doped channel. This reduces the threshold gather doping impurities from the substrate, thereby in-
voltage and improves mobility. creasing the doping concentration near the source and drain
Retrograde channel doping allows the threshold voltage end of the channel [44]. More highly doped p-type substrate
to be decoupled from the gate-controlled deple- near the edges of the channel reduces the charge-sharing
tion width . However, the body effect coefficient effects from the source and drain fields, thus reducing the
and the subthresheold slope, width of the depletion region in the drain-substrate and
, are still coupled to the gate depletion source-substrate regions. As the channel length is reduced,
width . For a given , reduction in improves these highly doped regions consume a larger fraction of

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 317
 Fig. 32 Stacking effect in two-input NAND gate.
Fig. 31 Short-channel threshold-voltage rolloff for retrograde and
superhalo (vertical and lateral nonuniform dopings).
voltage (less DIBL) of , and thus reducing the sub-
threshold leakage.
the total channel. Reduction of charge-sharing effects The leakage of a two-transistor stack is an order of mag-
reduces the threshold voltage degradation due to channel nitude less than the leakage in a single transistor [46]. An
length reduction. Thus, threshold voltage dependence on analysis of the subthreshold leakage through a stack of n tran-
channel length becomes more flat as shown in Fig. 31. sistor is shown in [47].
Hence, the off-current becomes less sensitive to channel Due to the stacking effect, the subthreshold leakage
length variation. The reduction in drain and source junction through a logic gate depends on the applied input vector.
depletion region width also reduces the barrier lowering in This makes the total leakage current of a circuit dependent
the channel, thus reducing DIBL. Since the channel edges on the states of the primary inputs [48], [49]. The most
are more heavily doped and junction depletion widths are straightforward way to find a low leakage input vector is to
smaller, the distance between source and drain depletion enumerate all combinations of primary inputs. For a circuit
regions is larger. This reduces the punchthrough possi- with primary inputs, there are combinations for input
bility. The higher doping near the channel edges causes states. Due to the exponential complexity with respect to
larger BTBT and higher GIDL. The BTBT currents in the the number of primary inputs, such an exhaustive method is
high-field region near the drain ultimately limit the halo limited to circuits with a small number of primary inputs. For
doping level [40]. large circuits, a random search-based technique can be used
to find the best input combinations. This method involves
generating a large number of primary inputs, evaluating the
B. Circuit Techniques for Leakage Reduction
leakage of each input, and keeping track of the best vector
In this section, four major circuit design tech- giving the minimal leakage current [48]. A more efficient
niques—namely, transistor stacking, multiple , dynamic way is to employ the genetic algorithm to exploit historical
, and supply voltage scaling (multiple and dynamic information to speculate on new search points with expected
) for leakage reduction in digital circuits (logic and improved performance to find a near-optimal solution [47].
memory)—are described. The reduction of standby leakage power by application of
1) Standby Leakage Control Using Transistor Stacks an input vector is a very effective way of controlling the
(Self-Reverse Bias): Subthershold leakage current flowing subthreshold leakage in the standby mode of operation
through a stack of series-connected transistors reduces when of a circuit. In [50], a stack transistor insertion technique
more than one transistor in the stack is turned off. This effect is given. For the gates with high subthreshold leakage in
is known as the stacking effect. The stacking effect is best noncritical paths, a leakage control transistor (low ) is
understood by considering a two-input NAND gate as shown inserted in series and is turned off during the standby mode.
in Fig. 32. When both and are turned off, the voltage The technique can effectively reduce the leakage current
at the intermediate node is positive due to small drain using single-threshold voltage.
current [45]. Positive potential at the intermediate node has 2) Multiple Designs: Multiple-threshold CMOS
three effects. technologies, which provide both high- and low-threshold
1) Due to the positive source potential , transistors in a single chip, can be used to deal with the
gate-to-source voltage of becomes leakage problem. The high-threshold transistors can suppress
negative; hence, the subthreshold current reduces the subthreshold leakage current, while the low-threshold
substantially. transistors are used to achieve high performance.
2) Due to , body-to-source potential of Multiple-threshold voltages can be achieved by the fol-
becomes negative, resulting in an increase in the lowing methods.
threshold voltage (larger body effect) of , and thus 1) Multiple channel doping. Multiple-threshold voltages
reducing the subthreshold leakage. can be achieved by adjusting the channel-doping den-
3) Due to , the drain to source potential of sities. Fig. 33 shows the threshold voltage at different
decreases, resulting in an increase in the threshold channel-doping densities [51]. For this approach,

318 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

Fig. 33 V at different channel-doping densities [51].
Fig. 35 Channel length at different oxide thicknesses for same
AR [51].

Fig. 34 V at different oxide thicknesses [51].

two additional masks are required. This technique Fig. 36 V rolloff for NMOS [51].
is commonly used to modify the threshold voltages.
However, the threshold voltage can vary due to the thicknesses [51]. An advance process technology is
nonuniform distribution of the doping density, making required for fabricating CMOS. An algorithm
it difficult to achieve dual threshold voltages when the for CMOS design is given in [51].
threshold voltages are very close to each other. 3) Multiple channel length. For short-channel transistors,
2) Multiple oxide CMOS . Gate oxide the threshold voltage decreases with the decrease in
thickness can be used to modify the threshold voltage channel length ( rolloff). Fig. 36 illustrates how
of a transistor. Variation of threshold voltage scaling of the feature size decreases the threshold
with oxide thickness for a 0.25- m device voltage based on MINIMOS simulations of 0.25- m
is shown in Fig. 34. Dual can be achieved CMOS technology. Hence, different threshold volt-
by depositing two different oxide thicknesses. For ages can be achieved by using different channel
transistors in noncritical paths, having a higher oxide lengths. Multiple channel length design uses the
thickness results in a high threshold voltage, and hence conventional CMOS technology. However, for the
low subthreshold leakage. On the other hand, lower transistors with feature sizes close to 0.1 m, halo
oxide thickness, and hence lower threshold voltage, in techniques [52] have to be used to suppress the SCE.
critical paths maintains the performance. Higher oxide This causes the rolloff to be very sharp; hence, it
thickness not only reduces the subthreshold leakage, is nontrivial to control the threshold voltage near the
it also reduces: a) gate oxide tunneling, since the minimum feature size for such technologies. Longer
oxide tunneling current exponentially decreases with channel lengths for high threshold transistors increase
an increase in the oxide thickness [30]; b) dynamic the gate capacitance, which has negative effect on
power consumption, since higher oxide thickness performance and power.
reduces the gate capacitance, which is beneficial for 4) Multiple body bias. For bulk silicon devices, the
reduction of the dynamic power [51]. body voltage can be changed to modify the threshold
For deep-submicrometer devices, increasing the voltage. If separate body biases are applied to dif-
gate oxide thickness has an adverse effect of in- ferent NMOS transistors, the transistors cannot share
creasing SCE. To reduce the SCE, the AR of the the same well; therefore, triple well technologies are
device must be kept large enough. AR of a device required. However, it is easier to change the body
as represented in (21) indicates the short-channel bias of partially depleted silicon-on-insulator (SOI)
immunity of the transistor—the larger the ratio is, devices, since the SOI devices are isolated naturally.
the less the SCEs are [41]. Hence, increased oxide For example, consider the double-gate fully depleted
thickness of a transistor should be associated with (FD) SOI, whose front-gate and back-gate surface
channel length increase in order to prevent severe potentials are strongly coupled to each other. The
SCEs. Fig. 35 shows the relevant channel length for threshold voltage can be adjusted by biasing the
maintaining the AR constant at different gate oxide back-gate voltage.

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 319
Fig. 37 Schematic of MTCMOS circuit [53].

Based on the multiple-threshold technologies previ-

ously described, several multiple-threshold circuit design
techniques have been developed recently, as explained in
Sections III-B2a–e.
a) Multithreshold-voltage CMOS: Multithreshold-
voltage CMOS (MTCMOS) reduces the leakage by inserting
high-threshold devices in series to low circuitry [53].
Fig. 37(a) shows the schematic of an MTCMOS circuit.
A sleep control scheme is introduced for efficient power
management. In the active mode, SL is set low and sleep
control high transistors (MP and MN) are turned on.
Since their on-resistances are small, the virtual supply
voltages (VDDV and VSSV) almost function as real power Fig. 38 Dual V CMOS circuit.
lines. In the standby mode, SL is set high, MN and MP are
turned off, and the leakage current is low. b) Dual threshold CMOS: For a logic circuit, a higher
In fact, only one type of high transistor is enough for threshold voltage can be assigned to some transistors in non-
leakage control. Fig. 37(b) and (c) shows the PMOS insertion critical paths so as to reduce the leakage current, while the
and NMOS insertion schemes, respectively. The NMOS in- performance is maintained due to the use of low threshold
sertion scheme is preferable, since the NMOS on-resistance transistors in the critical path(s) [58], [59]. Therefore, no
is smaller at the same width; therefore, it can be sized smaller additional leakage control transistors are required, and both
than corresponding PMOS [54]. MTCMOS can be easily im- high performance and low power can be achieved simulta-
plemented based on existing circuits. A 1-V digital signal neously. Fig. 38 illustrates the basic idea of a dual cir-
processor chip for mobile phone applications has been de- cuit. Fig. 39 shows the path distribution of dual and
veloped recently [55]. However, MTCMOS can only reduce single CMOS for a 32-bit adder. Dual CMOS has the
the standby leakage power, and the large inserted MOSFETs same critical delay as the single low CMOS circuit, but
can increase the area and delay. Moreover, if data retention the transistors in noncritical paths can be assigned high
is required in the standby mode, an extra high memory to reduce leakage power. Dual threshold technique is good
circuit is needed to maintain the data [56]. Instead of using for leakage power reduction during both standby and active
high sleep control transistors as MTCMOS, super cutoff modes without delay and area overhead.
CMOS (SCCMOS) technique uses low transistors with c) Variable threshold CMOS: Variable threshold
an inserted gate bias generator [57]. For the PMOS (NMOS) CMOS (VTMOS) is a body-biasing design technique [60].
insertion, the gate is applied to 0V (VDD) in the active mode, Fig. 40 shows the VTMOS scheme. To achieve different
and the virtual VDD (VSS) line is connected to supply VDD threshold voltages, a self-substrate bias circuit is used to
(VSS). In the standby mode, the gate is applied to VDD control the body bias. In the active mode, a nearly zero body
(VSS to fully cut off the leakage current. Compared bias is applied. While in the standby mode, a deeper reverse
with MTCMOS, SCCMOS circuits can work at lower supply body bias is applied to increase the threshold voltage and cut
voltages. off the leakage current. This scheme has been used in a 2-D

320 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

Fig. 39 Path distribution of dual V and single V CMOS.

Fig. 40 VTCMOS. Fig. 41 Schematic of DTMOS inverter.

discrete cosine transform core processor [60]. Furthermore, of DTMOS can be seen in partially depleted SOI devices.
in the active mode, a slightly forward substrate bias can be Fig. 42 shows the SOI DTMOS structure and layout. In
used to increase the circuit speed while reducing SCEs [61]. [64], excellent dc inverter characteristics down to 0.2 V and
Providing the body potential requires routing the body grid good ring oscillator performance down to 0.3 V are achieved
that adds to the overall chip area. Keshavarzi et al. reported using this method. The supply voltage of DTMOS is limited
that reverse body biasing lowers integrated circuit leakage by the diode built-in potential in bulk silicon technology.
by three orders of magnitude in a 0.35- m technology [62]. The pn diode between source and body should be reverse
However, more recent data showed that the effectiveness of biased. Hence, this technique is only suitable for ultralow
reverse body bias to lower decreases as technology voltage (0.6V and below) circuits in bulk CMOS.
scales [62]. e) Double-gate dynamic threshold SOI CMOS
d) Dynamic threshold CMOS: For dynamic threshold (DGDT-MOS): The double-gate dynamic threshold voltage
CMOS (DTMOS), the threshold voltage is altered dy- (DGDT) SOI MOSFET [65] combines the advantages of
namically to suit the operating state of the circuit. A high DTMOS and double-gate FD SOI MOSFETs without any
threshold voltage in the standby mode gives low leakage limitation on the supply voltage. Fig. 43 shows the structure
current, while a low threshold voltage allows for higher of a DGDT SOI MOSFET. A DGDT SOI MOSFET is an
current drives in the active mode of operation. Dynamic asymmetrical double-gate SOI MOSFET. Back-gate oxide
threshold CMOS can be achieved by tying the gate and body is thick enough to make the threshold voltage of the back
together [63]. Fig. 41 shows the schematic of a DTMOS gate larger than the supply voltage. Since the front-gate and
inverter. DTMOS can be developed in bulk technologies back-gate surface potentials are strongly coupled to each
by using triple wells. “Doping engineering” is needed to other, the front-gate threshold voltage changes dynami-
reduce the parasitic components [64]. Stronger advantages cally with the back-gate voltage. Results show that DGDT

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 321
Fig. 42 SOI DTMOS structure and layout.

Fig. 44 Schematic diagram of V -hopping [39].

Fig. 43 DGDT SOI MOSFET structure.

SOI MOSFETs have nearly ideal symmetric subthreshold

characteristics. Compared with symmetric double-gate SOI
CMOS, the power delay product of DGDT SOI CMOS is
smaller [66].
Fig. 45 Schematic of DVTS hardware [68].
3) Dynamic Designs: Dynamic threshold voltage
scaling is a technique for active leakage power reduction.
This scheme utilizes dynamic adjustment of frequency Enable, the frequency controller generates
through back-gate bias control depending on the workload (say).
of a system. When the workload decreases, less power is b) Dynamic -scaling scheme: A block diagram
consumed by increasing . Two varieties of dynamic of the DVTS scheme and its feedback loop is presented in
scaling (DVTS) have been proposed, as described later. Fig. 45 [68]. A clock speed scheduler, which is embedded in
a) -hopping scheme: Fig. 44 shows the schematic the operating system, determines the (reference) clock fre-
diagram of the -hopping scheme [39]. Using the control quency at run-time. The DVTS controller adjusts the PMOS
signal (CONT), which is obtained from software, the power and NMOS body bias so that the oscillator frequency of the
control block generates select signals, Enable and voltage-controlled oscillator tracks the given reference clock
Enable, which in turn control the substrate bias for frequency. The error signal, which is the difference between
the circuit. When the controller asserts Enable, the reference clock frequency and the oscillator frequency,
in the target processor reduces to . On the other hand, is fed into the feedback controller. The continuous feedback
when the controller asserts Enable, the target pro- loop also compensates for variation in temperature and
cessor becomes . CONT is controlled by soft- supply voltage.
ware through a software feedback loop scheme [67]. CONT 4) Supply Voltage Scaling: Supply voltage scaling was
also controls the operation frequency of the target processor. originally developed for switching power reduction. It is
When the controller asserts Enable, the frequency an effective method for switching power reduction because
controller generates , and when the controller asserts of the quadratic dependence of the switching power on the

322 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

Fig. 46 Two-level multiple supply voltage scheme [75].

supply voltage. Supply voltage scaling also helps reduce

leakage power, since the subthreshold leakage due to DIBL
decreases as the supply voltage is scaled down [69]. For
Fig. 47 DVS architecture [67].
a 1.2-V 0.13- m technology, it is shown that the supply
voltage scaling has significant impacts on subthreshold
leakage and gate leakage (reductions in the orders of and 30% of Alpha 21 264 and 60% of Strong ARM processors
, respectively) [70]. are devoted to cache and memory structures [77]. Caches
To achieve low-power benefits without compromising per- account for a large (if not dominant) component of leakage
formance, two ways of lowering supply voltage can be em- energy dissipation in recent designs, and will continue to do
ployed: static supply scaling and dynamic supply scaling. In so in the future. Recent energy estimates for 0.13- process
static supply scaling, multiple supply voltages are used as technology indicate that leakage energy accounts for 30% of
shown in Fig. 46. Critical and noncritical paths or units of L1 cache energy and as much as 80% of L2 cache energy. To
the design are clustered and powered by higher and lower address the problem, several techniques have been proposed
supply voltages, respectively [71]. Since the speed require- in the literature, as explained in Sections III-B5a–c.
ments of the noncritical units are lower than the critical ones, a) Data retention gated-ground cache: A data reten-
supply voltage of noncritical units can be lowered without tion gated-ground cache (DRG-Cache) puts the unused por-
degrading system performance. Whenever an output from a tions of the memory core to low leakage mode to reduce
low unit has to drive an input of a high unit, a level power. The key idea is to introduce an extra NMOS transistor
conversion is needed at the interface [72]. The secondary (see Fig. 48) in the leakage path from the supply voltage
voltages may be generated off-chip [73] or regulated on-die to the ground of the static random access memory (SRAM)
from the core supply [74]. Dynamic supply scaling overrides cells; the extra transistor is turned on in the used sections
the cost of using two supply voltages by adapting the single and off in the unused sections, essentially “gating” the supply
supply voltage to performance demand. The highest supply voltage of the cells. Fig. 48 shows the anatomy of the DRG-
voltage delivers the highest performance at the fastest de- Cache. Gated ground achieves significantly lower leakage
signed frequency of operation. When performance demand because of the two off transistors connected in series, re-
is low, supply voltage and clock frequency is lowered, deliv- ducing the leakage current by orders of magnitude; this effect
ering reduced performance but with substantial power reduc- is due to the self-reverse biasing of the stacked transistors,
tion [76]. There are three key components for implementing which is called the stacking effect, as described earlier.
dynamic voltage scaling (DVS) in a general-purpose micro- Similar to conventional gating techniques, the
processor: an operating system that can intelligently deter- gated-ground transistor can be shared among multiple
mine the processor speed, a regulation loop that can gen- SRAM cells from one or more cache blocks. This amor-
erate the minimum voltage required for the desired speed, tizes the overhead of the extra transistor. Because the size
and a microprocessor that can operate over a wide voltage of the gated-ground transistor plays a major role in the
range. Fig. 47 shows a DVS system architecture [67]. Con- data retention capability and stability of the DRG-Cache,
trol of the processor speed must be under software control, and also affects the power and performance savings,
as the hardware alone may not distinguish whether the cur- the gated-ground transistor must be carefully sized (see
rently executing instruction is part of a compute-intensive Fig. 48) with respect to the SRAM cell transistors. While
task or a nonspeed-critical task. Supply voltage is controlled the gated-ground transistor must be made large enough to
by hard-wired frequency-voltage feedback loop, using a ring sink the current flowing through the SRAM cells during a
oscillator as a replica of the critical path. All chips operate read/write operation in the active mode and to enhance the
at the same clock frequency and same supply voltage, which data retention capability of the cache in the standby mode, a
are generated from the ring oscillator and the regulator. large gated-ground transistor may reduce the stacking effect,
5) Leakage Reduction Methods for Cache thereby diminishing the energy savings. Moreover, large
Memory: State-of-the-art microprocessor designs devote a transistors also increase the area overhead due to gating. In
large fraction of the chip area to memory structures, e.g., DRG-Cache, the gated-ground transistor is shared by a row
multiple levels of instruction and data caches, translation of SRAM cells. The gated-ground transistor is controlled
look-aside buffers, and prediction tables. For instance, by the row decoder logic of the conventional SRAM. The

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 323
Fig. 48 Anatomy of the DRG-Cache [78].

cells are turned on only when the row is being read from or
when data is written into the row. However, this requires the
row decoder to drive a larger gate capacitance associated
with the gated-ground transistor unlike conventional caches.
To maintain performance, proper sizing of the decoder is
required.
Conventional SRAM stores the data as long as the power
supply is on. This is because the cell storage nodes, which
are at zero and one, are firmly strapped to the power rails
through conducting devices (by a pulldown NMOS in one
inverter and a pull-up PMOS in the other inverter). When
the gated-ground transistor is ON, the DRG cache behaves
exactly like a conventional SRAM in terms of data storage.
Turning off the gated-ground cuts off the leakage path to the
ground. However, it also cuts off the opportunity to firmly
Fig. 49 Schematic of drowsy memory circuit [79].
strap nodes, which are at zero, to the ground. This makes it
easier for a noise source to write a one to that node. Turning
on the gated-ground transistor restores the zero data. Simula- as the pass transistors that connect the internal inverters of
tion results show that data is not lost even if the gated-ground the memory cell to the read/write lines (N1 and N2). This
transistor is turned off for indefinite time [78]. reduces the leakage through the pass transistors, since the
b) Drowsy cache: Significant leakage reduction can read/write lines are maintained in high-power mode.
also be achieved by putting the cache into a low-power c) Dynamic threshold voltage SRAM: Dynamic
drowsy mode [79]. In the drowsy mode, the information SRAM (DTSRAM) architecture can be used to reduce
in the cache line is preserved. However, the line has to be leakage energy dissipation in memory structures. Using
reinstated to a high-power mode before its contents can body biasing, the subthreshold leakage can be reduced
be accessed. One technique for implementing a drowsy without sacrificing data stability [81]. In a time-based
cache is to switch between two different supply voltages in dynamic scheme, high is assigned to the cache lines
each cache line [79]. Due to SCE in deep-submicrometer which are not accessed for a certain period (30 s–100 s),
devices, subthreshold leakage current reduces significantly and a low is assigned to the cache lines which are in
with voltage scaling [80]. The combined effect of reduced frequent use to maintain high performance [82]. Fig. 50
leakage and supply voltage gives large reduction in the depicts the two dominant leakage paths for a conventional
leakage power. six-transistor SRAM cell, the -to-ground and the bit-
Fig. 49 illustrates the circuit schematic of a SRAM cell line-to-ground leakage paths [78]. These two leakage paths
connected to the voltage controller. One PMOS pass gate make up a high percentage of the total leakage [82]. Fig. 51
switch supplies the normal supply voltage (VDD) (in the ac- shows the schematic of a DTSRAM cache line. The NMOS
tive mode), and the other supplies the low supply voltage substrate can be switched to 0 V for high performance.
(VDDLow) (in the standby mode) for the drowsy cache line. When the cache line is not in use, the substrate can be
Each pass gate is a high device to prevent leakage cur- switched to a negative voltage to reduce the leakage.
rent from the normal supply to the low supply through the Since the transition energy required for a single substrate
two PMOS pass gate transistors. A separate voltage con- bias transition is much more than the leakage energy saved
troller is needed for each cache line. By scaling the voltage during one clock cycle, transition cannot be made
of the cells to approximately 1.5 times of , the state of the every clock cycle [82]. Moreover, the performance loss
memory cell can be maintained. For a typical 70 nm process, due to negative body bias (i.e., high ) is considerable.
the drowsy voltage is about 0.3 V [79]. Since the capacitance To overcome these difficulties, properties of temporal and
of the power rail is very low, the transition time between the spatial locality of cache access can be used. In [82], a
high- and low-power state is low. High devices are used time-based scheme is described, which instead of turning

324 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

 REFERENCES

[1] V. De and S. Borkar, “Technology and design challenges for low

power and high performance,” in Proc. Int. Symp. Low Power Elec-
tronics and Design, 1999, pp. 163–168.
[2] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit De-
sign. New York: Wiley, 2000, ch. 5, pp. 214–219.
[3] C. Mead, “Scaling of MOS technology to submicrometer feature
sizes,” Analog Integrated Circuits Signal Process., vol. 6, pp. 9–25,
1994.
[4] R. Dennard et al., “Design of ion-implanted MOSFET’s with very
small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9,
p. 256, Oct. 1974.
[5] J. Brews, High Speed Semiconductor Devices, S. M. Sze, Ed. New
Fig. 50 The two dominant leakage paths (V to ground and York: Wiley, 1990, ch. 3.
bitline to ground) for a six-transistor SRAM cell. Leakage through [6] (2001) International Technology Roadmap for Semiconductors.
these two paths consist a high percentage of the total leakage [82]. International SEMATECH, Austin, TX. [Online]. Available:
http://public.itrs.net/
[7] S. Thompson, P. Packan, and M. Bohr, “Linear versus saturated drive
current: Tradeoffs in super steep retrograde well engineering,” in
Dig. Tech. Papers Symp. VLSI Technology, 1996, pp. 154–155.
[8] S. Venkatesan, J. W. Lutze, C. Lage, and W. J. Taylor, “Device drive
current degradation observed with retrograde channel profiles,” in
Proc. Int. Electron Devices Meeting, 1995, pp. 419–422.
[9] J. Jacobs and D. Antoniadis, “Channel profile engineering for
MOSFET’s with 100 nm channel lengths,” IEEE Trans. Electron
Devices, vol. 42, pp. 870–875, May 1995.
[10] W. Yeh and J. Chou, “Optimum halo structure for sub-0.1
m CMOSFET’s,” IEEE Trans. Electron Devices, vol. 48, pp.
2357–2362, Oct. 2001.
[11] A. Keshavarzi, K. Roy, and C. F. Hawkins, “Intrinsic leakage in low
power deep submicron CMOS ics,” in Proc. Int. Test Conf., 1997,
pp. 146–155.
Fig. 51 Schematic of a dynamic V SRAM set [81]. [12] R. Pierret, Semiconductor Device Fundamentals. Reading, MA:
Addison-Wesley, 1996, ch. 6, pp. 235–300.
[13] A. S. Grove, Physics and Technology of Semiconductor De-
a cache line to a high state right after its access, leaves vices. New York: Wiley, 1967.
[14] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI De-
the cache line in low for a certain period (30–100 s). vices. New York: Cambridge Univ. Press, 1998, ch. 2, pp. 94–95.
This ensures that the upcoming accesses within this period [15] , Fundamentals of Modern VLSI Devices. New York: Cam-
will not impose any energy or delay penalties. Moreover, bridge Univ. Press, 1998, ch. 3, pp. 120–128.
[16] J. M. Rabaey, Digital Integrated Circuits. Englewood Cliffs, NJ:
using the spatial locality of program reference, instead Prentice-Hall, 1996, ch. 2, pp. 55–56.
of only turning on the accessed cache line, a portion of [17] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI De-
the cache containing the accessed cache line is turned on. vices. New York: Cambridge Univ. Press, 1998, ch. 3, pp.
143–144.
Consequently, subsequent accesses occur in the turned-on [18] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous,
portion of the cache. A capacitor-discharging scheme is and A. R. LeBlanc, “Design of ion-implanted MOSFETs with very
described in [82] to implement the body-bias control circuit. small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9,
p. 256, 1974.
[19] R. Pierret, Semiconductor Device Fundamentals. Reading, MA:
Addison-Wesley, 1996, ch. 18, pp. 680–681.
IV. CONCLUSION [20] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI De-
vices. New York: Cambridge Univ. Press, 1998, ch. 3, p. 130.
With the continuous scaling of CMOS devices, leakage [21] V. De, Y. Ye, A. Keshavarzi, S. Narendra, J. Kao, D. Somasekhar,
current is becoming a major contributor to the total power R. Nair, and S. Borkar, “Techniques for leakage power reduction,”
consumption. In current deep-submicrometer devices with in Design of High-Performance Microprocessor Circuits, A. Chan-
drakasan, W. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE,
low threshold voltages, subthreshold and gate leakage have 2001, ch. 3, pp. 48–52.
become dominant sources of leakage and are expected to [22] S. Chung and C.-T Li, “An analytical threshold-voltage model of
increase with the technology scaling. GIDL and BTBT trench-isolated MOS devices with nonuniformly doped substrates,”
IEEE Trans. Electron Devices, vol. 39, pp. 614–622, Mar. 1992.
may also become a concern in advanced CMOS devices. [23] D. Fotty, MOSFET Modeling with SPICE. Englewood Cliffs, NJ:
To manage the increasing leakage in deep-submicrometer Prentice-Hall, 1997, ch. 6, pp. 113–115.
CMOS circuits, solutions for leakage reduction have to be [24] BSIM Group. MOSFET Model. Univ. California, Berkeley. [On-
line]. Available: http://www-device.eecs.berkeley.edu/~bsim3/
sought both at the process technology and circuit levels. At [25] D. Fotty, MOSFET Modeling with SPICE. Englewood Cliffs, NJ:
the process technology level, well-engineering techniques Prentice-Hall, 1997, ch. 11, p. 399.
by retrograde and halo doping are used to reduce leakage and [26] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit De-
sign. New York: Wiley, 2000, ch. 2, pp. 26–26.
improve short-channel characteristics. At the circuit level, [27] J. Mandelman and J. Alsmeir, “Anomalous narrow channel effect in
transistor stacking, multiple , dynamic , multiple trench-isolated burried channel P-Mosfets,” IEEE Electron Device
, and dynamic techniques can effectively reduce Lett., vol. 15, pp. 496–498, Dec. 1994.
[28] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI De-
the leakage current in high-performance logic and memory vices. New York: Cambridge Univ. Press, 1998, ch. 3, pp.
designs. 140–143.

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 325
 [29] , Fundamentals of Modern VLSI Devices. New York: Cam- [55] S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, and J. Yamada,
bridge Univ. Press, 1998, ch. 2, pp. 95–97. “A 1-V multi-threshold voltage CMOS DSP with an efficient power
[30] K. Schuegraf and C. Hu, “Hole injection Sio2 breakdown model for management for mobile phone application,” in Dig. Tech. Papers
very low voltage lifetime extrapolation,” IEEE Trans. Electron De- IEEE Int. Solid-State Circuits Conf., 1996, pp. 168–169.
vices, vol. 41, pp. 761–767, May 1994. [56] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, “A
[31] BSIM Group. BSIM4.2.1 MOSFET Model. Univ. 1-V high speed MTCMOS circuit scheme for power-down applica-
California, Berkeley. [Online]. Available: http://www-de- tions,” IEEE J. Solid-State Circuits, vol. 32, pp. 861–869, June 1997.
vice.eecs.berkeley.edu/~bsim3/ [57] H. Kawaguchi, K. Nose, and T. Sakurai, “A CMOS scheme for 0.5
[32] K. Cao, W.-C Lee, W. Liu, X. Jin, P. Su, S. Fung, J. An, B. Yu, and C. V supply voltage with pico-ampere stanby current,” in Dig. Tech.
Hu, “BSIM4 gate leakage model including source drain partiotion,” Papers IEEE Int. Solid-State Circuits Conf., 1998, pp. 192–193.
in Tech. Dig. Int. Electron Devices Meeting, 2000, pp. 815–818. [58] L. Wei, Z. Chen, M. Johnson, K. Roy, Y. Ye, and V. De, “Design and
[33] F. Hamzaoglu and M. Stan, “Circuit-level techniques to control gate optimization of dual threshold circuits for low voltage low power
leakage for sub-100 nm CMOS,” in Proc. Int. Symp. Low Power applications,” IEEE Trans. VLSI Systems, pp. 16–24, Mar. 1999.
Design, 2002, pp. 60–63. [59] P. Pant, V. K. De, and A. Chatterjee, “Simultaneous power supply,
[34] N. Yang, W. Henson, and J. Hauser, “Modeling study of ultrathin threshold voltage, and transistor size optimization for low-power
gate oxides using tunneling current and capacitance-voltage mea- operation of CMOS circuits,” IEEE Trans. VLSI Syst., vol. 6, pp.
surement in MOS Devices,” IEEE Trans. Electron Devices, vol. 46, 538–545, Dec. 1998.
pp. 1464–1471, July 1999. [60] T. Kuroda et al., “A 0.9 V 150 MHz 10 mW 4 mm 2-D discrete cosine
[35] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI De- transform core processor with variable-threshold-voltage scheme,”
vices. New York: Cambridge Univ. Press, 1998, ch. 2, pp. 97–99. Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., pp. 166–167,
[36] , Fundamentals of Modern VLSI Devices. New York: Cam- 1996.
bridge Univ. Press, 1998, ch. 2, pp. 99–100. [61] Y. Oowaki et al., “A sub-0.1 m circuit design with substrate-over-
[37] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit De- biasing,” in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf.,
sign. New York: Wiley, 2000, ch. 2, pp. 28–29. 1998, pp. 88–89.
[38] , Low-Power CMOS VLSI Circuit Design. New York: Wiley, [62] A. Keshavarzi, C. F. Hawkins, K. Roy, and V. De, “Effectiveness of
2000, ch. 2, pp. 27–28. reverse body bias for low power CMOS circuits,” in Proc. 8th NASA
[39] K. Nose, M. Hirabayashi, H. Kawaguchi, S. Lee, and T. Sakurai, Symp. VLSI Design, 1999, pp. 2.3.1–2.3.9.
“V -Hopping scheme to reduce subthreshold leakage for low-power [63] F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C.
processors,” IEEE J. Solid-State Circuits, vol. 37, pp. 413–419, Mar. Hu, “A dynamic threshold voltage MOSFET(DTMOS) for ultra-low
2002. voltage operation,” Dig. Tech. Papers IEEE Int. Electron Devices
[40] Y. Taur, “CMOS scaling and issues in sub-0.25 m systems,” in Meeting, pp. 809–812, 1994.
Design of High-Performance Microprocessor Circuits, A. Chan- [64] C. Wann, F. Assaderaghi, R. Dennard, C. Hu, G. Shahidi, and Y.
drakasan, W. J. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE, Taur, “Channel profile optimization and device design for low-power
2001, ch. 2, pp. 27–45. high-performance dynamic-threshold MOSFET,” in Dig. Tech. Pa-
[41] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit De- pers IEEE Int. Electron Devices Meeting, 1996, pp. 113–116.
sign. New York: Wiley, 2000, ch. 5, pp. 224–226. [65] L. Wei, Z. Chen, and K. Roy, “Double gate dynamic threshold
[42] S. Thompson, P. Packan, and M. Bohr, “MOS scaling: Transistor voltage (DGDT) SOI MOSFETS for low power high performance
challenges for the 21st century,” Intel Technol. J., 3rd quarter 1998. designs,” in Proc. IEEE Int. SOI Conf., 1997, pp. 82–83.
[43] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI De- [66] , “Design and optimization of double-gate fully-depleted SOI
vices. New York: Cambridge Univ. Press, 1998, ch. 4, pp. MOSFETS for low voltage low power CMOS circuits,” Proc. IEEE
184–187. Int. SOI Conf., pp. 69–70, 1998.
[44] D. Fotty, MOSFET Modeling with SPICE. Englewood Cliffs, NJ: [67] S. Lee and T. Sakurai, “Run-time voltage hopping for low-power
Prentice-Hall, 1997, ch. 11, pp. 396–397. real-time systems,” Proc. IEEE/ACM Design Automation Conf., pp.
[45] V. De, Y. Ye, A. Keshavarzi, S. Narendra, J. Kao, D. Somasekhar, 806–809, 2000.
R. Nair, and S. Borkar, “Techniques for leakage power reduction,” [68] C. H. Kim and K. Roy, “Dynamic V scaling scheme for active
in Design of High-Performance Microprocessor Circuits, A. Chan- leakage power reduction,” in Proc. Conf. Design, Automation and
drakasan, W. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE, Test Europe, 2002, pp. 163–167.
2001, ch. 3, pp. 52–55. [69] A. J. Bhavnagarwala, B. L. Austin, K. A. Bowman, and J. D.
[46] Y. Ye, S. Borkar, and V. De, “New technique for standby leakage Meindl, “A minimum total power methodology for projecting limits
reduction in high-performance circuits,” in Dig. Tech. Papers Symp. on CMOS GSI,” IEEE Trans. VLSI Syst., vol. 8, pp. 235–251, June
VLSI Circuits, 1998, pp. 40–41. 2000.
[47] Z. Chen, M. Johnson, L. Wei, and K. Roy, “Estimation of standby [70] S. Tyagi et al., “A 130 nm generation logic technology featuring
leakage power in CMOS circuits considering accurate modeling of 70 nm transistors, dual Vt transistors and 6 layers of Cu intercon-
transistor stacks,” in Proc. Int. Symp. Low Power Electronics and nects,” in Dig. Tech. Papers Int. Electron Devices Meeting, 2000,
Design, 1998, pp. 239–244. pp. 567–570.
[48] Z. Chen, L. Wei, A. Keshavarzi, and K. Roy, “IDDQ testing for deep [71] M. Takahashi et al., “A 60-mw MPEG4 video codec using clustered
submicron ICs: Challenges and Solutions,” IEEE Des. Test Comput., voltage scaling with variable supply-voltage scheme,” IEEE J. Solid-
pp. 24–33, Mar.–Apr. 2002. State Circuits, vol. 33, pp. 1772–1780, Nov. 1998.
[49] D. Duarte, Y. F. Tsai, N. Vijaykrishnan, and M. J. Irwin, “Evaluating [72] Y. Kanno, H. Mizuno, K. Tanaka, and T. Watanabe, “Level
run-time techniques for leakage power reduction,” in Proc. 7th Asia converters with high immunity to power-supply bouncing for
and South Pacific and 15th Int. Conf. VLSI Design, 2002, pp. 31–38. high-speed Sub-1-V LSI’s,” in Dig. Tech. Papers Symp. VLSI
[50] M. C. Johnson, D. Somasekhar, and K. Roy, “Leakage control with Circuits, 2000, pp. 202–203.
efficient use of transistor stacks in single threshold CMOS,” in Proc. [73] T. Fuse, A. Kameyama, M. Ohta, and K. Ohuchi, “A 0.5 V
ACM/IEEE Design Automation Conf., 1999, pp. 442–445. power-supply scheme for low power LSI’s using multi-Vt SOI
[51] N. Sirisantana, L. Wei, and K. Roy, “High-performance low-power CMOS technology,” in Dig. Tech. Papers Symp. VLSI Circuits,
CMOS circuits using multiple channel length and multiple oxide 2001, pp. 219–220.
thickness,” in Proc. Int. Conf. Computer Design, 2000, pp. 227–232. [74] L. R. Carley and A. Aggarwal, “A completely on-chip voltage reg-
[52] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI De- ulation technique for low power digital circuits,” in Proc. Int. Symp.
vices. New York: Cambridge Univ. Press, 1998, ch. 4, p. 194. Low Power Electronics and Design, 1999, pp. 109–111.
[53] S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. [75] R. K. Krishnamurthy, A. Alvandpour, V. De, and S. Borkar, “High-
Yamada, “1-V power supply high-speed digital circuit technology performance and low-power challenges for sub-70 nm micropro-
with multi-threshold voltage CMOS,” IEEE J. Solid-State Circuits, cessor circuits,” in Proc. IEEE Custom Integrated Circuits Conf.,
vol. 30, pp. 847–854, Aug. 1995. 2002, pp. 125–128.
[54] J. Kao, A. Chandrakasan, and D. Antoniadis, “Transistor sizing [76] T. D. Burd, T. A. Pering, A. J. Stratakos, and R. W. Brodersen, “A
issues and tool for multi-threshold CMOS technology,” in Proc. dynamic voltage scaled microprocessor system,” IEEE J. Solid-State
ACM/IEEE Design Automation Conf., 1997, pp. 495–500. Circuits, vol. 35, pp. 1571–1580, Nov. 2000.

326 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 2, FEBRUARY 2003

 [77] S. Manne, A. Klauser, and D. Grunwald, “Pipeline gating: Specu- Saibal Mukhopadhyay (Student Member,
lation control for energy reduction,” in Proc. 25th Annu. Int. Symp. IEEE) received the B.E. degree in electronics
Computer Architecture, 1998, pp. 32–141. and telecommunication engineering from
[78] A. Agarwal, H. Li, and K. Roy, “DRG-Cache: A data retention gated- Jadavpur University, Calcutta, India, in 2000.
ground cache for low power,” in Proc. Design Automation Conf., He is working toward the Ph.D. degree in
2002, pp. 473–478. electrical engineering at Purdue University, West
[79] K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, Lafayette, IN.
“Drowsy caches: Simple techniques for reducing leakage power,” His research interests include low-power
in Proc. 29th Annual Int. Symp. Computer Architecture, 2002, pp. high-performance digital design using deep-sub-
148–157. micrometer CMOS, and circuit design with
[80] S. Wolf, Silicon Processing for the VLSI Era. Sunset Beach, CA: nanodevices.
Lattice Press, 1995, vol. 3, The Submicron MOSFET, pp. 213–222.
[81] H. Mizuno, “An 18 A (A standby current 1.8-V, 200-MHz micro-
processor with self-substrate-biased data-retention mode,” IEEE J.
Solid-State Circuits, vol. 34, pp. 1492–1500, Nov. 1999. Hamid Mahmoodi-Meimand (Student
[82] C. H. Kim and K. Roy, “Dynamic Vt SRAM: A leakage tolerant Member, IEEE) received the B.S. degree in
cache memory for low voltage microprocessors,” presented at the electrical engineering from Iran University of
Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug. Science and Technology, Tehran, Iran, in 1998
2002. and the M.S. degree in electrical engineering
from the University of Tehran, Tehran, in 2000.
He is working toward the Ph.D. degree in
electrical engineering at Purdue University, West
Lafayette, IN.
Kaushik Roy (Fellow, IEEE) received the His research interests include low-power and
B.Tech. degree in electronics and electrical high-performance circuit design for deep-submi-
communications engineering from the Indian In- crometer CMOS technologies.
stitute of Technology, Kharagpur, India, in 1983
and the Ph.D. degree in electrical and computer
engineering department from the University of
Illinois, Urbana-Champaign, in 1990.
He was with the Semiconductor Process and
Design Center of Texas Instruments, Dallas, TX,
where he worked on field programmable gate
array architecture development and low-power
circuit design. In 1993, he joined the electrical and computer engineering
faculty at Purdue University, West Lafayette, IN, where he is currently a
Professor. He has published more than 200 papers in refereed journals and
conferences, holds five patents, and is the coauthor of Low-Power CMOS
VLSI Design (New York: Wiley, 1998). His research interests include VLSI
design/CAD with particular emphasis in low-power electronics for portable
computing and wireless communications, VLSI testing and verification,
and reconfigurable computing.
Dr. Roy received the National Science Foundation Career Development
Award in 1995, the IBM Faculty Partnership Award, the ATT/Lucent
Foundation Award, and Best Paper Awards at the 1997 International Test
Conference and the 2000 International Symposium on Quality of IC
Design, and is currently a Purdue University Faculty Scholar Professor. He
is on the editorial boards of IEEE DESIGN AND TEST OF COMPUTERS, IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON
VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. He was also Guest
Editor for the special issues on low-power VLSI of IEEE DESIGN AND TEST
OF COMPUTERS (1994) and IEEE TRANSACTIONS ON VERY LARGE SCALE
INTEGRATION (VLSI) SYSTEMS (June 2000).

ROY et al.: LEAKAGE CURRENT MECHANISMS AND LEAKAGE REDUCTION TECHNIQUES IN DEEP-SUBMICROMETER CMOS CIRCUITS 327