Instructions Formats

IAS MACHINE

MEMORY: 4096 WORDS

WORD LENGTH: 40 BITS
STORED PROGRAM CONCEPT
DATA: SIGN BIT AND 39 BIT VAULE
TWO 20 BIT ISTRUCTIONS
EACH INSTRUCTION: 8 BIT OPCODE, 12 BIT
ADDRESS (POINTS TO THE OPERAND IN THE
MEMORY)
IAS MEMORY FOMATS
Fetch / Execute Cycle

V.Saritha, SCSE, VIT University

 IAS Computer AC MQ

MAR🡨PC
MBR🡨M[MAR] Arithmetic & Logic Circuits
Input/output
IBR🡨MBR<20..39> IBR🡨MBR<20..39> Equipments
IR🡨MBR<0..7> IR🡨MBR<0..7>
MAR🡨MBR<8..19> MAR🡨MBR<8..19> MBR
MBR🡨M[MAR] MBR🡨AC
AC🡨MBR M[MAR}🡨MBR
IR🡨IBR<0..7> IR🡨IBR<0..7>
MAR🡨IBR<8..19> IBR PC
MBR🡨M[MAR]
AC🡨AC + MBR Main
PC🡨PC+1 Memory
MAR🡨PC
IR
MBR🡨M[MAR] MAR

Control
Circuits
 ACAC= MQ
MEMORY 7
3
1. LOAD M(X) 500, ADD M(X)
501
2. STOR M(X) 500, (Other Ins)
.....
500. 3
50
501. 4 LOADMBR
ADD MBR=
50
M(X)
(Other
M(X) 0
3STOR0
Ins) 4
501
M(X)
PC 21
MA
R
501
500
21
MB LOAD M(X) 500, ADD M(X)
R
STOR M(X) 500,
43 (Other Ins)
501
IR LOAD
STOR
ADD M(X)M(X)
IBR ADD
(Other
M(X) Ins)
501
AC 37
Add
50
IBR PC
Mar
MAR ==1
PC ←
1
M(X) PC
2
←PC 3 ADD
LOAD M(X) 500,
M(X) 501
4
MAR STOR M(X) 500,
IR MAR
MAR = =
MAR =add
1= = (Other Ins)
=500
add
add
501
500 ==
2 add
501
1500
2
 ACAC= MQ
MEMORY 7
3
1. LOAD M(X) 500, ADD M(X)
501
2. STOR M(X) 500, (Other Ins)
.....
500. 3
50
501. 4 LOADMBR
ADD MBR=
50
M(X)
(Other
M(X) 0
3STOR0
Ins) 4
501
M(X)
PC 21
MA
R
501
500
21
MB LOAD M(X) 500, ADD M(X)
R
STOR M(X) 500,
43 (Other Ins)
501
IR LOAD
STOR
ADD M(X)M(X)
IBR ADD
(Other
M(X) Ins)
501
AC 37
Add
50
IBR PC
Mar
MAR ==1
PC ←
1
M(X) PC
2
←PC 3 ADD
LOAD M(X) 500,
M(X) 501
4
MAR STOR M(X) 500,
IR MAR
MAR = =
MAR =add
1= = (Other Ins)
=500
add
add
501
500 ==
2 add
501
1500
2
Instruction
• Definition:

• Instruction is a statement by which the operation of CPU is

determined.
• These instructions referred as “Machine instructions or computer
Instructions”

• The collection of different instructions that the CPU can execute is referred to
as the CPU’s instruction set.
•What must an instruction set
specify…?
• Which Operation to perform
• Where to find the operand or
operands
• Where to put the result, if there is
result
• Where to find the next instruction
Instruction Representations
• Each instruction is represented by sequence of bits
• The instruction is divided into two fields
• Opcode field
• Operand field
• This operand field further divided into one to four fields.
• This layout of the instruction is known as the “Instruction
Format”
• Simple instruction format
Operand Operand Result Next
Opcode
Address1 Address2 Address1 Instruction
CLASSIFICATION OF INSTRUCTIONS
IAS Instruction set
IAS Instruction set (continued)
Problem

Write an appropriate assembly language code for the following

operation and interpret to Von Neumann IAS architecture
X=Y*Z
// Where Y->40 bit data and Z->40 bit data
Result would be more than 40 bit.
 EXAMPLE ALP (IAS)
Assume that data variables ‘Y’ & ‘Z’ available at memory locations
801 & 802 resly. And X will be stored 803 onwards.
LOAD MQ, M(801) MQ🡨M[801]
Address values
MUL M(802) Ac🡨MQ * M[802] 801 Y

STOR M(803) M[803]🡨AC 802 Z

LOAD MQ AC🡨MQ 803 Result [msb]

STOR M(804) M[804]🡨AC 804 Result [lsb]

Example Problems
Write an Assembly language programming for the following
expressions using IAS computer Instruction set and interpret to
the flow of IAS computer
1. A=(B-C)*D
2. A=B*(C+D)

Make necessary assumptions.

Computer Components:
Top Level View
 Instruction Cycle
● The IAS operates repetitively performing an instruction
cycle.
● Each instruction cycle consists of Two subcycles.
● Two steps:
● Fetch
● Execute
 Fetch Cycle
● Program Counter (PC) holds address of next instruction to
fetch

● Processor fetches instruction from memory location pointed to

by PC

● Increment PC
● Unless told otherwise

● Instruction loaded into Instruction Register (IR)

● Processor interprets instruction and performs required actions

 Execute Cycle
● Processor-memory
● data transfer between CPU and main memory
● Processor- I/O
● Data transfer between CPU and I/O module
● Data processing
● Some arithmetic or logical operation on data
● Control
● Alteration of sequence of operations
● e.g. jump
● Combination of above
Instruction Cycle State Diagram
Instruction state cycle diagram (cont..)
• Instruction address calculation (iac):
• Determine the address of the next instruction to be executed. Adding a fixed
number to a next number.
• Instruction fetch: (if)
• Read the instruction from its memory location into the processor.
• Instruction operation decoding (iod)
• Analyze instruction to determine type of operation to be performed and
operand(s) to be used.
• Operand Address Calculation: (oac)
• If the operation involves the reference to an operand in memory or available
via I/O, then determine the address of the operand.
• Operand Fetch (of):
• Fetch the operand from memory or read it from I/O.
• Data Operation (do):
• Perform the operation indicated in the instruction.
• Operand store (os)
• Write the result into memory or out to I/O.
Characteristics of Hypothetical Machine
Characteristics of Hypothetical Machine (cont..)

• The processor contains a single data register called an accumulator

(AC). Both instructions and data are 16 bits long. Thus it is convenient
to organize memory using 16 bit words.
• The instruction format provides 4 bits for the opcode, so that there
can be as many as 24 =16 different opcodes, and upto 212= 4096(4K)
words of memory can be directly addressed.
Example of Program Execution