LAB 2, E3-238 ANALOG VLSI CIRCUITS, AUG-DEC 2021, , INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

E3-238: Analog VLSI Circuits

Lab 2
September 2021

INSTRUCTIONS
1. Format the graphs exactly as required in the problem.
2. Include duly filled Table 2 and Table 3 in the report.
3. Submit your report through the “Submit work” link provided in Microsoft Teams.

PART 1: MOSFET CHARACTERIZATION

Consider a MOSFET which consists of an n+ polysilicon gate on a 26 Å thick silicon-dioxide layer over
p- type substrate with NA = 6 x 1016 cm-3. The length and width of the gate are 0.5 𝜇𝑚 and 4 𝜇𝑚,
respectively. The carrier mobility in the inversion layer is 270 𝑐m2/𝑉. 𝑠. The zero-bias small-signal
junction (source/drain to bulk) capacitances are 30 𝑓𝐹. The overlap capacitance between gate and
diffusion (source/drain) is 81.5 p𝐹/m and carrier saturation velocity is given as 5.6 x 105 m/s. In
addition, a DC operating point for the transistor is known, i.e., 𝐼d = 300 𝜇𝐴 at 𝑉𝑔𝑠 = 0.80 𝑉, 𝑉𝑑𝑠 = 1.2 𝑉,
and 𝑉𝑠𝑏 = 0.6 𝑉. Assume the channel-length modulation parameter 𝜆 = 0.1 𝑉-1 and ignore the sidewall
junction capacitances.
a. Derive the complete small-signal high-frequency model for the transistor about the DC
operating point.1
b. Create a Spectre model for the transistor by setting parameter values in the template2 shown in (10
Table 1, and simulate the following DC characteristic curves3 with 𝑉𝑑𝑑 = 1.8 𝑉: )
1. Output characteristics: 𝐼𝑑 vs. 𝑉𝑑𝑠 for 𝑉𝑔𝑠 = 𝑙𝑖𝑛𝑠𝑝𝑎𝑐𝑒 (0 𝑉, 𝑉𝑑𝑑, 6) 4, 𝑉𝑠𝑏 = 0 𝑉, and
𝑉𝑑𝑠 = 𝑙𝑖𝑛𝑠𝑝𝑎𝑐𝑒 (0 𝑉, 𝑉𝑑𝑑, 100)
2. Transfer characteristics: 𝐼𝑑 vs. 𝑉𝑔𝑠 for 𝑉𝑑𝑠 = 𝑙𝑖𝑛𝑠𝑝𝑎𝑐𝑒 (0 𝑉, 𝑉𝑑𝑑, 6), 𝑉𝑠𝑏 = 0 𝑉, and
𝑉𝑔𝑠 = 𝑙𝑖𝑛𝑠𝑝𝑎𝑐𝑒 (0 𝑉, 𝑉𝑑𝑑, 100)
3. Back-gate characteristics: 𝐼𝑑 vs. 𝑉𝑠𝑏 for 𝑉𝑑𝑠 = 𝑙𝑖𝑛𝑠𝑝𝑎𝑐𝑒 (0 𝑉, 𝑉𝑑𝑑, 6), 𝑉𝑔𝑠 = 0 𝑉, and
𝑉𝑠𝑏 = 𝑙𝑖𝑛𝑠𝑝𝑎𝑐𝑒 (0 𝑉, 𝑉𝑑𝑑, 100)
c. Obtain the following graphs that relate the small-signal quantities to the bias parameters. (06
4. 𝑔m, 𝑟0, and 𝑓T vs. 𝑉𝑔𝑠 for 𝑉𝑑𝑠 = 1.5 𝑉 )
5. 𝑔m, 𝑟0, and 𝑓T vs. 𝐼d for 𝑉𝑑𝑠 = 1.5 𝑉
6. 𝑔m/𝐼d and 𝑓T vs. 𝐼d/𝑊 for 𝑉𝑑𝑠 = 1.5 𝑉
Repeat (b) and (c) for the nmos2v5 transistor of the tsmc18 library.
Explain the reasons for deviation from the square-law model. (Write individual response in the report)

(04)
1
Assume reasonable values for the unknown process parameters (if required).
2
Delete the parameter if the given information is not sufficient to calculate its value.
3
Format the graphs (labels, ranges, scales, and parameters) as mentioned in the problem statement.
4
The expression 𝑙𝑖𝑛𝑠𝑝𝑎𝑐𝑒(𝑠𝑡𝑎𝑟𝑡, 𝑠𝑡𝑜𝑝, 𝑁) represents a set of N numbers spaced linearly between the start and stop values.
5
The name nmos2v refers to a 1.8V nominal VT NMOS transistor with a 1.8𝑉 inter-terminal voltage limit.

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LAB 2, E3-238 ANALOG VLSI CIRCUITS, AUG-DEC 2021, , INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

Table 1 Level-2 MOSFET model template.

model myNMOS mos2 type=n

+ vto= // threshold voltage at zero body bias
+ kp= // transconductance parameter (𝜇𝑛𝐶𝑜𝑥)
+ lambda= // channel-length modulation parameter
+ phi= // surface potential at strong inversion
+ gamma= // body effect parameter
+ uo= // carrier surface mobility
+ vmax= // carrier saturation velocity
+ ucrit= // critical field for mobility degradation
+ uexp= // critical field exponent for mobility degradation
+ nsub= // channel doping concentration
+ cgso= // gate-source overlap capacitance
+ cgdo= // gate-drain overlap capacitance
+ cgbo= // gate-body overlap capacitance
+ cbs= // zero-bias bulk-source junction capacitance
+ cbd= // zero-bias bulk-drain junction capacitance
+ pb= // bulk-junction built-in potential
+ mj= // bulk-junction grading coefficient

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LAB 2, E3-238 ANALOG VLSI CIRCUITS, AUG-DEC 2021, , INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

PART 2: CURRENT MIRROR DESIGN

Explore current mirror using nmos2v transistor cells from the tsmc18 library.

(10)
a) Design a current mirror for input reference current of Ii = 10 A and output current of Io = 10 A.
Sweep Vout and plot % error ((𝐼𝑜,𝑠𝑖𝑚 − 𝐼𝑜 ) × 100/𝐼𝑜 as a function of Vout. How can you reduce
error? (Hint: increase L). Show change in error with increasing L for a fixed Vout (for example Vout = (5)
VDD). Why does increasing L reduces error?
b) In the above design, sweep temperature from -40 to 150 C and plot the effect on % error. Can you
reduce error by increasing Vod? (5)
c) Repeat the exercise for Ii = 100 nA, and Io = 1A. Note that you would require large L to satisfy
sufficient Vod. Compare the estimated area of design a) and c). (5)
d) Use the designs of a) and c) and provide a step in the input current Ii with rise time of 1ns. Plot the
transient settling of Io with time. Comment on the results of a) and c).

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LAB 2, E3-238 ANALOG VLSI CIRCUITS, AUG-DEC 2021, , INDIAN INSTITUTE OF SCIENCE, BANGALORE (560012), KARNATAKA, INDIA

PART 3: CMOS AMPLIFIER DESIGN

Find an optimal design7 for the voltage amplifier shown in with the following specifications.
1. Voltage gain ≥ 26 𝑑𝐵
2. -3-dB bandwidth ≥ 60 𝑀𝐻𝑧
3. Power dissipation ≤ 2.5 𝑚𝑊 (10
4. Output impedance ≤ 50 Ω )
5. Output swing ≥ 0.8 𝑉

VDD = 0.9V

VSS = -0.9V

Use the nmos2v, and pmos2v transistor cells from the tsmc18 library.

a. Explain your choice of the DC operating point based on the trade-offs between the specifications
given.
b. Derive the expressions for frequency-dependent voltage gain, input impedances, and output
(04
impedance from the small-signal model of the circuit. Obtain the small-signal model parameters )
by simulating the transistor at the chosen bias point.
c. Simulate the circuit using AC analysis and include the following graphs in the report:
(06+04)
1. Voltage gain in dB versus frequency showing the -3 𝑑𝐵 corner point.
2. Input resistance (left y-axis) and input reactance (right y-axis) versus frequency.
3. Output resistance (left y-axis) and output reactance (right y-axis) versus frequency. (06)
d. What is the ratio between the bias current and signal current (peak amplitude) in M3? Comment
on the applicability of the small-signal model for the source follower stage. Also, explain the
limiting factors for the voltage gain, bandwidth, and output resistance. (Write individual
response in the report)
(02+02+06)
HINT
The design problem is essentially an optimization problem where an objective function is to be
maximized (or minimized) satisfying the constraints. A possible choice for the objective function could
be a function between 𝑔m𝑟0𝑓T/𝐼D (performance metric) and 𝐼D/𝑊 (design or decision variable)8. The
objective would then be to find the 𝐼𝐷/𝑊 which maximizes the 𝑔𝑚𝑟0𝑓𝑇/𝐼𝐷.

7
The optimal design implies finding the optimum transistor sizes and bias voltages (or currents).
8 What transistor lengths and which transistor’s 𝑔m𝑟0𝑓T/𝐼D and 𝐼D/𝑊 to be used is left to the designer’s choice

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