Input and Output Facilities

BACS1113 Computer
Organization and Architecture
Overview
● I/O Modules
● Programmed I/O
● Interrupts
○ Servicing Interrupts
○ The Uses of Interrupts
○ Multiple Interrupts and Prioritization

● Direct Memory access (DMA)

● I/O System Architecture
○ I/O Bus Architecture
○ Channel Architecture
I/O Modules
● Serves as an interface between the CPU and the specific device,
accepting commands from the CPU on one side and controlling the
device on the other.

Simple I/O Configuration

A Slightly More Complex I/O Module Arrangement
I/O Modules
I/O Modules functions :

● Recognizes messages addressed to it and accepts commands from the CPU

● Provides a buffer where the data from memory can be held until it can be
transferred to the disk
● Provides the necessary registers and controls to perform a direct memory
transfer.
● interrupt capability, to notify the CPU when the operation is completed.
I/O Modules

CPU
Interface Device
Interface
● CPU interface : performs CPU interfacing tasks:
○ Accepting I/O commands from the CPU
○ Sending interrupts and status information to the CPU.
● Device interface : supplies control of the device:
○ Moving the head to the correct track in a disk drive and rewinding tape.
I/O Modules
● Accepts I/O requests and interacts directly with the device to satisfy
those
Requests.
● It would be difficult to program the CPU to provide the correct types of
signals to operate I/O devices. The CPU time required to control these
devices would reduce the usefulness of the system
I/O Modules
● simple CPU I/O instructions can be used to control complex operations.
● simplify the task of interfacing peripheral devices to a CPU. This off
load a considerable amount of work from the CPU.
● Make it possible to control I/O to a peripheral with a few simple I/O
commands.
● Support DMA → CPU is free to perform other tasks.
● provide the specialized circuitry to interface different types of
peripherals.
Input Output
Techniques
I/O Techniques
● Programmed I/O. (PIO)
○ CPU controlled I/O
● Interrupt-driven I/O.
○ External input controls
● Direct Memory Access. (DMA).
○ Method for transferring data between main
memory and a device that bypasses the CPU
Programmed I/O
● The simplest method for performing I/O
● An I/O module is connected to a pair of I/O registers in the CPU via a
bus
Programmed I/O
Input from peripheral is transferred from:

I/O Data register (One word at a time)

I/O Module

Accumulator register

CPU
Programmed I/O
Output data will be passed from:

I/O Module
I/O Data register

I/O Module

Accumulator register

I/O Module
CPU
Programmed I/O
● Each instruction produces a single input or output.
● Address information must be sent with the I/O
instruction to recognize I/O devices individually.
● Full instruction fetch-execute cycle for each I/O data
word (very slow)
● Primary use : keyboards
Example: Programmed I/O
1. CPU executes INPUT 24 instruction. Address 24 is copied to the I/O
address register.
Example: Programmed I/O
2. Address 24 is recognized by the keyboard I/O module. A read/write
control line indicates that the instruction is an INPUT.
Example: Programmed I/O
3. A buffer in the I/O module holds a keystroke, in this case ASCII 68,
the letter “D”. The data is transferred to the I/O data register.
Example: Programmed I/O
4. From there it is copied to the appropriate accumulator or general-
purpose register, completing the operation.
Interrupts
● Signal that causes the CPU to alter its normal flow on
instruction execution.
○ Free CPU from waiting for events
○ Provides control for external input
● Examples of Interrupt
○ An unexpected user input
○ Illegal instructions
○ Multitasking, multiprocessing
○ An abnormal situation
Interrupts
● Interrupt line
○ Special control lines to the CPU that provides
interrupt capabilities.
● The messages sent to the computer on these lines
are known as interrupts.
● Cause the computer to suspend the program being
executed and jump to a special interrupt processing
program.
Servicing Interrupts
1. Suspends program in progress
2. Saves context, including last instruction executed
and data values in registers, in the PCB (process
control block)
3. Branches to interrupt handler program (interrupt
routine)
Servicing Interrupts
1. Before interrupt arrives,
program A is executing.
The program counter points
to the current instruction.
Servicing Interrupts
2. When the interrupt is received
by the CPU, the current instruction
is completed, all the registers are
saved in the stack area (or in a
special area known as a process control block).
The PC is loaded with the starting location of
program B, the interrupt handler program.
This causes a jump to program B, which
becomes the executing program.
Servicing Interrupts
3. When the interrupt routine is complete,
the registers are restored, including the
program counter, and the original
program resumes exactly where it left off
The uses of Interrupts
1. THE INTERRUPT AS AN EXTERNAL EVENT NOTIFIER

● Notifying the CPU of external events that require action.

● Free CPU from polling.
● User to control the computer from input device.
● E.g. Keyboard Input, Real-time or time-sensitive system
Using a keyboard handler Interrupt
The uses of Interrupts
2. THE INTERRUPT AS A COMPLETION SIGNAL

● Controls the flow of data to the output devices.

● Notify the computer of the completion of a particular course of action.
● Example :
○ Printer ready - printer to control the flow of characters to the
printer in an efficient way.
Using a printer
handler input
The uses of Interrupts
3. THE INTERRUPT AS A MEANS OF ALLOCATION CPU TIME

● Allocating CPU time to different programs that are sharing the CPU.
● Example :
○ Time sharing
○ Since the CPU can only execute one program at a time. Computer
system share the CPU by allocating small segment of time to each
program, in rapid rotation among them.
Using an Interrupt
For Time Sharing
The uses of Interrupts
4. THE INTERRUPT AS AN ABNORMAL EVENT INDICATOR

● Handle abnormal events that affect operation of the computer system.

● Usage is similar to external input events, but in this case, the events
are directed at the problems within the computer system itself.
● Example :
○ Power failure, Illegal instruction, Hardware error.
Software Interrupts
● Generated by Operating system (Windows Kernel).
● The interrupt instruction works in the same way as a hardware
interrupt, saving appropriate registers and transferring control to an
interrupt handling procedure.
● Example :
○ Handling timer expiration
○ Exception Handler (Try-Catch Exceptions)
Multiple Interrupts and Prioritization
● When an interrupt occurs
○ Are there other interrupts already waiting
service?
○ How does the computer identify the interrupting
device?
● Can be handled by assigning priorities to each
interrupt.
Multiple Interrupts and prioritization
● Processing methods to identify devices that initiate
the interrupt :
○ Vectored interrupt : the address of the
interrupting device is included as part of the
interrupt.
○ Polled interrupt : the general interrupt that
shared by all devices. Identifies the Interrupting
device by polling each device.
Vectored Interrupt Processing
Polled Interrupt Processing
Multiple Interrupts
Past Year Question
Answer
Direct Memory Access (DMA)
● A method of transferring data between peripherals &
memory without using the CPU.
● Transferring large blocks of data.
● Direct transfer, CPU not actively involved itself.
● Required conditions for DMA
○ I/O interface & memory must be connected
○ I/O module must be capable of read & write to memory
○ Conflicts between the CPU & the I/O module must be
avoided
Direct Memory Access (DMA)
● The transfer is initiated by a program in the CPU,
using programmed I/O, but the CPU can then bypass
for the remainder of the transfer.
● The I/O module will notify the CPU with an interrupt
when the transfer is completed.
● Once this has occurred, the data is in memory, ready
for the program to use.
Direct Memory Access (DMA)
E.g. : Consider a program that sorts a block of numbers.

● To operate efficiently,
● Transfer the entire block of numbers from HDD to
memory
● Perform sorting in the memory.
● Transfer the data back to HDD.
Direct Memory Access (DMA)
● For DMA to take place, three primary conditions must be met.

1st:

● There must be a method to connect together the I/O interface and

memory.
● In some systems, both are already connected to the same bus, so this
requirement is easily met.
Direct Memory Access (DMA)
2nd:

● The I/O module associated with the particular device

must be capable of reading and writing to memory.
● It does so by simulating the CPU’s interface with
memory.
● Specifically, the I/O module must be able to load a
memory address register and to read and write to a
memory data register.
Direct Memory Access (DMA)
3rd:

● There must be a mean to avoid conflict between the CPU and the I/O
module.
● It is not possible for the CPU and a module controlling disk I/O to load
different addresses into MAR at the same instant, or for two different
I/O modules to transfer data between I/O and memory on the same
bus at the same instant.
Direct Memory Access (DMA)
● Since the CPU is not actively involved during the
transfer, the CPU can be used to perform other tasks
during the time when I/O transfers are taking place.
● DMA is not limited to just disk-to-memory transfer. It
can be used with other high-speed devices.
● DMA is an effective mean to transfer video data from
memory to the video I/O system for rapid display.
Direct Memory Access (DMA)
FOUR pieces of data must be provided to initiate the
DMA transfer :
1. The location of the data on the I/O device.
2. The starting location of the block of data in
memory.
3. The size of block to be transferred.
4. The direction of transfer.

● Read (I/O -> memory)

● Write ( memory -> I/O )
DMA Initiation & Control
1. Programmed I/O used to
prepare I/O module for transfer
by providing required information
and initiating transfer.

2. DMA transfer. In this case

data is transferred from disk
to memory.

3. Upon completion, disk

controller sends completion
interrupt to CPU.
Direct Memory Access (DMA)
● It takes several instructions to initiate a DMA transfer
● Thus, it is not useful to perform a DMA transfer for
very small amounts of data.
● If the data to transfer is small, or the computer only
perform single task, the time freed up by DMA
cannot be used productively.
CPU-Memory-I/O
Architecture
CPU-Memory-I/O Architecture
Basic CPU-Memory-I/O Pathway
Input/Output System Architectures
● Bus architecture
○ used in almost all personal computers.

● Channel architecture.
○ found primarily in IBM mainframe computers
I/O Bus Architecture
● Bus Architecture
○ Backbone for connections of various components,
memory and I/O, to the CPU.
● Simplest form
○ Single system bus connects the CPU to
memory and to all various I/O modules that
control I/O devices
Bus Architecture
● Consists of a number of interconnected buses.
○ CPU bus, PCI bus, ISA bus
● These buses are interconnected by Bus interfaces
(expansion bus interface, bus bridges)
○ Expand the flexibility by converting bus signals
from one to another.
Bus Architecture
● The interconnect ability makes it possible to design
and use industry standard buses on equipment of
different vendors.
○ Connection of I/O devices standardized across a
wide range of equipment types and
manufacturers.
○ The major aspect of Open Architecture concept.
Bus Configuration
Channel Architecture
● Used in all IBM mainframe computers since late 70s
● Channel subsystem
○ Separate I/O processor that serves as a separate
CPU for I/O operations
○ Channel control words
○ Programs stored in memory, independent of CPU
○ Transfer data between memory and an I/O device
using DMA
Channel Architecture
● Sub channels
○ Each of it is connected to a control unit module
through one or more
channel paths
○ Similar role to a device controller
● Up to 8 different channel paths between channel
subsystem and
control unit (used as alternative, if busy)
I/O Channel Architecture