26 October - 20 November, 2009: Fpga Design & VHDL Fundamentals of Fpgas

2065-19
Advanced Training Course on FPGA Design and VHDL for Hardware

Simulation and Synthesis
26 October - 20 November, 2009
FPGA Design & VHDL

Fundamentals of FPGAs
Nizar Abdallah
ACTEL Corp. 2061 Stierlin Court Mountain View
CA 94043-4655
U.S.A.
FPGA Design & VHDL
Nizar Abdallah
[email protected]
October 2009
Fundamentals of FPGAs
Agenda
FPGA Fundamentals
Mixed-Signal FPGAs
Actel Fusion Architecture
FPGA Design Considerations
Trends
Choosing an FPGA
Development Tools
Summary
Actel Corporation Confidential © 2009 3

FPGA Fundamentals: A Brief History
Before FPGAs

Before FPGAs: Simple PLDs (SPLDs)–PROMs
Maxfield, Clive
“The Design Warrior’s Guide to FPGAs”
Elsevier

Before FPGAs: Simple PLDs (SPLDs)–PLAs
Maxfield, Clive
Elsevier

Before FPGAs: Simple PLDs (SPLDs)–PALs
Maxfield, Clive
Elsevier

Before FPGAs: Complex PLDs (CPLDs)
Maxfield, Clive
Elsevier

The GAP

FPGA Fundamentals: Definition
Field Programmable Gate Array
A large number of logic gates in an IC

array that can be connected
(configured) electrically
The Four Components of FPGAs

The Configuration Element
The Logic Module
The Memory
Control Circuits/Special Features

FPGA Fundamentals: Basic Architecture
Generic FPGA Architecture
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FPGA Fundamentals: Routing Technologies
The Interconnect Switch
XXX

M2M Antifuse
Bit Select 1 Bit Select 2 Input

Word line
VCC VCC
Floating Gate
MEMORY
•Erase SWITCH
•Program
•Sense
Word Select / Bias
Bit A B Bit
Line Line
Flash Output
SRAM
SRAM Flash Anti-fuse
1T
6T
Best of Both Worlds

Reprogrammable Reprogrammable Nonvolatile
& Nonvolatile
Large Switch Small Switch Smallest Switch

expensive wires cheap wires cheapest wires
Low Logic Utilization High Logic Utilization Highest Logic Utilization
typ 60% typ >85% typ >90%
ProASIC, ProASICPlus, ProASIC3 Routing Switch

Programming Technologies
Feature SRAM Anti-fuse Flash
Behind by 1-2 Behind by 1-2
Technology node State of the art
generations generations
Reprogrammable Yes No Yes
Preserves configuration when off No Yes Yes
Requires external configuration

Yes No No
file
Instantly on No Yes Yes
IP security Acceptable Excellent Excellent
Power consumption Medium Low Low

FPGA Fundamentals: Logic Elements
LUT based vs. MUX based
Maxfield, Clive
Elsevier

FPGA Fundamentals: Logic Elements
Actel's Flash MUX based Logic Module
a

a a
0
a 1
a

Data a Y
X3 pin 1
a 0
pin 4 a 0 F2
a a a a 1 1

a a a
a YL
a
0
Clk 1
X2 a
pin 3

a a
a
a a a

Set/Reset/Enable
X1

pin 2 a a
Clr
a
XC a
pin 5 a
a
a a

Combinatorial Sequential
Any 3 Input D Flip-Flop With Enable
Function and Set or Reset
(3 input LUT D Q
Equivalent) Enable
A CLK
B Q
C Set or Reset

FPGA Fundamentals: An Example
Control Store 110101011101010010001

FPGA Fundamentals: Complex Architecture
A Plethora of IPs...

Fundamentals of Mixed-Signal
FPGAs
Actel Fusion® FPGA

Mixed-Signal FPGAs: Analog vs. Digital
Analog Signal
Digital Signal

Quanta

Pendulum Tracking

Pendulum Tracking-2 Quanta-

Pendulum Tracking-5 Quanta-

Mixed-Signal FPGAs: Analog-to-Digital (A/D)

Sampling and Quantization

System Monitoring

Separate Analog and Digital

Microcontrollers

Mixed-Signal FPGAs: All in one

Actel’s Fusion Mixed-Signal FPGA
Typical System
System Memory Cache Memory NV Storage

DRAM SRAM FLASH
MPU / MCU FPGA / ASIC
Analog Power Clock Discrete

Interface Mgmt Mgmt Analog

Actel’s Fusion Mixed-Signal FPGA
Flash based
Up to 30 analog inputs
ADC (12 bits, 600 ksps)
Up to 1.5M system gates
Advanced I/O support
SRAM / FIFO blocks
Embedded Flash Memory
… and much more…

Fusion Architecture
Fusion starts with ProASIC3…

Fusion Architecture
And adds Flash Memory Blocks and Analog Peripherals…

Fusion PSC: Target Applications
Power and Temperature Management
Power sequencing with tracking control
Smart battery charging
Voltage, current, temperature monitors and alarms
Fan and heat-element control and monitoring
Intelligent Platform Management Interface (IPMI)
Motor and Motion Control
Motor control – stepper, 3-phase and solenoid control
Anti-lock brakes
System initialization and configuration
Context save and restore
Context switching
System boot codes
Storage
Program code storage
EEPROM emulation
Data acquisition and logging
Low Power and Clocking
Control for sleep mode and wake-up
Live at power-up clock generation, conditioning, and distribution

Fusion Family
Part # AFS090 AFS250 AFS600 AFS1500
ARM enabled - - M7AFS600 -
Cortex M1 enabled - M1AFS250 M1AFS600 M1AFS1500
System Gates 90K 250K 600K 1,500K
General
Tiles (D-FF) 2,304 6,144 13,824 38,400

Secure (AES) ISP Yes Yes Yes Yes
PLLs 1 1 2 2
Globals 18 18 18 18
RAM blocks (512x9) 6 8 24 60
Total RAM 27 Kbits 36 Kbits 108 Kbits 270 Kbits
Memory
FlashROM bits 1Kbits 1Kbits 1Kbits 1Kbits

Flash Memory Blocks
1 1 2 4
Total Flash Memory 2 Mbits 2 Mbits 4 Mbits 8 Mbits
Analog Quads 5 6 10 10
Analog
Analog Inputs 15 18 30 30
Output Gate Drivers 5 6 10 10
I/O Types Analog / LVDS / Std+ Analog / LVDS / Std+ Analog / LVDS / Pro Analog / LVDS / Pro
I/O Banks (+ JTAG) 4 4 5 5
I/O
Max Digital I/O 75 114 172 252

Analog I/O 20 24 40 40
QN108 37/9 (16)
Double ended
I/O: Single /
QN180 60/16 (20) 65/15 (24)

(analog)
PQ208 93/26 (24) 95/46 (40)

FG256 75/22 (20) 114/37 (24) 119/58 (40) 119/58 (40)
FG484 172/86 (40) 228/86 (40)
FG676 252/126 (40)

Analog System Builder
Creates Complete Analog System Including
AB Hard-Macro
Analog System Soft-IPs (RTL)
Analog System data storage RAMs
Memory files for simulation
Configuration file for import into NVM System

Analog System Builder: Supported Peripherals
Voltage Monitor
Current Monitor
Differential Voltage Monitor
Temperature Monitor
Direct Digital Input
Output Gate Driver
Internal Temperature Monitor
Internal Voltage Monitor
RTC (Real Time Counter)

Analog System Builder GUI
Enter system ADC clock rate Specify ADC resolution Choose Advanced Options
clock rate
Sampling rate for

channel
Assign pins for
analog channels
Select peripherals Define ADC sampling
sequence

To Configure a Voltage Monitor

To Configure Differential Voltage Monitor

To Configure Current Monitor

To Configure Gate Driver Outputs

A Simple Example

A Simple Example
Displaying Flags for Different Voltage Thresholds

A Simple Example
Creating a Libero Project

A Simple Example
Use SmartDesign to Connect Various Analog & Digital
Blocks on a Virtual Canvas

A Simple Example
Within SmartDesign, use the Analog System Builder to
Create the Voltage Monitor – Max from Potentiometer=3.3V

A Simple Example
Assigning to a Voltage Channel (ex. AC4)

A Simple Example
Synthesis -> P&R -> Programming

Fusion Peripherals
Clocking
RC and Crystal Oscillators
Clock Conditioning Circuitry
No-Glitch MUX
Embedded Memory
Analog Block

Fusion Clock Resources
Fusion Provides Multiple Clocking
Resources:
On chip clock sources:
GPIO RC oscillator @ 100MHz
Crystal Oscillator Circuit
Six CCC Blocks / PLLs (1 or 2)
MOSFET No-Glitch MUX
Outputs A3P FPGA Real Time Counter (RTC)
Fabric
Use Models
Mux
Ana
Analog A/D (incl. SRAM,

Inputs
CCC/PLL, IO) Internal 100MHz RC oscillator
Crystal OSC circuit
32 KHz – 20 MHz
CCC/PLLs can multiply, divide, and
Xtal OSC, phase shift clock signals for user
FLASH
RC OSC, applications
Memory
RTC, Vreg
Sources include: crystal Osc, RC
Osc, or external clock
JTAG Port RTC enables low power sleep mode

Fusion Clock Resources
System Block Diagram
100 MHz RC clock

GND_OSC generator
VCC_OSC
Clock out
to FPGA core
C R
Crystal Oscillator GLA

C
C No- To core
Xtal Clock PLL/ Glitch
External CCC Mux
Or External Clock IOs GLC CLKOUT
Crystal RC
From FPGA Core
GLINT

RC & Crystal Oscillators

Fusion RC Oscillator
Features
Summary
Clock frequency: 100 MHz
+/-1%: 0 to 70 C
Block Diagram
Duty cycle 40% – 60%
Requires no external
components VCC_OSC 100 MHz RC 100MHz
Clock Generator CLK_OUT
Can be used to drive either a GND_OSC
CCC with
PLL or Output Pad RCOSC IP Macro PLL
EN
Provides an integrated,
accurate on-chip clock source Trim <27:0>
Additional Features
Factory trim capability for high
precision
Note*: Crystal oscillator and RC oscillator physically

share the same VCC and GND power pads.

Fusion Crystal Oscillator
Features
High-precision Clock Source MODE0
From PLL tile
Up to 100ppm (0.01%) precision

MODE0_RTC
Supports Both On-chip and Off-
chip Resources MODE1
VCC_OSC
Source for PLL/CCC
MODE1_RTC
Modes
Crystal
External Crystal: GND_OSC EN
High gain: 2 – 20 MHz Oscillator
Med gain: 0.2 – 2 MHz Circuit EN_RTC
Low gain: 32 – 200 KHz XTLOSC IP Macro
RC Network: 32kHz – 4MHz XTAL1
Specifications
Maximum output jitter – 50pS From RTC
RMS External XTAL2
Crystal
10 MHz crystal (0.05%) TO CCC/PLL
CLKOUT0
Duty cycle: 40% - 60% TO RTC
(3.3v)
CLKOUT1
Note: Crystal oscillator and RC oscillator physically

shared the same VCC and GND power pads.

Fusion
Clock Conditioning Circuitry (CCC)
All Devices Have 6 Clock Conditioning Circuitry (CCC)

Blocks, BUT …
… Some CCC Blocks do not contain PLLs
AFS090 / AFS250 – 1 PLL
AFS 600 / AFS1500 – 2 PLLs
… Non-PLL Functionality Still Available
Divider and Delay Elements
Global Access from I/O or Internal Signal
3 Global MUX Blocks
Steer Signals from Global Pads and FPGA Fabric into Global
Networks

Fusion PLL
Functions
Clock Phase Adjustment
Clock Delay Minimization
Clock Frequency Synthesis
Allows Access From Global Pads To Global Network and PLL
Allows Access From PLL To FPGA Core
Input Sources:
Single Ended I/O, Differential I/O, FPGA Core, RC Osc, XTAL Osc
Reference
Clock Output
Phase Low-Pass Clock
VCO
Feedback Detector Filter
Clock

Fusion PLL
Features
Delay Blocks (6 Programmable and 1 Fixed)
Programmable Delay/Advance up to 5.56 ns in 160 ps
increments for Clock Skew Minimization
5 Frequency Divider Blocks
Provide Frequency Multiplication/Division
Clock Phase Adjustment
0°, 90°, 180°, and 270°
Dynamic Shift Register
Provides Dynamic Reconfiguration Capability

Fusion PLL
Block Diagram
Fixed delay
Divider available in bypass mode

No-Glitch MUX (NGMUX)

Fusion No-Glitch MUX (NGMUX)
Provides Special Switching Sequence
Between Two Asynchronous Clock Domains
User-configurable to select between 2 of 3
possible clock sources – GLA, GLC, or other
internal signal
Time-out circuitry included in case one of the
clocks stops or runs at very low frequency
GLA
Advantage No- To core
PLL/
Eliminates narrow pulses/glitches which can CCC
Glitch
Mux
cause clocking errors GLC CLKOUT
Especially critical in hi-rel apps
Uses
Clock domain control GLINT
SEL
Power reduction by transitioning to lower
frequency

Fusion No-Glitch MUX Usage
NGMUX is Implemented as a 2:1 Mux in the Software
Instantiate NGMUX in VHDL or Verilog Description
NGMUX Macro
Signal Name Direction Function

CLK0 CLK0 Input Clock Input
CLK1 Input Clock Input
GL
CLK1 Mux Select
S S Input 0 -> 1 CLK1
1 -> 0 CLK0
CLKOUT Output Clock Output

Fusion No-Glitch MUX
Operation
Switching from CLK0 to CLK1:

GL will drive one last complete CLK0 positive pulse (i.e. one rising
edge followed by one falling edge).
From that point GL stays low until the second rising edge of CLK1
occurs.
At the second CLK1 rising edge, GL will continuously deliver CLK1
signals.

Fusion: Global Distribution Network
Quadrant Global Rib Left and Right CCCs

Provide 6 Chip-wide
3
3 3 3 3 3 Global Networks
Quadrant Global Spine
9
(Access from I/Os in
Middle of Left and
Right Sides)
Central Global Rib 12 Quadrant Global
Networks (3 per
6 6 6
3
6 Quadrant – Access
from I/Os in 4
3
6 6 6 6 Corners)
Global Spine
Each VersaTile Has

Access to 9 Global
Resources
Access from PLLs
33 3 3 3
and Internal Signals
3
PLL/CCC
PLL/CCC

Fusion Peripherals
Clocking
Embedded Memory
Flash Memory Block
FlashROM
SRAM and FIFO
Analog Block

Fusion
Only FPGA with Flash Memory

Fusion Flash Features
Flash Memory 2 Mb Density
1 – 4 blocks/device
Each 2 Mb array has independent
GPIO controller
Independent JTAG access
Flexible Operation
MOSFET
Outputs A3P FPGA
x8, x16, and/or x32 FPGA
Fabric Each supports multiple partitions
Mux
Ana
Analog
Inputs
A/D (incl. SRAM, Small page size (1kb)
CCC/PLL, IO)
Can be accessed by either on-chip
or off chip resources
High Performance
FLASH
Xtal OSC, 60 ns random access
RC OSC,
Memory
RTC, Vreg
Pipelined 10 ns access of
sequential memory addresses
JTAG Port

Fusion Flash Features (cont.)
Flash Memory Level:
FPGA access
Password security
GPIO JTAG access for programming
Page Level:
MOSFET JTAG read / write protection
Outputs A3P FPGA
Fabric
Program/erase
Mux
Ana
Analog A/D (incl. SRAM, Partition on page boundaries

Inputs
Block Level Error Detect:
CCC/PLL, IO)
Single error correct

Double error detect
Xtal OSC,
FLASH
RC OSC,
Memory
RTC, Vreg
JTAG Port

Fusion Peripherals
Clocking
Embedded Memory
Flash Memory Block
FlashROM
SRAM and FIFO
Analog Block

FlashROM (FROM) Memory
8 pages of 128 bits (8x128)
Same as ProASIC3\E FROM
FPGA Core and FlashROM Memory Can Be Programmed
Separately
Allows Changing FROM without Erasing Core
Core Powered Down during FROM Programming
Example Applications
IP Addressing
User/System Preference Storage
Device Serialization
Inventory Control
Subscription Models (Set-top Boxes)
Secure Key Storage
Presets
Date Stamping
Version Management

FlashROM
Logical View
Programming Control and JTAG Interface
Core Access
Prog. Access 128 Bit Data
3-bit Page 3-bit Page

Address Address from
Program Control
Logic
7-bit Address
from FPGA
8-bit data
Core
4-bit Word
Address
8-bit Data
To FPGA Core
Every 128-bit Page Can Be Reprogrammed Independently

Fusion Peripherals
Clocking
Embedded Memory
Flash Memory Block
FlashROM
SRAM and FIFO
Analog Block

Dual-Port SRAM Blocks
Multiple 4K bit Embedded Memory Blocks:
2 Write/Read ports OR independent 2-port
Synchronous operation up to 250 MHz
Fully programmable
Scalable aspect ratio from 256x18 to 4Kx1 DIN DOUT
ADDR
Cascadable - wide and deep BLKEN
PORT A
WR_RDN
SmartGen tool automates memory generation CLK
WIDTH
FIFO Capability 4k bit
SRAM
Decoder, FIFO control and flag logic built into RAM DIN Block DOUT
block ADDR
BLKEN
Programmable FIFO depth and flag threshold WR_RDN
CLK
PORT B
WIDTH

Fusion SRAM Implementation
True Dual-port RAM:
Variable Aspect Ratios – 4096x1, 2048x2, 1024x4 or 512x9
Independent Read and Write Port Widths
Dual-port Options – Both Read, Both Write, One Read & One
Write; Same Clock Frequency or Two Different Clock Frequencies
Pass-through of Write Data or Hold Old Data on Output
Two-port RAM:
Variable Aspect Ratios – 512x9 or 256x18
Independent Read and Write Widths
Dedicated Read and Write Ports
Both Macros Have
Synchronous Write
Synchronous Read – Pipelined or Non-Pipelined
Asynchronous Output Reset

Fusion RAM
FIFO
Fusion Has One FIFO Macro:
Variable Aspect Ratios – 4096x1, 2048x2, 1024x4, 512x9, or
256X18
Independent Read and Write Port Widths
Four FIFO Flags – Empty, Full, Almost-empty, Almost-full
FIFO Empty/Full Flags Synchronized to Read Clock and Write Clock,
Respectively
Programmable Threshold Values of ‘Almost’ Flags
Asynchronous Reset
Active-low Block Enable
Active-low Write Enable and Active-high Read Enable
FSTOP and ESTOP – FIFO Counters Can Count after FIFO Is Full
or Empty
Allows Writing to FIFO Once and Repeatedly Reading Same Contents
without Rewriting Contents

Fusion Peripherals
Clocking
Embedded Memory
Flash Memory Block
FlashROM
SRAM and FIFO
Analog Block

Fusion Analog Block
1.5V Voltage regulator
-3.3V Voltage converter (for internal use
only)
Bandgap voltage reference
Power System Monitor (Generates
Flash and ADC Reference)
Real Time Counter System (RTC)
Analog Quad (up to 10 Analog Quads)
Voltage monitor block
Current Monitor block
Temperature monitor block
Gate control/driver block
Analog MUX
ADC
Selectable 8/10/12 bit resolution
32 input channels
Up to 600K samples per second

Analog Quad (AQ)
Analog Quad is the Basic Analog I/O Structure

Fusion Analog Quad
Features
Includes 4 analog interface pins
AV pin – Input: direct and prescaler voltage monitor
AC pin – Input: direct and prescaler voltage monitor, current monitor
AT pin – Input: direct and prescaler voltage monitor, temp monitor
AG pin – Output Power FET gate control or high voltage, high drive output
Input voltage range for AV and AC pads: - 10.5V to 0 V or 0V to 12V
+/- 10%
Input voltage range for AT pad: 0V to 16V +/- 10%
AV, AC, AT pads can be used as low speed digital inputs
(Tr, Tf > 20nS)
Modular building block used on all Fusion family members
AFS090: 5 Quads
AFS250: 6 Quads
AFS600, AFS1500: 10 Quads

Analog Quad: Direct Input
Analog Quad
AV AC AG AT
Pads Gate Driver
Voltage Monitor Current Monitor Temperature
On chip
Block Block Monitor Block
Pre- Pre- Pre-

Scaler Scaler Scaler
Power
MOSFET
Digital Digital Gate Driver Digital
Input Input Input
Current
Temp.
Monitor/Inst.
Monitor
Amplifier
From
To FPGA To FPGA FPGA To FPGA
To Analog Mux To Analog Mux To Analog Mux
Direct Input used when Maximum Input Voltage is between 2V and VREF

Analog Quad: Direct Input
AV, AC, and AT pads can be Routed Directly to the Analog Mux by
Configuring the Analog Quad
Features
Best accuracy, lowest offset
No Buffers or Amplifiers between Input pin and ADC
No DC input current; capacitive load only (~20pF)
Resistive connection to ADC: ~4k ohm
One Input range: 0V to ADC reference level
Full scale level for internal reference is 2.56V
Decimal value of 8 most significant bits is input level in ‘centiVolts’
( i.e., ADC count of 207 = 2.07V at input)
Equivalent function to micro-controller style ADC
Limitations
Positive input only
Single range
Needs low impedance input source for full bandwidth
Input capacitance varies greatly as input selection MUX is changed and
Sample/Hold cycles

Analog Quad: Pre-scaler Input
Analog Quad
AV AC AG AT
Pads Gate Driver
On chip
Pre- Pre- Pre-

Power
MOSFET
Input Input Input
Current
Temp.
Monitor/Inst.
Monitor
Amplifier
From
Pre-scaler Input used when Input Voltage is not between 2V and VREF

Analog Quad: Pre-scaler Input
Features
Input voltage ranges for AV and AC pads
Pre-Scaler input from -10.5V to 0V or 0V to 12V
Full scale ranges for ADC: ±16V, ±8V, ± 4V, ± 2V, ± 1V, ± 0.5V, ± 0.25V and ±0.125V
Input voltage ranges for AT pads
Pre-Scaler input from 0V to 16V
Full scale ranges for ADC: +16V and +4V
All ranges indicate input level in mV with a simple left or right shift of the
binary value
On 4V range with 12 bit ADC setting, LSB = 1mV at input pin
Constant input impedance; ~1M ohm, 5pF
Limitations
Pre-scale circuits add offset and gain error
Dynamic range changes are discouraged (will cause transient measurement
errors on all channels)

Pre-Scaling
Overdriving the ADC Input Can Result in:
Erroneous Conversions
Input Latch Up
Permanent Damage To Device Is Possible
To Avoid Overdriving, The Input Can Be Pre-scaled To
Ensure Maximum Voltage To ADC Does Not Exceed VREF
“Scale Down” Voltages That Are Greater Than VREF
“Scale Up” Voltages That Are Less Than VREF
Invert If Input Voltage Is Negative
VCC VREF
Analog to N
VIN Pre-scaler Digital
Converter

Pre-Scaling (Cont.)
Pre-scaler Value (Gain) is Chosen to Ensure (Max VIN * G)
≤ VREF
Gain May Be Chosen Such That the LSB of the Converter
Output is a Convenient Number
Example:
For VREF = 2.56V and VIN = 6V, G = 0.4267 Ensures Input to ADC ≤ VREF
But . . .
LSB of ADC equals the following:
8 bit: 23.44 mV
10 bit: 5.86 mV
12 bit: 1.47 mV
Using A Different Gain Value Can Result In Simpler Calculations
Limitations
Pre-scale Circuits Add Offset and Gain Error

Analog Quad: Pre-scaling Factors
LSB 8-bit LSB 10-bit LSB 12-bit
Full Scale Voltage conversion conversion conversion
VIN Scaling Factor (G) (VREF / G) (mV) (mV) (mV) Range Name
12V ≥ VIN > 8V 0.15625 16.368 V 64 16 4 16V
8V ≥ VIN > 4V 0.3125 8.184 V 32 8 2 8V
4V ≥ VIN > 2V 0.625 4.092 V 16 4 1 4V
2V ≥ VIN > 1V 1.25 2.046 V 8 2 0.5 2V
1V ≥ VIN > 0.5V 2.5 1.023 V 4 1 0.25 1V
0.5V ≥ VIN > 0.25V 5.0 0.5115 V 2 0.5 0.125 0.5V
0.25V ≥ VIN > 0.125V 10.0 0.25575 V 1 0.25 0.0625 0.25V
VIN ≤ 0.125V 20.0 0.127875 V 0.5 0.125 0.03125 0.125V
Fusion Scaling Factors Give Convenient LSB Values For All ADC Resolutions
All Ranges Indicate Input Level in mV with Simple Left or Right Shift of Binary Value
Maximum Allowable Input Voltage:
-10.5V or +12V for AV and AC pads
+16V for AT pad
Pre-scaling Offset and Gain Error
Gain error
Positive DC inputs: 1% typ
Negative DC inputs: 2% typ
Offset error
2 ± 0.2% of range

Analog Quad: Pre-scaler Input Examples
Example 1
8V Is Applied to AV Pad
Scaling Factor Is Set to 0.3125
Output of Pre-scaler (Input to ADC) is (8 * 0.3125) = 2.5V
For 12-bit Resolution, ADC output = 212 * (2.5 / 2.56) = 4000
LSB = (2.56 / 0.3125) / 212 = 2 mV
Example 2
12V Is Applied to AV Pad
Scaling Factor Is Set to 0.15626
Output of Pre-scaler (Input to ADC) is (12 * 0.15625) = 1.875V
LSB = (2.56 / 0.15626) / 212 = 4 mV
Example 3
–0.2V Is Applied to AV Pad
Scaling Factor Is Set to 10
Output of Pre-scaler (Input to ADC) is (0.2 * 10) = 2.0V
Input signal is inverted to make ADC input positive
LSB = (2.56 / 10) / 212 = 0.0625 mV

Analog Quad: Current Monitor

Analog Quad: Current Monitor
Can sense Current by Measuring Voltage Drop Across an External
Resistor
10V 0.1Ohm 1A
10V 9.9V
AV AC
10x 1V
To ADC
If the Polarity bit is set to ‘0’ (positive):

Current monitor output will be = 10 * (AV-AC)
If the Polarity bit is set to ‘1’ (negative):
Current monitor output will be = 10 * (mag(AV)-mag(AC))
Note: ADC input should be positive only

Analog Quad: Temperature Monitor

Analog Quad: Temperature Monitor
Can Monitor Temperature of External Transistor Connected as Diode
Basic accuracy of 5 degrees C
Output count of ADC reads directly as absolute temperature (K)
Example: @ room temperature (25°C = 298.15°K):

Diode equation –
V = (KT/q) * ln(I1/I2)
Where I1/I2 is 10 and K/q is 86.258x10-6
V = 59.2mV
After gain of 12.5 voltage to ADC will be = 59.2mV * 12.5 = 740mV

Analog Quad: Direct Digital Input

Analog Quad: Direct Digital Input
AV, AC, and AT pads can be used as low speed Digital
Inputs (LVTTL)
Operating speed – 10MHz (Max)
(Tr, Tf > 20nS)
Delay – 10nS (Typ)
The Digital Buffers can be Disabled if not used

Analog Quad: Gate Driver
Power
Line Side
Analog Quad
Supply Load Side
Off chip Rpullup
AV AC AG AT
Pads Gate Driver
On chip
Pre- Pre- Pre-

Power
MOSFET
Input Input Input
Current
Temp.
Monitor/Inst.
Monitor
Amplifier
From

Features
Controls turn on of external Power FET by pulling the gate towards
ground
FET Vgs limited to Ig * Rpullup
Slew rate of load controlled by Ig/Cgd = dV/dt
Works for positive supplies (with P-FET) and negative
supplies (with N-FET)
High drive mode can sink/source 25mA
Limitations
Requires external pullup resistor
Open drain style output. Does not output a voltage level

Gate Driver has two Modes:
High current drive - 25mA @ 1V
Low current drive – choose between 1, 3, 10 and 30uA

Fusion Analog MUX
Input to the Fusion ADC is a 32:1
Analog MUX
30 Input Channels are User Definable
Connected to Analog Quad AV. AC and
AT inputs
Two Channels are Hardwired Internally
Channel 0 is wired to the FPGA’s 1.5 V
supply
Fusion device can monitor its own
power supply
Channel 31 connects to an internal
temperature diode
Monitor temperature of the Fusion
device
Analog Block Input CHNUMBER[4:0]
Selects Channel for Conversion

Fusion ADC
8/10/12 bit Selectable Resolution
32 Input Channels
Up to 600K samples/sec
TUE (Total Unadjusted Error)
+/- 2 LSB in 8 bit mode
Clock
ADC interface clock max frequency – 100MHz
Selectable clock divider (divide by 4 to 1024) to generate ADC internal clock
ADC internal clock frequency range – 1 – 10MHz
Sample and Hold
Selectable sample time 2 – 257 * ADC internal clock period
Self Calibration
Automatic full calibration on powerup
Optional incremental calibration after each conversion
Status Signals:
Conversion in progress
Sampling in progress
Calibration in progress
Data valid
Power Requirements
3.3V for Analog, 1.5V for Digital, and reference voltage (2.56V to 3.3V)
Analog Block Summary
Up to 10 Analog Quads per Device
Pre-scaler input range:
-10.5 V to 0V or 0V to 12V for AV and AC inputs
0 to 16V for AT input
Voltage Monitor
Current Monitor
Temperature Monitor
Gate Driver – For controlling Power MOSFETs
32 Input Channel ADC with Selectable Resolution (8/10/12
bit)
Selectable Internal/External Voltage Reference
1.5V Voltage Regulator
Real Time Counter (RTC)

Fusion: I/O Overview
Fusion I/Os Are Organized in Banks Supporting Multiple
Standards
1.5 V, 1.8 V, 2.5 V and 3.3 V
Common I/O Features
Programmable Slew Rate
Programmable Drive Strength
Weak Pull-up / Pull-down
I/Os Power Up in Known State
No special power up sequencing is required

Fusion: I/O Functions
Regular I/Os
Input, Output, Tristate and Bidirectional Buffers
Registered I/Os
Built-in Input, Output and Output-Enable Registers
Each Register Equivalent to 1-tile Core Flip-flop
DDR I/Os
Built-in Input and Output DDR Registers

Fusion I/O Bank Types
Hot Swap Bank
Support for Single-ended I/O Standards
LVTTL, LVCMOS
Hot Swappable
3 Drive Strengths, Weak Pull-up / Pull-down Circuits
DDR Transmit / Receive
LVDS Bank
Support for Single-ended and Differential I/O Standards
Single-ended
LVTTL, LVCMOS
PCI, PCI-X
Differential
High-Speed 700Mb/s LVDS with External Resistors
LVPECL I/O
2 Programmable Slew Rates, 6 Drive Strengths, Weak Pull-up / Pull-down
Circuits
No Hot-swap Capability

Fusion I/O Bank Types (cont.)
Pro I/O Bank
LVDS Bank I/O Standards Support PLUS …
… Voltage-Referenced I/O Standards
HSTL1
SSTL2/3
GTL+
2 Programmable Slew Rates, 6 Drive Strengths, Weak Pull-up / Pull-
down Circuits
Hot-Swappable
Analog I/O Bank
Analog Quad I/O Structure
Can be used for low speed digital input signals

Fusion I/O: I/O Bank Type Summary

Fusion: I/O Banks per Device
AFS090 / AFS250
Four I/O Banks:
1 Hot-swap Bank - North side of chip
2 LVDS Banks – East, West sides
1 Analog Bank – South side
AFS600 / AFS1500
Five I/O Banks:
2 Pro I/O Banks - North side of chip
2 LVDS Banks – East, West sides
1 Analog Bank – South side

LVDS / Pro I/O Banks: Output Drive and Slew Rate
LVDS Bank
Pro I/O Bank

Fusion: I/O Banks and User I/O Counts
Part # AFS090 AFS250 AFS600 AFS1500

I/O Types Analog / LVDS / Std+ Analog / LVDS / Std+ Analog / LVDS / Pro Analog / LVDS / Pro
I/O Banks (+ JTAG) 4 4 5 5
I/O
Max Digital I/O 73 114 172 278

Analog I/O 20 24 40 40
QN108 36/14
I/O: digital /
QN180 48/20 62/24

analog
PQ208 93/24 95/40

FG256 73/20 114/24 119/40 119/40
FG484 172/40 228/40
FG676 278/40

Agenda
Fusion Overview
Fusion Architecture
Fusion Design Flow
Development Support

Fusion Design Flow
Fusion Smart Backbone
Libero Flow
SmartGen
Simulation
Programming and Security

Actel Fusion Silicon: Physical View
FPGA Fabric
System Application
Optional MCU
(ARM or 8051)
Fusion Fusion Fusion
Smart Smart Smart
Applet 1 Applet 2 Applet 3 Peripheral in
FPGA Fabric
Control
Flash Memory Analog Smart Analog Smart Analog Smart

Peripheral Peripheral 1 Peripheral 2 Peripheral n

The Fusion Backbone
Analog System NVM System
Builder A3P SEQUENCE CONTROL
Interface
STATE Builder
INIT SAVE
Clients Clients Power-up
FLAGS USER_DATA Initialization
Interface
Flag Transition State Machine
FPGA State Machine
Fabric NVM Access
Control & Interfaces
SMTR MEM
Your
FPGA LPF / Threshold INIT
Evaluation SMEV MEM
Functions CONFIG
Engine 1.5V to
ASSC MEM FPGA and NVM
Backbone 3.3V
Time-Slot based Analog Test Register
NVM System Sample Sequence PTBASE
State Machine GND ADC

ACM
NVM
Analog System PTEM
VDD15A
This gets repeated 5 times (for the 10 quad configuration)
GNDA[1]
PCAP
Embedded Band Gap,

Supply filter 1.5V
Blocks NCAP
-3.3V Charge
Pump
Analog Quad Analog Quad and Power
System
Voltage
Regulator
VDD33[ 1]
Monitor
VDD33[ 0] PUB
Fusion Device To
ADC
Ch0 ATESTIN
Probe
GNDREF
Pad
BGOUT
GNDAQ
VDDN33 GNDA[0] GNDAQ[0] AV[0] AC[0] AG[0] AT[ 0] ATRTN[4 :0] AT[9:1] AG[9:1] AC[9: 1] AV[9:1] GNDAQ[1] AVDD ADCGNDREF VAREF

System Overview
Soft IP Role in System
“Glue” That Binds System Components Together
Main Control for Analog System
Sampling
Digital low-pass filtering
Threshold comparisons
State filtering
GPI/GPO
Makes microcontroller dependency unnecessary (self-sustained)
Soft IP Configuration
All configuration within the Analog I/F Soft IP is controlled via setting top-
level Generics/Parameters and propagating these values through hierarchy
Allow user read access to RAMs, RAM address space size, enable DLPF, control
Current/Temperature monitoring functions, Declare number of GPI/GPO signals,
etc.

System Overview
Hard/Soft IP Blocks

System Overview
NVM
Non-Volatile Memory (NVM)
Clock
11 Generation
9 ADC Extern al C lock
System configuration storage

This clock signal i s
Crystal Oscil lator PLL Cl ock
distributed to all
Analog . components in this
Inputs Analog SAR
from
. Mux ADC diagram
RC Oscill ator
Quads .
uS
5
mS
Including Analog system

S
Interval Gen
User
Read
Access
1
ADCSample
Sequence Controller
6
512x9
Dual-Port RAM
configuration parameters User

2
System Monitor
512x9
7
4
Init/Config
10
Read Evaluation Phase NVM JTAG

Dual-Port RAM(s) RAM Initializer
Access State Machine
User-define storage User

Read
3
System Monitor
Transition Phase
512x9
8
Dual-Port RAM(s)
On-chip/off-chip microcontroller(s) General-Purpose

Digital Inputs
General-Purpose
Digital Outputs
User data storage

10
etc.
NVM
Soft IP
Hard IP

System Overview
Init/Config Block
Init/Config Soft IP Block
Clock
11

9 ADC Extern al C lock
Generation
distributed to all
Analog . components in this
Inputs Analog SAR
from
. Mux ADC diagram
RC Oscill ator
Quads .
uS
5
mS
Reads configuration information from NVM

S
Interval Gen
1 6
User
ADCSample 512x9
Read Sequence Controller Dual-Port RAM
Access
Initializes (writes) all “clients”

2 4 10
7
User System Monitor
512x9 Init/Config
Read Evaluation Phase NVM JTAG
Dual-Port RAM(s) RAM Initializer
Analog Quads, analog I/F soft IP, user IP

8

User System Monitor
512x9
Read Transition Phase
Dual-Port RAM(s)
General-Purpose General-Purpose
Digital Inputs Digital Outputs
When init/config is done, the

analog I/F soft IP commences operation 4
Init/Config
RAM Initializer
Soft IP
Hard IP

System Overview
Dual-Port RAM Blocks
Clock
11 Generation
9
512x9 Dual-port RAM Blocks

ADC Extern al C lock

distributed to all
.

Analog
components in this
Inputs Analog SAR
from
. Mux ADC diagram
RC Oscill ator
Quads .
uS
5
mS
S
Interval Gen
Heart of Analog I/F system User

Read
Access
1
ADCSample
Sequence Controller
6
512x9
Dual-Port RAM
Initialized by Init/Config 512x9 User

Read
Access
2
System Monitor
Evaluation Phase
State Machine
512x9
7
Dual-Port RAM(s)
4
Init/Config
RAM Initializer
10
NVM JTAG
ASSC block Configuration Dual-Port RAM(s)

User
Read
Access
3
System Monitor
Transition Phase
State Machine
512x9
8
Dual-Port RAM(s)
Parameter storage
General-Purpose General-Purpose
Digital Inputs Digital Outputs
ADC sample storage for

each analog channel Soft IP
Digitally low-pass filtered ADC sample storage Hard IP
Application sequence storage for SMEV and SMTR blocks
Threshold comparison results for SMEV block

System Overview
ASSC Soft IP Block
ADC Sample
Sequence Controller (ASSC)
Controls ADC
Calibration
Power-down
Sampling
8/10/12-bit Resolution
Detects Saturation of Channels
Digital post-scaling of ADC Samples
Controls Current Monitor and Temperature Monitor Strobes
RAM Stores Sequence Information for ASSC

Sampling Sequence Specification
Why do we need to Sequence the Samples???
32 analog signals; 1 ADC
TDM Sequencing
64 Time Slots
More time slots for a Channel; more ADC Mindshare; Higher Throughput
Each channel Added to Analog System Gets Added to Sequencer
Automatically
Sequence can be Optionally Modified for More/Less Samples
Out of Sequence Jumps for Special Sampling During Runtime
One time jump; return to regular operating sequence
No automatic sequence, manual jump requests only
Main Operating Sequence
Automatically computed based on target rate
Manual specification for customized applications

Main Feature Description
ASSC Time Slots
Programmable Sequencer
Time
0 1 2 3 4 5 6 7 8 9 10 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Seq (Timeslot) #
1 2 1 3 1 4 1 2 1 3 1 2 1 3 1 4 R C S PD Channel / Function
Reset to Seq 0 after Sampling Channel 4 Power Down

Stop
- 64 Possible Sample slots
Calibrate
- Variable sample rates
- Power down Reset to Seq 0
- Timed sampling
- Automatic or external triggering
- External controlled ‘jump to Seq #’

System Overview
SMEV Soft IP Block
System Monitor Evaluation Phase
State Machine
Compares ADC Samples with
user-defined Thresholds
Simple 12-bit, Unsigned Arithmetic
Operations
A[11:0], B[11:0]
Digital Low-Pass Filtering of ADC Samples
Average ADC sampled data
Requires only current ADC sample and
previous averaged data
State Filtering (Digital Correlation)
Look for 0->1 or 1->0 Transitions
RAM Stores Application Sequences for
SMEV
Sequences controlled by Op-codes

Digital Low Pass Filtering
12 11.1
N=2 9.86
10.4
10.8
9.15
8.20
6.94
5.25
0
3
Step Response
T = 4 Samples
12
N=2 3 Full charge/Discharge
2.25 At 5*T = 20 samples
1.68
1.26 0.95 0.71
0
Impulse Response
Equation: Xn <= Xn-1 – (Xn-1/2N) + (In/2N); where N = LPF factor

Digital Low Pass Filtering (cont.)

Digital Filtering - Step Response
N= 2 4
In = 12 12
Initial Value = 0 0
Digital Filtering, N= 2 and N = 4
Xo 3.000 0.750
X1 5.250 1.453 14.000
X2 6.938 2.112
12.000
X3 8.203 2.730
X4 9.152 3.310 10.000
X5 9.864 3.853
X6 10.398 4.362 OUtput Voltage 8.000
Series1
X7 10.799 4.839 Series2
6.000
X8 11.099 5.287
X9 11.324 5.706 4.000
X10 11.493 6.100
X11 11.620 6.469 2.000
X12 11.715 6.814

0.000
X13 11.786 7.138 1 3 5 7 9 11 13 15 17 19 21 23 25 27
X14 11.840 7.442 Samples
X15 11.880 7.727

State Filtering
12 11.1
N=2 Over_8v 9.86
10.4
10.8
9.15
8.20
6.94 Assert==3
5.25
0
3
Step Response
T = 4 Samples
12
N=2 3 Full charge/Discharge
2.25 At 5*T = 20 samples
1.68
1.26 0.95 0.71
0
Impulse Response

System Overview
SMTR Soft IP Block
System Monitor Transition
Phase State Machine
User-defined Digital Inputs and
Digital Outputs (flags)
Boolean Operations on Digital Inputs
and Internal Temporary Registers
Branching Operations (if-then-else conditional
jumps, looping)
“Microcontroller-like”
Reads and Processes SMEV Comparisons
RAM Stores Application Sequences for SMTR
Sequences Controlled by Op-codes

Data Processing Order
Acquire Analog Signal
Convert to Digital Data
Average the Resulting Data to Smooth the Samples
Compare the Result With the Threshold to Detect Overflow
or Underflow
Wait for Multiple Compare Results to Remove Glitches
Raise the Over/Under Flow Flag

Main Feature Description
Analog I/F Operation Flow
ASSC -> SMEV -> SMTR
Pipelined, TDM operation: ADC samples first, Evaluation of samples second,
Transition decisions based on Evaluation third, repeat …
ASSC ch1 ch2 ch3 ch1 …

Block
activity
{ SMEV ev1 ev2 ev3 …
SMTR tr1 tr2 tr3 …
time

Soft IP Summary
Soft IP Main Control for Analog System
Configurable via Setting Generics/Parameters at top-
level
Pipelined Operation
Complex Sequencing, Branching, and Looping
Operations Possible With Limited Hardware Resources
Completely Self-sustained System (no Micro Required)

Fusion Design Flow
Libero Flow
SmartGen
Simulation

Libero IDE
Integrated Development Environment

Schematic Editor
HDL entry tools
SmartGen Wizard
Actel IP Cores
Logic Synthesis
Logic Simulator
I/O Editor
Place & Route tools
Timing Analysis
Device Programming

Familiar FPGA Design Flow
Schematics Libero IDE
Simulation
Verilog/VHDL
IP Blocks
SmartGen
Logic Synthesis
Programmed
FPGA
Place & Route

Fusion Design Flow
Libero Flow
SmartGen
Flash Memory System Builder
Other SmartGen Cores
Simulation

Libero with SmartGen

SmartGen Cores for Fusion
New System Builders
New Silicon Cores
Divided and Delayed Clock
Crystal Oscillator
VRPSM
NGMUX
RC Oscillator
Dynamic CCC
Enhanced Cores from ProASIC3/E
Static PLL
Delayed Clock
RAM
Initialization from Flash Memory

Analog & NVM System Generation
User
Analog System Generation Flash Memory System Generation
SmartGen SmartGen
Config File
Analog System Builder Flash Memory System Builder
RTL Mem files Mem files RTL
ASSC+RAM ASSC.mem NVM.mem Init IP
NVM.efc
SMEV+RAM SMEV.mem NVM
SMTR+RAM Programming
SMTR.mem Files NVM Top
AB AB.mem
Analog Top

Fusion Design Flow
Libero Flow
SmartGen
Simulation

SmartGen


Supported Clients
Analog System
Initialize AB and Analog System soft IP RAM data
Uses configuration file generated by Analog System Builder
Data Storage Clients
Use NVM as a hard-drive. Partition and access the NVM memory.
Initialization Clients
User clients that required initialization and start-up
RAM Initialization Client
Special type initialization client
Generated by SmartGen
Uses configuration file generated by SmartGen
CFI Data Client
Used to store the query data for CoreCFI
The data is stored in a reserved page location. This client does not take up any of
the 2048 pages in the Flash Memory
CoreCFI Provides an Industry-Standard External Interface to Actel Fusion™
Flash Memory

Flash Memory Builder Features
Supports the Following Memory File Formats
Intel-Hex
Motorola-S
Actel-Hex
Actel-Binary
Generates Map Files for Programming the NVM
Clients are Page Aligned
Clients are Initialized Sequentially
Start Addresses for Partitions
Automatically managed
Manually specified and locked for applications requiring fixed addresses
Automatic Conflict Resolution for Overlapping Client Partitions

Initialization Client
Specify Clients to be Initialized at
Start-up
Supported Word Sizes
8 bit & 9 bit
On-demand Save-back to NVM
Multiple Memory file Formats
Supported

Data Storage Client
Create a Partition in the Flash
Memory System and Specify the
Memory Content for That
Partition
Supported Word Sizes
1 byte, 2 byte, 4 byte
Start Address
Ability to Lock Start Address
(System Builder Level)

RAM Initialization Client
The RAM Initialization Client is a Special
Type of Initialization Client That Allows Select Client Name from pull-
RAM to be Initialized at Power-up down menu
Memory Editor in SmartGen used to
specify RAM content
Difference from Initialization Client:
Cascading Of Multiple RAM Blocks Is
Handled Automatically
Initialization on a 9-bit Data Bus for
Optimized Write Cycles
Logic Automatically Created for
Multiplexing Initialization and run time
Interfaces
Set JTAG Protection

Analog System Client
Load the Configuration File Generated by the Analog
System Builder Into the Flash Memory System Builder
The Analog System Components can be Initialized by the
Flash Memory System at Start Up
Select Client Name from pull-

down menu

Flash Memory System Builder with RAM
Initialization Client
Start address
Start and end pages
Lock start address

Flash Memory System
Restrictions
Minimum Usage per Client: 1 Page
Maximum Data Storage Clients: 64
Maximum Initialization Clients: 64
Analog System takes 6 Initialization Clients
4 Initialization Clients if Calibration IP is not used
Each RAM takes as many Initialization Clients as Number of
RAM Blocks in the RAM

Fusion Design Flow
Libero Flow
SmartGen
Simulation

Creates Complete Analog System Including
AB Hard-Macro
Analog System Soft-IPs (RTL)
Analog System data storage RAMs
Memory files for simulation
Configuration file for import into NVM System

Analog System Builder in Libero

Supported Peripherals
Voltage Monitor
Current Monitor
Temperature Monitor
Output Gate Driver
RTC (Real Time Counter)

Enter system ADC clock rate Specify ADC resolution Choose Advanced Options
clock rate
Sampling rate for

channel
Assign pins for
analog channels
Select peripherals Define ADC sampling
sequence

Voltage Monitor Settings
Signal Name
Name of analog pad in top-
level design
Acquisition Time
Sample & Hold Duration
Digital Filtering
Digital Averaging Factor
Initial Value
Maximum Voltage
Used to set the pre-scaling
factor
User range 0V to +12 or -
12V to 0V
ADC range -3V to + 3V

Voltage Monitor Flag Settings
Voltage Comparison Flag
Specification
Flag Name
Specify Flag Assertion when
Under or Over Threshold
Threshold level (V)
Number of consecutive times
the signal is above or below
threshold for flag to assert
and de-assert
Eliminate cases where a
single glitch causes the flag
to assert
Make sure the signal is really
above or below range for
flag assert
Make sure the condition that
caused the flag assertion is
really gone before de-
asserting the flag

Current Monitor
Requires a Voltage-current Channel Pair Placed On
Adjacent Package Pins
Measures Differential Voltage Across External Resistor
The differential voltage is multiplied by 10x before it is applied to the
ADC
Choose an external resistor that ensures that the difference in
voltages is less than the value of Vref
Optionally Monitors Voltage on the Voltage Channel in the
Pair
Options identical to voltage monitoring service
Voltage Differential Must be Less Than or Equal to VREF

Current Monitor Settings
Digital Filtering
Initial Value
Acquisition Time
Sample & Hold duration
Signal Name
Name of analog pad in top-level design
External Resistor
Value of the resistor connected across the
Current-Voltage pair
Current Comparison Flag Specification
Flag Name
Specify Flag Assertion when Under or
Over Threshold
Threshold level (A)
Number of consecutive times the signal is
above or below threshold for flag to assert
and de-assert
Voltage Monitor Settings Same as
Voltage Monitor

Measures The Differential Voltage Between A Pair Of
Voltage And Current Input Channels
Uses same components as Current Monitor
Requires two channels (AV and AC)
they must be on adjacent package pins
Optionally Monitors Voltage on the Voltage Channel in the
Pair

Differential Voltage Monitor Settings
Digital Filtering
Initial Value
Acquisition Time
Signal Name
Name of analog pad in top-level
design
Differential Voltage Comparison
Flag Specification
Flag Name
Specify Flag Assertion when Under
or Over Threshold
Threshold level (V)
Number of consecutive times the
signal is above or below threshold
for flag to assert and de-assert
Voltage Monitor Flags same as
Voltage Monitor

Temperature Monitor
Measures Differential Voltage Across External Diode
Configuration Settings
Identical to the voltage monitoring service, except maximum supply
voltage.

Temperature Monitor Settings
Digital Filtering Factor
Acquisition Time
Signal Name
Name of analog pad in top-level
design
Temperature Comparison Flag
Specification
Flag Name
Specify Flag Assertion when
Under or Over Threshold
Threshold level (oC)
Number of consecutive times the
signal is above or below
threshold for flag to assert and
de-assert

Output Gate Driver
Analog Output from the FPGA
Controlled via the Gate Driver
Enable
Active High
Generated with FPGA gates
Turn External PMOS or NMOS
Transistor ON or OFF (Gate
Driver Polarity)
Can be Driven by Flag Logic
from Analog System to Build a
Self-controlled Design

Enables Use of Unused Analog Inputs as Slow Digital
Inputs
Useful if Running Out of I/Os in a Design
Does Not Need to be Sequenced Via Sample Sequencer
Does Not Impact Throughput of the Analog System

Used to Monitor the Chip
Temperature
32nd Channel in the Analog
Mux
Similar to External
Temperature Monitor
Flags Can be Used to
Detect Overheating of the
Device
One Per Device

Used to Monitor 1.5V Supply
to FPGA Fabric and NVM
Channel 0 on the Analog
Mux
Similar to Voltage Monitoring
Flags Can be Used to
Detect and Handle Brown-
out Conditions
One Per Device

RTC Configuration in SmartGen
Crystal Oscillator Mode Control
RTC CLK must be driven by XTLOSC
RTC controls XTLOSC Mode
Low Gain (32 kHz to 200 kHz)
Medium Gain (200 kHz to 2 MHz)
High Gain (2 MHz to 20 MHz)
Match with Register Value
Triggers MATCH when counter equals 40-bit match value
Initial value
Can specify non-zero value
Reset Counter to Zero
Works as a timer application when chosen
Works as an elapsed time record if not chosen
Export MATCH Signal
Asserts RTCPSMMATCH to activate Voltage Regulator Power Supply
Monitor (VRPSM)

RTC Configuration in SmartGen
Two Views in SmartGen
Enter desired time or match value

RTC Design Considerations
Uses Analog System Configuration Bus for Setting the
Various Values
Can be Used with VRPSM & XTLOSC to Create a Self
Wake-up Application
Analog Block System Clock FMAX = 100 MHz but
RTC Initialization clock FMAX = 10 MHz

with Peripherals
Analog System Builder After Adding Peripherals

Sample Sequencer
ADC has 32 Input Channels
30 external inputs + Internal Temperature + Internal Voltage
Each channel must be sampled individually
TDM Sequencing Used (64 Time Slots)
SmartGen Sample Sequence “Procedures”
“Procedure” is a named group of samplings
(Power Up; Calibrate; Run; Standby; Power Down, etc.)
“Procedure” can be as small as one and as many as 64 samplings
Support for Multiple Independent “Procedures” and Repeat
“Procedures”
Jump to New Procedure Caused by Terminating Operation in a
Sequence or an External Trigger
Supports use models where different channels are sampled at
different times during system operation
Example: power-up sequence and normal operation sequence

Sample Sequence Specification
Main Procedure – System Default
Always starts at slot 0 and always executed upon reset
Cannot be deleted or unlocked
Additional Procedures
Define additional procedures based on system requirements
Procedures Must be Triggered by External User Logic Through the
External ASSC Control ports
Two modes:
Jump and continue
Assert ASSC_SEQJUMP for 1 clock to execute slot at ASSC_SEQIN
Single Step
Set ASSC_XMODE = 1, to enable single step through sequencer
Assert ASSC_XTRIG for 1 clock to execute slot at ASSC_SEQIN

SmartGen
Sample Sequencer GUI
Add or Delete a Procedure
Sequence for
selected procedure

Sampling Sequence Operations
Available Operations:
SAMPLE - Sample a channel that is configured in the system and proceed
to the next slot
SAMPLE_JUMP – Sample a channel that is configured in the system and
jump to the start of the specified procedure
CALIBRATE – Perform a full calibration of the Fusion ADC and proceed to
the next slot
Takes 3840 ADC Clock cycles
CALIBRATE_JUMP – Perform a full calibration of the Fusion ADC and jump
to the start of the specified procedure
JUMP – Jump to the start of the specified procedure
POWERDOWN – Perform a powerdown operation on the ADC;
After a powerdown is initiated, a calibration operation is required to resume
sampling
STOP – Stop the sequencer
An external trigger is required to re-start the sequencer
NOP – No operation is performed and proceed to the next slot
NOP’s in the middle of a sequence use up a time slot; NOP’s after the end of the
last functional slot do not use up a time slot

SmartGen
Sample Sequencer with Procedures
Add or Delete a Procedure
Defined procedures
Sample rate for

each channel in
selected procedure
Sequence for Jump Destination

selected procedure

Pin Assignments and Generate
Analog Pin Assignments are

Made in SmartGen
Click Generate to create the

Analog System Soft IP

Fusion Backbone
SmartGen Output Files
Analog System Builder Output
Analog System Log File

Output

Fusion Analog Block IP
Basic Configuration
Initialization Clock for the Analog System

must be less than 10 MHz
PLL and NGMUX can be used to
provide a slow initialization
frequency and a fast operating
frequency

Fusion Design Flow
Libero Flow
SmartGen
Simulation

Crystal Oscillator
New for Fusion
Mode control from FPGA or RTC
Mode selection for Gain
Low Gain (32 – 200KHz)
Medium Gain (200KHz - 2MHz)
High Gain (2MHz - 20MHz)

VRPSM, NGMUX and RCOSC
Very few configuration options
NGMUX and RCOSC available under Clock Conditioning
Cores
VRPSM in Voltage Regulator Category

Static PLL
Similar to ProASIC3 PLL
Dividers, Delays, Phase-shift & MUX selections
New Input Clock Sources
Crystal Oscillator
RC Oscillator
GLA Output Divider Available in PLL Bypass Mode
Divider values 1 - 32
RC Oscillator Clock Source Considerations
Input Clock frequency is 100MHz
Extra Divide-by-half feature available
Dividers with values 0.5, 1.5, 2.5 …. 31.5
SmartGen does not Include the XTL/RCOSC Library Macro as part of
PLL Generation
User must manually connect XTLOSC or RCOSC to CLKA

Divided and Delayed Clock
New for Fusion
Divide a Clock and Optionally Delay by a Given Amount
Clock Source Options Same as Static PLL
Same divider Options as static PLL Including the RC Oscillator Divide-
by-half
Divider RESET for Predictable Edge Synchronization Between Input and
Output Clock

Fusion Design Flow
Libero Flow
SmartGen
Simulation
Analog Block Simulation
Flash Memory Block Simulation

Supported Simulators
The Analog Block Simulation Flow Works With All Digital
Simulators That Actel Supports
ModelSim VHDL
Cadence NC-VHDL
ModelSim Verilog
Cadence NC-Sim
Cadence NC-Verilog
The Digital Simulation Flow Correctly Handles All 37
Analog Inputs
VAREF, GNDREF, AV0-AV9, AC0-AC9, AT0-AT9,
ATRETURN01, ATRETURN23, ATRETURN45, ATRETURN67,
ATRETURN89
Analog Block Simulation Requires Using Actel-supplied
VHDL Procedures or Verilog Modules

Input Stimulus for Analog System
Create Analog System Netlist Using SmartGen

Each analog pin will be configured as either an analog or a digital
input
Use analog_io Package Contained in
<drive>:\Actel\Libero_v8.5\Designer\lib\vtl\95\fusion.vhd
library fusion;
use fusion.analog_io.all;
For Input AV0 Configured as an Analog Input
drive_analog_input( 0.3, AV0 );
This converts the real number 0.3 into a serial-bit-stream which
drives AV0
For Input AV1 Configured as a Digital Input
AV1 <= ‘1’;

VHDL Simulation
Analog IO Procedures
Use the Procedures Contained in Package analog_io
procedure drive_analog_input(analog_val : in real;

signal serial : out std_logic);
procedure drive_current_inputs(volt_real : in real;
resistor : in real;
current : in real;
signal av : out std_logic;
signal ac : out std_logic );
procedure drive_differential_inputs(volt_real : in real;

delta : in real;
signal av : out std_logic;
signal ac : out std_logic );
procedure drive_temperature_quad(temp_celsius : in real;

signal serial: out std_logic );

Driving Analog Input
VHDL Simulation
Pass a Constant into Procedure
drive_analog_input( 0.3, AV0 );
This converts the real number 0.3 into a serial-bit-stream which drives
AV0
Pass a Real Variable into Procedure
variable AV0real : real;
AV0real := 0.3;
drive_analog_input( AV0real, AV0 );

VHDL Simulation
Driving Analog Input Using Signal (Not Recommended)
VHDL Signal Assignments do not Occur Instantly

Example of poorly written code with unexpected behavior
signal AV0real : real;
AV0real <= 0.4;
wait on AV0real;
AV0real <= 0.3;
drive_analog_input( AV0real,AV0 ); -- AV0 will be assigned 0.4 not 0.3
Make Sure that the Signal Value has been Updated when
Passing a Signal into drive_analog_input
A wait statement can be used for this
signal AV0real: real;

serialize_AV0:process
begin
wait on AV0real;
drive_analog_input ( AV0real, AV0 );
end process serialize_AV0

VHDL Simulation
Restrictions
You Cannot Call drive_analog_input From a Process
With a Sensitivity List
drive_analog_input contains wait statements
NC-VHDL does not allow a subprogram with wait statements to be
called from a process with a sensitivity list

Input Stimulus for Analog System
Verilog Simulation
Create Analog System Netlist Using SmartGen
Each analog pin will be configured as either an analog or a digital
input
Use the Verilog Modules drive_analog_io and
read_analog_io contained in:
<drive>:\Actel\Libero_v8.5\Designer\lib\vlog\fusion.v
For Input AV0 Configured as an Analog Input:
drive_analog_io drive_AV0( 0.3, AV0 );
This converts the real number 0.3 into a serial-bit-stream which
drives AV0
For Input AV1 Configured as a Digital Input:
assign AV1 = 1’b1;

Verilog Simulation
Analog IO Modules
Use the Modules Provided by Actel
module drive_analog_input (parallel_in, serial_out);
module drive_current_inputs (volt_vect, resistor_vect, current_vect, av,

ac);
module drive_differential_inputs (volt_vect, delta_vect, av, ac);
module drive_temperature_quad (temp_celsius, serial_out);

Verilog Simulation
Restrictions
You Cannot Instantiate drive_analog_io in a Procedural
Block
Must instantiate macro outside the procedural block

WaveFormer Lite
Supports Creation of Analog Stimulus for Fusion
Pre-defined analog waveforms are available such as Sinusoidal, Step,
Increment, Random, and RC discharge
VHDL Testbench includes VHDL procedures in analog_io package
drive_current_monitor(volt_real, resistor, current, signal_serial);
drive_current_inputs(volt_real, resistor, current, signal_av, signal_ac);
drive_differential_inputs(volt_real, delta, signal_av, signal_ac);
drive_temperature_quad(temp_celsius, signal_serial);
Verilog Testbench includes modules for analog inputs provided by
Actel
module drive_analog_input ( parallel_in, serial_out );
module drive_current_inputs ( volt_vect, resistor_vect, current_vect, av, ac );
module drive_differential_inputs ( volt_vect, delta_vect, av, ac );
module drive_varef_out ( parallel_in, en_out, serial_out );
module drive_current_monitor (volt_vect, resistor_vect, current_vect, serial_out );
module drive_temperature_quad ( temp_celsius, serial_out );

Fusion Analog Signals
Specify Signal Type
Select Temperature,
Voltage or Current
from list

Using Built-In Waveforms
Click to select list of signal functions
,(Concatenate)
Inc(start, increment, count)
Dec(start, decrement, count)
IncString(“string”, start, increment, count)
Range(start, finish, count)
RandInt(count, Range_to_zero)
Hex(list)
Bin(list)
Rep((list, count)
Skip(count)
File(“filename.txt”)
Signal(“signalname”)
Map{operations} list
PRBS7(length, seed)
PRBS15(length, seed)
Sin(amplitudeV, period, duration)
SinStart(amplitudeV, period, duration)
SinEnd(amplitudeV, period, duration)
CapCharge(amplitudeV, RC, duration)
CapDischarge(amplitudeV, RC, duration)
Ramp(StartV, EndV, Duration)


WaveFormer Lite
VHDL Testbench
architecture STIMULATOR of stimulus is
-- Control Signal Declarations
signal AV5V_driver : real;
signal Temp_driver : real;
...
begin
...
-- Actel Analog Drivers Block
drive_analog_input(AV5V_driver, AV5V);
drive_temperature_quad(Temp_driver, Temp);
...
-- Sequence: Unclocked
Unclocked : process
begin
AV5V_driver <= 0.0;
Temp_driver <= 5.0;
wait for 12 ns;
INIT_POWER_UP <= '1';
wait for 28 ns;
SYS_RESET <= '1';
wait for 379907 ns;
AV5V_driver <= 0.1;
wait for 20132 ns;
...
WaveFormer Lite
Verilog Testbench
module stimulus(SYS_CLK, SYS_RESET, INIT_POWER_UP, VAREF, Supply_good,
Over_temp, ATRETURN01, AV5V, Temp);
output SYS_CLK;
output SYS_RESET;
. . .
reg SYS_RESET_driver;
reg INIT_POWER_UP_driver;
reg VAREF_driver;
reg ATRETURN01_driver;
real AV5V_driver;
real Temp_driver;
. . .
drive_analog_input analog_AV5V_driver($realtobits(AV5V_driver), AV5V);
drive_temperature_quad temperature_Temp_driver($realtobits(Temp_driver), Temp);
. . .
task Unclocked;
begin
#12;
INIT_POWER_UP_driver <= 1'b1;
#26;
SYS_RESET_driver <= 1'b1;
#380193;
AV5V_driver <= 0.1;
#19;
Temp_driver <= 5.75;
#19725;
Temp_driver <= 15.0;
#25;

Viewing Values of Serialized Signals in Simulator
Waveform Viewer Shows the Values of the Serialized Signals as ‘Z’

The serialization procedure in the simulation models occurs in zero
simulation time, using delta delays
The remainder of the time the serialized signal is ‘Z’
ModelSim displays both the time and the delta during simulation

Restrictions on AV/AC/AT Voltages for Current and
Temperature Monitors
Analog Voltage Reference
Selected by VAREFSEL
0 = voltage supplied from internal reference = 2.56V
1 = external voltage applied = VAREF
Current Monitor
Maximum value is voltage reference
10 times the difference in the absolute voltages applied on the AV and AC
quads
If exceeded then the current monitor output will saturate at the reference
voltage.
If internal reference used:
Saturates at 2.56V when difference between AV and AC is 0.256V or greater
Temperature Monitor
Maximum value is voltage reference
12.5 times the absolute voltage applied on the AT quad
If exceeded then the temperature monitor output will saturate at the
reference voltage.
If internal reference used:
Saturates at 2.56V when AT is 0.2048V or greater

ADC
Clock Period and Conversion Time
ADC_CLK
ADC internal clock
Minimum period is 100ns (10MHZ)
Maximum period is 2,000ns (0.5 MHZ)
Generated from user-controlled signals:
SYSCLK
TVC[7:0] (programming divider)
Conversion Time
Dependent on user design requirements:
ADC_CLK period
STC[7:0] (sample time control)
ADC mode (8, 10, or 12-bit conversion)
Minimum conversion time is 1.2us
10MHZ ADC_CLK, 8-bit conversion, and sampling time of 2 ADC_CLK periods
Maximum conversion time is 542us
0.5MHZ ADC_CLK, 12-bit conversion, and sampling time of 257 ADC_CLK periods
RESULT will not change until conversion is finished.
When the conversion is finished, DATAVALID is asserted and RESULT is driven

Fusion Design Flow
Libero Flow
SmartGen
Simulation
Analog Block Simulation
Flash Memory Block Simulation

Addressing
The NVM Array is Word-Addressable
DATAWIDTH signal used to select the size of the word
1, 2, or 4 bytes
Address bits are MSB Justified
Different from RAMs
For 1 byte access:
ADDR[17:0] are significant
For 2 byte access:
ADDR[0] is ignored
For 4 byte access:
ADDR[1:0] are ignored

Data
Data bits are LSB Justified
Same as RAMs
For 1-byte access:
DO[7:0] are significant
DO[31:8] are 0
For 2-byte access:
DO[31:16] are 0
For 4-byte access:
WEN Updates User Data into Page Buffer only
To store data into the NVM array, WEN should be followed by a
PROGRAM of the same page

Cycle Accuracy
Copy Page is Cycle-approximate
Affects any user operations which involve copy page operations
Cycle time is non-deterministic in silicon
Takes 63-67 clock cycles
Simulation models always execute copy page in 65 clock cycles
Update Page Cycle Accuracy Controlled by Generic
(VHDL) / Parameter (Verilog) FAST_SIM
Affects RESET, PROGRAM and ERASE operations
Duration of Busy
Cycle
FAST_SIM = 1(default) FAST_SIM = 0
Reset 3 SYSCLK cycles 25 us
Program
4 us 8.4 ms
Erase

Busy Operation
FAST_SIM = 1 (default)
RESET operation System Reset de-asserted Busy de-asserted after 3 clock cycles
PROGRAM operation
User program command Busy asserted for 4 us

Using FAST_SIM Generic / Parameter
Modify NVM file from SmartGen
module nvm_block(
. . .
); add
. . .
NVM #( .MEMORYFILE("nvm_block.mem"), .FAST_SIM(0) )
NVM_INST (.RD({ USER_DOUT[31], USER_DOUT[30], USER_DOUT[29], USER_DOUT[28],
USER_DOUT[27], USER_DOUT[26], USER_DOUT[25], USER_DOUT[24],
. . .
USER_DATA[3], USER_DATA[2], USER_DATA[1], USER_DATA[0]}),
. . .
VCC VCC_power_inst1 (.Y(VCC_power_net1));
endmodule nvm_block.v
architecture DEF_ARCH of nvm_block is
component NVM generic (MEMORYFILE:string := "";
add
FAST_SIM: integer := 0
port( RD: out std_logic_vector(31 downto 0);
BUSY: out std_logic;
. . .
LOCKREQUEST: in std_logic := 'U');
end component;
. . .
begin
NVM_INST : NVM generic map(MEMORYFILE => "nvm_block.mem“)
port map(RD(31) => USER_DOUT(31),
. . ., LOCKREQUEST => USER_LOCK);
. . .
end DEF_ARCH; nvm_block.vhd
Busy Operation
FAST_SIM = 0
RESET operation Busy asserted for 25us

System Reset de-asserted
PROGRAM operation
User program command Busy asserted for 8 ms

Lab 2
Complete Lab 2 in the Lab Guide
Open a project in Libero
Configure a Voltage Monitor, Current Monitor and Gate Driver
Simulate the Design

Fusion Design Flow
Libero Flow
SmartGen
Simulation

Programming & Security
Device Programming Scenarios
First-time Programming
Specify Security Information
Re-programming
Specify Previously-used Security Information
Changing Security Settings
Environments
Trusted Programming Environment
Users May Have Access to Pass Key and AES Key
Un-trusted Programming Environments
Never Expose Pass Key or AES Key
Never Program Security Settings

FlashPoint
Start-up Screen

FlashPoint
Security Settings

FlashPoint
FlashROM

Fusion Starter Kit
Designed to Showcase Fusion
FPGA – single volt operation
Crystal – 32 kHz for RTC
Tri-color LED to exhibit PWM
MOSFET on board to power control
Potentiometer for analog voltages
LCD to display values
Temperature diode on board
Fusion can monitor own current draw!
Starter Kit Features
All I/O brought out to headers
JTAG headers for programming & chain
Daughter card pins compatible w/PA3
Prototyping area
Contents
Libero IDE Gold
Fusion evaluation board
FlashPro3
Tutorial and documentation
Logic Navigator debugger
Available Now

Fusion Embedded Development Kit
Develop designs using
Fusion Mixed-Signal FPGA
M1AFS1500-FGG484
Cortex-M1 embedded processor
8051s embedded processor
Ethernet applications
The development kit includes

Low Cost Programming Stick
Libero IDE
Free Libero IDE Gold license
SoftConsole for Compile/Debug
On Chip Program and Debug
User’s guide and tutorial
Example designs
PCB schematics and layout files
Ordering code
M1AFS-EMBEDDED-KIT @ $199

Fusion Embedded Development Board Features
RoHS compliant
10/100 Ethernet interface
USB-to-UART interface
I2C interface
Built-in temperature monitor
Voltage potentiometer
RealView debug header
OLED 96x16 pixel display
4,000,000 SRAM

Fusion Advanced Development Kit
Microprocessor and System Management Applications
Development Platform
Supports the Following Functions:
Power-up detection
Thermal management
Power sequencing
Sleep modes
System diagnostics
Remote communications
Clock generation and management
Kit Contents:
FlashPro3programming stick
2 Mini USB cables
Fusion Advanced Development Board with ARM Cortex-M1–enabled
M1AFS1500-FGG484
Libero IDE DVD, including SoftConsole for processor-based designs

Barto's Law
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26 October - 20 November, 2009: Fpga Design & VHDL Fundamentals of Fpgas

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2065-19

Advanced Training Course on FPGA Design and VHDL for Hardware

26 October - 20 November, 2009

FPGA Design & VHDL

Actel Corporation Confidential © 2009 3

Actel Corporation Confidential © 2009 4

Actel Corporation Confidential © 2009 5

Actel Corporation Confidential © 2009 6

Actel Corporation Confidential © 2009 7

Actel Corporation Confidential © 2009 8

Actel Corporation Confidential © 2009 9

A large number of logic gates in an IC

The Four Components of FPGAs

Actel Corporation Confidential © 2009 10

Actel Corporation Confidential © 2009 11

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Bit Select 1 Bit Select 2 Input

SRAM Flash Anti-fuse

Best of Both Worlds

Large Switch Small Switch Smallest Switch

ProASIC, ProASICPlus, ProASIC3 Routing Switch

Actel Corporation Confidential © 2009 15

Reprogrammable Yes No Yes

Preserves configuration when off No Yes Yes

Requires external configuration

Instantly on No Yes Yes

IP security Acceptable Excellent Excellent

Power consumption Medium Low Low

Actel Corporation Confidential © 2009 16

Actel Corporation Confidential © 2009 17

Actel Corporation Confidential © 2009 18

Control Store 110101011101010010001

Actel Corporation Confidential © 2009 19

Actel Corporation Confidential © 2009 20

Actel Fusion® FPGA

Actel Corporation Confidential © 2009 22

Actel Corporation Confidential © 2009 23

Actel Corporation Confidential © 2009 24

Actel Corporation Confidential © 2009 25

Actel Corporation Confidential © 2009 26

Actel Corporation Confidential © 2009 27

Actel Corporation Confidential © 2009 28

Actel Corporation Confidential © 2009 29

Actel Corporation Confidential © 2009 30

Actel Corporation Confidential © 2009 31

Actel Corporation Confidential © 2009 32

System Memory Cache Memory NV Storage

MPU / MCU FPGA / ASIC

Analog Power Clock Discrete

Actel Corporation Confidential © 2009 33

Actel Corporation Confidential © 2009 34

Actel Corporation Confidential © 2009 35

Actel Corporation Confidential © 2009 36

Actel Corporation Confidential © 2009 37

Tiles (D-FF) 2,304 6,144 13,824 38,400

FlashROM bits 1Kbits 1Kbits 1Kbits 1Kbits

Max Digital I/O 75 114 172 252

QN180 60/16 (20) 65/15 (24)

PQ208 93/26 (24) 95/46 (40)

The Four Components of FPGAs

All Devices Have 6 Clock Conditioning Circuitry (CCC)

Switching from CLK0 to CLK1: