Av2026 Airoha Dvbs Tuner Ic

AV2026 Digital Satellite Tuner

S i n g le C h i p T u n e r f or D V B - S / A B S - S R ecei v e r
Datasheet
VERSION 0.20 18-Jul-11
This document is commercially confidential and must NOT be disclosed to third parties without prior consent.
The information provided herein is believed to be reliable. But production testing may not include testing of
all parameters. AIROHA Technology Corp. reserves the right to change information at any time without
notification. ( HTTP://WWW.AIROHA.COM.TW TEL:+886-3-6128800 FAX:+886-3-6128833 [email protected] )

AV2026
Single Chip Tuner for Digital Satellite Receiver
This document is commercially confidential and must NOT be disclosed

to third parties without prior consent.
The information provided herein is believed to be reliable. But
production testing may not include testing of all parameters. AIROHA
Technology Corp. reserves the right to change information at any time
without notification.
Page 2 of 17 CONFIDENTIAL

AV2026 Single Chip DVB-S/ABS-S Tuner
Datasheet Copyright © 2011, Airoha Technology Corp.
Version 0.20 2011/07/18

AV2026
Revision History
Version Change Summary Page Date
0.10 Created 02-Nov-10
0.20 RFIN- Description 7,8 18-Jul-11

Version 0.20 2011/07/18

AV2026
INDEX
Revision History ........................................................................................................ 3
1 Features ............................................................................................................ 5
2 Description ........................................................................................................ 5
3 Pin Assignment .................................................................................................. 6
4 Pin Name Description ......................................................................................... 7
5 Block Diagram and Description ............................................................................ 8
5.1 General Description ......................................................................................... 8
5.2 Receiver Section ............................................................................................. 9
5.3 Synthesizer/VCO/XO Section ............................................................................ 9
5.4 Control Section ............................................................................................... 9
6 2-wire Serial Interface ...................................................................................... 11
6.1 Read/write Timing Parameters ....................................................................... 11
6.2 Read/write Procedures .................................................................................. 12
7 Electrical Characteristics ................................................................................... 13
7.1 Absolute Maximum Ratings ............................................................................ 13
7.2 DC Electrical Specifications ............................................................................ 14
7.3 AC Electrical Specification .............................................................................. 15
8 Package Dimension .......................................................................................... 17

Version 0.20 2011/07/18

AV2026
1 Features
 Input RF Frequency: 850MHz to 2300MHz
 Single +3.3V Power Supply
 Embedded LNA, Mixer, VCO, crystal oscillator and LDO regulators
 Embedded DC offset Cancel Circuit
 No Calibration Required
 Programmable channel f ilter with bandwidth from 4MHz to 40MHz
 Embedded RF signal loop through path
 2-wire serial control interface
 QFN4*4mm 28pin package
2 Description
AV2026 is a highly integrated single chip for DVB-S/ABS-S Tuner receiver application. The
input RF signal frequency ranges from 850MHz to 2300MHz. AV2026 implements zero-IF
direct conversion architecture with embedded LNA, Mixer, VCO, crystal oscillator and LDO
regulators to minimize the external BOM cost. There is no additional calibration procedure
required in AV2026 during power-on procedures. A programmable baseband channel
filter is also implemented to provide different channel bandwidths from 4MHz to 40MHz. A
27MHz reference clock with on-chip buffer is also provided for the baseband section clock
source. A simple 2-wire interface allows easy control from the baseband controller.

Version 0.20 2011/07/18

AV2026
3 Pin Assignment
2 1 2 1 T

G P P G U
E A A P E O
R C C C R 1
C G G C C G
C E E C P C E
V R R V C V R
28 27 26 25 24 23 22
REG2OUT 1 21 VDDD
VCCRF1 2 AIROHA 20 VCCXO
RFIN+ 3
AV2026
AV2020 19 XTAL1
RFIN- 4 18 XTAL2
Digital Satellite Tuner
VCCRF2 5 17 ADDR1
RFAGC 6 16 SDA
RFLP 7 15 SCL
8 9 10 11 12 13 14
P N F

I N P
I T 0
I S R
Q Q Z X X
X X C E D
R R T
R R C D
V A

Version 0.20 2011/07/18

AV2026
4 Pin Name Description

PIN SIGANL TYPE DESCRIPTION
1 REG2OUT Regulator Output RFVCC Regulator Output

2 VCCRF1 VCC Supply RFVCC Supply Voltage for RF Circuits
3 RFIN+ Input, Analog RF Signal Input
4 RFIN- Analog LNA virtual ground
5 VCCRF2 VCC Supply RFVCC Supply Voltage for RF Circuits
6 RFAGC Input, Analog Control RF AGC Control Voltage
7 RFLP Output, Analog RF Loop Through Signal Output
8 RXQP Output, Differential Analog BB Output
9 RXQN Output, Differential Analog BB Output
10 VCCZIF VCC Supply RFVCC Supply Voltage for ZIF Circuits
11 RXIN Output, Differential Analog BB Output
12 RXIP Output, Differential Analog BB Output
13 TEST Input, Digital Control Should be connected to ground
14 ADDR0 Digital Device Address Control
15 SCL Input, Digital Serial Interface
16 SDA Input/Output, Digital Serial Interface
17 ADDR1 Digital Device Address Control
18 XTAL2 Analog XTAL Input
19 XTAL1 Analog XTAL Input
20 VCCXO VCC Supply DIGVCC Supply Voltage for XO Circuits
21 VDDD VCC Supply DIGVCC Supply Voltage for Digital Circuits
22 REG1OUT Regulator Output DIGVCC Regulator Output
23 VCCREG1 VCC Supply 3.3V Supply Voltage for Regulator
24 CP Analog Charge Pump
25 VCCCP VCC Supply RFVCC Supply Voltage for CP Circuits
26 REGCAP2 Analog Regulator Output for External Capacitor
27 REGCAP1 Analog Regulator Output for External Capacitor
28 VCCREG2 VCC Supply 3.3V Supply Voltage for Regulator

Version 0.20 2011/07/18

AV2026
5 Block Diagram and Description
5.1 General Description
2 1 2 1 T

G P P G U
E A A P E O
R C C C R 1
C G G C C G
C E E C P C E
V R R V C V R
28 27 26 25 24 23 22
REG2OUT 1 Regulator Regulator Regulator 21 VDDD
VCCRF1 2 20 VCCXO
Synthesizer
RFIN+ 3 19 XTAL1
/2
RFIN- 4 18 XTAL2
VCCRF2 5 D D
17 ADDR1
C C
O O
C C
RFAGC 6 16 SDA
Control
&
RFLP 7 Register 15 SCL
8 9 10 11 12 13 14
P N F

I N P
I T 0
I S R
Q Q Z X X
X X C E D
R R T
R R C D
V A
AV2026 is a single chip IC for DVB-S/ABS-S Tuner receiver application. There are three
main sections within AV2026, i.e. the Receiver section, the synthesizer/PLL/VCO section
and the control section. Embedded LDO regulators are also integrated in AV2026 such
that only a single 3.3volt VCC supply is needed.

Version 0.20 2011/07/18

AV2026
5.2 Receiver Section

The Receiver section comprises a LNA and RF variable gain amplifiers, a Zero-IF mixer, a
programmable channel filter and a VGA. The RF signal is directly down-converted to
baseband signals, filtered by the channel filter and amplified by the VGA and then output
to RXIQ output pins. An internal DC offset cancellation mechanism is implemented to
reject DC offset at RXIQ output signals.
A loop-through path is also provided in AV2026. The input RF signal can be re-transmitted
to another receiver box through this path. A buffer amplifier is used to keep the RF signal
unchanged to the next receiver. This path can be enabled/disabled independently.
5.3 Synthesizer/VCO/XO Section

A fractional-N frequency synthesizer architecture is implemented in AV2026. The input RF
frequency ranges from 850MHz to 2300MHz. An on-chip VCO with embedded loop filter is
also included in AV2026. A crystal oscillator is provided in AV2026 and only an external
crystal is needed. The generated 27MHz reference clock signal can be output to baseband
processor.
5.4 Control Section

A 2-wire control interface is implemented in AV2026. Detailed timing diagram and
read/write procedures of the 2-wire interface are described in chapter 6. A 7-bit device
address plus read/write bit is required for this 2-wire interface. There are four device
addresses available in AV2026 in each read and write mode, selected by external pins
ADDR0/ADDR1, as listed in table 5.1 and table 5.2. The level of ADDR1/0 would be “High”
if it kept open or NC, and would be “Low” if connected to GND directly.

Version 0.20 2011/07/18

AV2026
7-bit Address Read Address

ADDR1 ADDR0 R/W bit
MSB LSB (in Hex)
Low Low 1 1 0 0 0 0 0 1 0xC1
Low High 1 1 0 0 0 0 1 1 0xC3
High Low 1 1 0 0 0 1 0 1 0xC5
High High 1 1 0 0 0 1 1 1 0xC7
Table 5.1: Read Address
7-bit Address Write Address

ADDR1 ADDR0 R/W bit
MSB LSB (in Hex)
Low Low 1 1 0 0 0 0 0 0 0xC0
Low High 1 1 0 0 0 0 1 0 0xC2
High Low 1 1 0 0 0 1 0 0 0xC4
High High 1 1 0 0 0 1 1 0 0xC6
Table 5.2: Write Address

Version 0.20 2011/07/18

AV2026
6 2-wire Serial Interface

6.1 Read/write Timing Parameters
TS1 TH1 TLOW THIGH TIR TIF TPS TS3 TBUF
70%
CLOCK
30%
70%
DATA
30%
START TIR TH2 TS2 TIF TOF STOP START

SYMBOL PARAMETER MIN TYP MAX UNIT

CLOCK Frequency 0 400 KHz
TS1 CLOCK Input to DATA N-edge Setup time (START) 600 ns
TH1 CLOCK Input to DATA N-edge Hold time (START) 600 ns
TS2 DATA Input to CLOCK P-edge Setup time 100 ns
TH2 DATA Input to CLOCK N-edge Hold time 0 900 ns
TS3 CLOCK Input to DATA P-edge Setup time (STOP) 600 ns
TBUF STOP to START time 1300 ns
TOF DATA Output Fall time 20 250 ns
TIR DATA Input & CLOCK Rise time 20 300 ns
TIF DATA Input & CLOCK Fall time 20 300 ns
THIGH CLOCK HIGH duration 600 ns
TLOW CLOCK LOW duration 1300 ns
TPS Input Filter Pulse Suppression 50 ns

Version 0.20 2011/07/18

AV2026
6.2 Read/write Procedures
AV2026 allows single register read/write and multiple registers write sequentially through
the 2-wire interface. The procedures are described as follows. In each R/W process a read
or write device address is first transmitted, then followed by the register address and data
content. There are four device addresses available in AV2026 for read/write mode, and is
selected by external pins ADDR0/ADDR1 as described in Sec 5.4.
Single Write Procedure

S S
T A A A T
A Write-mode C Register X C Register X C O
R K K K
T Device Address Address Data P
Sequential Write Procedure

S S
T A A A A A T
A Write-mode C Register X C Register X C Register X+1 C Register X+Y C O
R K K K K K
T Device Address Address Data Data Data P

Single Read Procedure
S S S
T A A T A A T
A Write-mode C Register X C A Read-mode C Register X C O
R K K R K K
T Device Address Address T Device Address Data P

Version 0.20 2011/07/18

AV2026
7 Electrical Characteristics
7.1 Absolute Maximum Ratings

AV2026 could be damaged by any stress in excess of the absolute maximum ratings listed below.
ITEM MIN. MAX.
Power supply voltage (VCCREG1/2) – 0.3V 5.5V

Pin voltage – 0.3V HOST_IO_VCC + 0.3V
Maximum power dissipation - 0.5W
Operating temperature – 20 C ° +85 C°
Storage temperature – 65 C ° +150 C

°
LNA input level - +10 dBm

Digital pin - +5mA
RFAGC pin - +5mA
*Connect current limit resistor at Digital pin, RFAGC pin.

Version 0.20 2011/07/18

AV2026
7.2 DC Electrical Specifications

Typical values are measured at VCCREG=3.3V, Ta=25oC on Airoha AV2026 evaluation board unless the
items specified in the notes of the table.
Item Symbol Test Condition Min. Typ. Max. Unit
Power Supply Voltage VCCREG 2.97 3.3 3.63 V
Power Supply Current

130 140 mA
(RF Loop Through path disabled)
Power Supply Current

140 150 mA
(RF Loop Through path enabled)
Digital Input Voltage – High Level VIH 0.7*VCCREG VCCREG+0.3 V
Digital Input Voltage – Low Level VIL - 0.3 0.3*VCCREG V
Interface Output Voltage – High Level VOH IOUT = 500µA 0.8*VCCREG V
Interface Output Voltage – Low Level VOL IOUT = - 500µA 0.2*VCCREG V

Version 0.20 2011/07/18

AV2026
7.3 AC Electrical Specification

Typical values are measured at VCCREG=3.3V, Ta=25oC on Airoha AV2026 evaluation board unless the
items specified in the notes of the table.
PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Receiver Section
RF Front-End Input
Input frequency range 850 2300 MHz
RF gain control range Controlled by RFAGC pin -10 +70 dB
Noise Figure Max Gain 5 dB
RFAGC control voltage range 0.5 2.8 V
Baseband gain control range Controlled by register 12 dB
Baseband gain control step 1.5 dB/step
IIP3 -25dBm RF input 2 dBm
IIP2 -25dBm RF input 10 dBm
Adjacent Channel Rejection 23 dB
LO product leakage at RFIN -80 dBm
2LO-RF rejection -45dBm RF Input 35 50 dBc
2RF-LO rejection -45dBm RF Input 50 dBc
Baseband Output
Normal output swing 0.5 Vpp
I/Q Amplitude imbalance 1 dB
I/Q Quadrature phase imbalance @ 1.5MHz 3 deg
I/Q output impedance 50 Ohm
High pass –3dB frequency 500 1200 Hz
Channel filter -3dB Bandwidth 4 40 MHz
Channel filter Rejection Ratio > 2x F-3dB 40 dB
> 8MHz +/- 5 %
Channel filter BW accuracy
< 8MHz +/- 0.5 MHz
RF Loop Through Path
Output return loss 850-2300 MHz 10 dB
Gain 0 1.5 4.5 dB
Noise Figure 10 dB
OIP3 5 dBm
OIP2 10 dBm
Reverse Isolation 30 dBc

Version 0.20 2011/07/18

AV2026
Synthesizer/VCO/XO Section
Ref divider frequency range 27 MHz
LO integrated phase jitter 10kHz to 20MHz 2 3 Degree
Locking time 1 4 ms
Xtal buffer output swing 600 mVpp
Xtal buffer output duty cycle 40 50 60 %

Version 0.20 2011/07/18

AV2026
8 Package Dimension
Package: Punch type QFN 4x4x0.9mm, 0.4mm pitch, 28 pins

Version 0.20 2011/07/18

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AV2026 Digital Satellite Tuner

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Page 2 of 17 CONFIDENTIAL

Page 3 of 17 CONFIDENTIAL

Page 4 of 17 CONFIDENTIAL

Page 5 of 17 CONFIDENTIAL

2 1 2 1 T

VCCRF1 2 AIROHA 20 VCCXO

P N F

Page 6 of 17 CONFIDENTIAL

4 Pin Name Description

1 REG2OUT Regulator Output RFVCC Regulator Output

Page 7 of 17 CONFIDENTIAL

5 Block Diagram and Description

5.1 General Description

2 1 2 1 T

REG2OUT 1 Regulator Regulator Regulator 21 VDDD

P N F

Page 8 of 17 CONFIDENTIAL

5.2 Receiver Section

5.3 Synthesizer/VCO/XO Section

5.4 Control Section

Page 9 of 17 CONFIDENTIAL

7-bit Address Read Address

Table 5.1: Read Address

7-bit Address Write Address

Table 5.2: Write Address

Page 10 of 17 CONFIDENTIAL

6 2-wire Serial Interface

TS1 TH1 TLOW THIGH TIR TIF TPS TS3 TBUF

START TIR TH2 TS2 TIF TOF STOP START

SYMBOL PARAMETER MIN TYP MAX UNIT

Page 11 of 17 CONFIDENTIAL

6.2 Read/write Procedures

Single Write Procedure

Sequential Write Procedure

Page 12 of 17 CONFIDENTIAL

7.1 Absolute Maximum Ratings

ITEM MIN. MAX.

Power supply voltage (VCCREG1/2) – 0.3V 5.5V

Storage temperature – 65 C ° +150 C

LNA input level - +10 dBm

*Connect current limit resistor at Digital pin, RFAGC pin.

Page 13 of 17 CONFIDENTIAL

7.2 DC Electrical Specifications

Item Symbol Test Condition Min. Typ. Max. Unit

Power Supply Voltage VCCREG 2.97 3.3 3.63 V

Power Supply Current

Power Supply Current

Digital Input Voltage – High Level VIH 0.7*VCCREG VCCREG+0.3 V

Digital Input Voltage – Low Level VIL - 0.3 0.3*VCCREG V

Interface Output Voltage – High Level VOH IOUT = 500µA 0.8*VCCREG V

Interface Output Voltage – Low Level VOL IOUT = - 500µA 0.2*VCCREG V

Page 14 of 17 CONFIDENTIAL

7.3 AC Electrical Specification

PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Page 15 of 17 CONFIDENTIAL

Page 16 of 17 CONFIDENTIAL