TOA 1221

COMPUTER ORGANIZATION AND

ARCHITECTURE

Lec05

Computer Arithmetic – I
Integers Representation and Arithmetic (Addition and Subtraction)
 Contents

How ALU is interconnected with the rest of the processor?

Representation of integers
Sign-magnitude, ones complement, twos complement,
biased
Sign magnitude representation
Representation, drawbacks
Twos complement representation
Characteristics, examples, advantages, special cases, use of
value-box for conversion, sign extension
Arithmetic with Twos complement numbers -
Addition/Subtraction, geometric depiction, Hardware
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 Arithmetic and logic unit (1)

Computers do not store numbers or letters

Computers store bit sequences

The bit sequences can be interpreted as representing

integers or floating point numbers

Arithmetic can be accomplished by the direct hardware

implementation of the arithmetic algorithms.

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 Arithmetic and logic unit (2)

Does the calculations

Everything else in the computer is there to service this unit

Handles integers

May handle floating point (real) numbers

May be separate FPU (maths co-processor)

May be on chip separate FPU (486DX +)

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 ALU inputs and outputs

Data are presented to ALU in registers and the results of an operation are
stored in registers.
Connected by signal paths to the ALU
ALU may set flags as the result of an operation
Control unit provides signals
for controlling the operation of ALU
Movement of the data into and out of the ALU

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 Integer Representation

Representation of nonnegative integers:

No minus sign/No period for computer storage and processing
Only have 0 & 1 to represent everything
8 bits word could be used to represent the nonnegative numbers from 0 to 255.
Positive numbers stored in binary
e.g. 41=00101001
General - n-bit sequence: an-1 an-2 …..a1a0 is unsigned integer A, then

n-1
A = Σ 2i ai
i=0

Representation of negative integers:

Sign-Magnitude, one’s complement, Two’s complement, Biased

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 Sign-Magnitude Representation (1)
Left most bit is sign bit
0 means positive
1 means negative

Examples:
+24 = 00011000
-24 = 10011000
n-2

A = Σ 2i ai, if an-1 = 0
i=0

General case n-2

A = - Σ 2i ai, if an-1 = 1
i=0

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 Sign Magnitude Representation (2)
- Drawbacks
Sign Magnitude Rep. is rarely used for implementing the integer portion of
ALU
• While performing addition/subtraction of numbers in sign-magnitude representation,
– First Compare the sign of two operands
– If the sign are different, then compare the magnitudes of the operands
– Then perform the subtraction of smaller magnitude number from the larger
magnitude number
– Put the sign of larger magnitude number as the resultant sign.
– Requirement of additional hardware circuitry needed to compare the sign as well as
magnitude.
– Time taken for performing addition/subtraction will also be more.
• Two representations of zero (+0 and -0)
– difficult to test for zero
– always should convert from -0 to +0 .

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 Ones' complement

Value obtained by inverting all the bits in the binary representation of

the number (swapping 0's for 1's and vice-versa).
Only represent integers in the range −(2N−1−1) to 2N−1−1 while two's
complement can express −2N−1 to 2N−1−1.
Addition algorithm:
1. Add two numbers as if they were unsigned integers.
2. If there is a carry out of the sign position, then add that bit to LSB of the
result and propagate the carries as necessary. (end-around carry rule)
3. An overflow occurs if two positive numbers are added and the result is
negative or if two negative numbers are added and the result is positive.
These numbers have not seen widespread use.

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Ones' complement – characteristics

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 Twos Complement Representation
- Characteristics (1)

Range : - (2n-1) through (2n-1) -1

8 bit Twos compliment
Range:
-128 = 10000000 = -27 through
+127 = 01111111 = 27 -1

16 bit Twos compliment

Range:
-32768 = 100000000 00000000 = -215 through
+32767 = 011111111 11111111 = 215 – 1

Number of representations of zero : One (There is no negative zero)

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 Twos Complement Representation
- Characteristics (2)

Negation ( conversion from positive to negative and vice versa)

Procedure 1: Take the Boolean complement of each bit of the

corresponding positive number, then add 1 to the resulting bit pattern

viewed as an unsigned integer.

Procedure 2: Starting from LSB, write the bits as it is up to and

including the first 1. Invert the remaining bits.

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 Twos Complement Representation
- Characteristics (3)

Expansion of Bit length: Add additional bit positions to the left and fill in

with the value of the original sign bit

Overflow Rule: If two numbers with the same sign are added, then

overflow occurs if and only if the result has the opposite sign.

Subtraction Rule: To subtract B from A, take the twos complement of B

and add it to A.

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 Twos Complement Representation
- Examples

Assume 8-bit twos complement representation

+3 = 00000011
+2 = 00000010
+1 = 00000001
+45= 00101101

0 = 00000000
-1 = 11111111
-2 = 11111110
-3 = 11111101
-45 = 11010011

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 Expression for Twos complement representation

Range of positive integers represented = 0 (all the magnitude bits are 0’s)
through (2n-1 ) -1 ( all the magnitude bits are 1’s)
Example: For 8 bit, 00000000 (0) through 01111111 (127 (i.e) ( 27-1))

Range of negative numbers represented = -1 through – (2n-1)

Example: For 8 bit, 11111111 (-1) through 10000000 (-128 (i.e) (- 27 ))

Equation defining the twos complement representation for both positive

and negative numbers

n-2
A = - 2n-1 an-1 + Σ 2i ai
i=0

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 Advantages for using Twos complement
Representation

Only One representation of zero

Arithmetic works easily - No special Hardware required
Negation is fairly easy
3 = 00000011
Boolean complement gives 11111100
Add 1 to LSB 11111101
else
starting from LSB, write the bits as it is up to and including the first 1, find
Ones complement of remaining bits

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 Twos Complement Representation
- Negation Special Case 1

0= 00000000

Bitwise NOT 11111111

Add 1 to LSB +1

Result 1 00000000

Carry out of MSB is ignored, so:

-0=0

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 Twos Complement Representation
-Negation Special Case 2

-128 = 10000000
bitwise NOT 01111111
Add 1 to LSB +1
Result 10000000
So:
-(-128) = -128 X
Monitor MSB (sign bit)
It should change during negation
There is no +128 for 8-bit twos complement representation.

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 Twos Complement Representation
- Negation special case 2 -discussion

Number of different bit patterns in an n-bit word is 2n - even number

Wish to represent positive, negative integers and zero

equal number of positive and negative representation of integers - two

representations for zero (Sign-Magnitude representation )

One representation of zero, unequal number of positive and negative

integers (Twos complement representation - There is a representation for
(- 2n-1 ) but no representation for (+ 2n-1 ))

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 Use of a Value Box for Conversion between
Twos Complement Binary and Decimal (1)

An Eight-position Two’s Complement Value Box

-128 64 32 16 8 4 2 1

Example 1: Convert 8-bit Twos complement binary 10000011 to Decimal

-128 64 32 16 8 4 2 1

1 0 0 0 0 0 1 1
-128 +2 +1

= -128 +2 +1 = -125

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 Use of a Value Box for Conversion between
twos Complement Binary and Decimal (2)

Example 2: Convert Decimal –120 to Twos complement Binary

representation

-120 = -128 + 8

-128 64 32 16 8 4 2 1

-128 +8

1 0 0 0 1 0 0 0

-120 = 10001000

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 Conversion between different bit lengths (1)

Sometimes desirable to take n-bit integer and store in m bits,

m>n

For Sign-Magnitude, move the sign bit to the new left-most

position and fill in with zeros.
+18 = 0001 0010 (Sign Magnitude, 8bits)

+18 = 0000 0000 0001 0010 (Sign Magnitude,16 bits)

-18 = 1001 0010 (Sign Magnitude,8 bits)

-18 = 1000 0000 0001 0010 (Sign Magnitude,16 bits)

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 Conversion between different bit lengths (2)

For Twos complement,

Positive number pack with leading zeros
+18 = 00010010 (Twos complement - 8 bits)
+18 = 00000000 00010010 (Twos complement - 16 bits)

Negative numbers pack with leading ones

-18 = 11101110 (Twos complement-8 bits)
-18 = 11111111 11101110 (Twos complement-16 bits)

i.e. Pack with MSB (Sign bit)

called Sign extension

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 Biased Representation

Uses a pre-specified number K as a biasing value.

K = 2n-1 – 1
A value is represented by the unsigned number which
is K greater than the intended value.
0 is represented by K
−K is represented by the all-zeros bit pattern

Examples 1: Given 4 bits, bias value, K = 23 –1 = 7

TRUE VALUE to be represented = 3
add the bias 3 + 7 = 10
unsigned value +10
Thus, 3 in 4-bit biased representation will be 1010
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 Biased Representation

Examples 2: Given 4 bits, bias value, K = 23 –1 = 7

TRUE VALUE to be represented = -4
add the bias -4 + 7 = 3
unsigned value 3
Thus, -4 in 4-bit biased representation will be 0011

Examples 3: Given 8 bits, bias value, K = 27 –1 = 127

TRUE VALUE to be represented = 10
add the bias 10 + 127 = 137
unsigned value 137
Thus, 10 in 8-bit biased representation will be 10001001

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 Different Representations for 4-bit Integers
Decimal Representation Sign-Magnitude Twos Complement Biased Representation
Representation Representation
+8 — — 1111
+7 0111 0111 1110
+6 0110 0110 1101
+5 0101 0101 1100
+4 0100 0100 1011
+3 0011 0011 1010
+2 0010 0010 1001
+1 0001 0001 1000
+0 0000 0000 0111
–0 1000 — —
–1 1001 1111 0110
–2 1010 1110 0101
–3 1011 1101 0100
–4 1100 1100 0011
–5 1101 1011 0010
–6 1110 1010 0001
–7 1111 1001 0000
–8 — 1000 —

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 Fixed point representation

Representation for integers discussed can be called as fixed point

representation

Called so since the binary point is fixed and assumed to be the right of the right-most

digit

can use the same representation for fractions by scaling the numbers

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 Integer Arithmetic
- Addition and Subtraction

Normal binary addition

Monitor sign bit for overflow

Take twos compliment of subtrahend and add to minuend

i.e. a - b = a + (-b)

So we only need addition and complement circuits

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Addition of Numbers in Twos Complement
Representation
(-7) + (+5) (-4) + (+4)
1001 1100
+0101 +0100
1110 = -2 1 0000 = 0
(+3) + (+4) (-4) + (-1)
0011 1100
+0100 +1111
0111 = 7 1 1011 = -5
(+5) + (+4) (-7) + (-6)
0101 1001
+0100 +1010
1001 = overflow 1 0011 =overflow

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 Condition for overflow

If two numbers are added, and they are both positive or both negative,
then overflow occurs if and only if the results has the opposite sign.

Note that overflow can occur whether or not there is a carry.

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 Detection of overflow

Carry out of sign bit and carry into the sign bit will be given as two inputs

to the exclusive-OR gate and the output of exclusive-OR gate is connected

to overflow flip-flop.

If carry out of sign bit and carry into sign bit are equal - NO overflow

If carry out of sign bit and carry into sign bit are not equal - OVERFLOW

occurs

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 Subtraction of Numbers in Twos Complement
Representation

To subtract one number (subtrahend) from another (minuend), take the twos

complement of the subtrahend and add it to the minuend.

Thus, subtraction is achieved using addition. The last two examples

demonstrate that the overflow rule still applies

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Subtraction of Numbers in 2’s Complement
Representation (M-S = M+(-S))
0010 0101
+1001 +1110
1011 = -5 1 0011 = 3
M = 2 = 0010 M = 5 = 0101
S = 7 = 0111 S = 2 = 0010
-S = 1001 -S = 1110
1011 0101
+1110 +0010
1 1001 = -7 0111 = 7
M = -5 = 1011 M = 5 = 0101
S = 2 = 0010 S = -2 = 1110
-S = 1110 -S = 0010
0111 1010
+0111 +1100
1110 = overflow 1 0110 = overflow
M = 7 = 0111 M = -6 = 1010
S = -7 = 1001 S = 4 = 0100
-S = 0111 -S = 1100 33
Geometric Depiction of Twos
Complement Integers (1)…

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 Geometric Depiction of Twos
Complement Integers (2)

Starting at any number on the circle, we can add positive k

(or subtract negative k) to that number by moving k
positions clockwise

Starting at any number on the circle, we can subtract

positive k ( or add negative k) from that number by
moving k positions counterclockwise

If an arithmetic operation results in traversal of the point

where the endpoints are joined, an incorrect answer is
given (Overflow)

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Hardware for Addition and Subtraction (1)

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 Hardware for Addition and Subtraction (2)

For binary addition, the two numbers are presented to the adder from
two registers, designated as A and B.
The result may be stored in one of these registers or in a third register.
The overflow indication is stored in a 1-bit overflow flag
0 indicates no overflow while 1 indicates overflow

For binary subtraction, the subtrahend in B register is passed through a

twos complementer circuit
A register contents and Twos complement of B register contents
are fed to the adder

Control signals are used to control whether or not the complementer is

used, depending on whether the operation is addition or subtraction.

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 Problem (1)

Find the following differences using twos complement

arithmetic:

a. 111000 - 110011

b. 11001100 - 101110

c. 111100001111 - 110011110011

d. 11000011 - 11101000

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 Problem (2)

Assume the following numbers are represented in 8-bit twos

complement representation. Perform the following arithmetic.

Check whether there is an overflow.

a. (85)+(65)

b. (-75)+(67)

c. (127) – (45)

d. (-128) – (-100)

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 Problem (3)

What is the range of numbers that can be represented in 8 bit and 16 bit

ones complement numbers

Perform addition/subtraction of 8 bit numbers using 1’s complement

representation using different examples given below:

a. (6) + (13) b. (-6) - (13)

c. (-94) + (65) d. (120) – (89)

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 Problem(4)

Consider the following operation on a binary word. Start with the least significant

bit, copy all bits that are 0 until the first 1 bit is reached and copy that bit , too.

Then take the complement of each bit thereafter. What is the result?

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 Reference

Slides adopted from the book

William Stallings, “Computer Organization and

Architecture: Designing for Performance”,
8/E, Prentice Hall, 2010.
(ISBN-10: 0135064171, ISBN-13: 9780135064177)

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