Interview questions

Company1 : Intel :- 22/3/2021 to 26/3/2021

1 a) Analytical questions on mosfet, it's operations under interviewer specific

conditions, graph, biasing.
b)3:8 decoder using nand gate
c) python file operation (basics)
d)personal questions-daily routine

2. a) Introduce yourself.
b) Tell me about your project and ask questions based on the project (what u have
done, what is the result u see, questions on verilog code( bcoz my project is based
on verilog), how many bytes in 32bits,...etc.).
c) Latch is a combinational or sequential circuit?
d) Differentiate between latch and flip flop?
e) why latch is level triggered?
f) what is setup time and clock skew?

3)
1. Details about project and implementation
2. Verilog code for Flip flop with asynchronous reset
3. Question about verilog operators
4. FSM question
5. Aptitude question

5.
1. introduce yourself.
2. Explain your project.
3. digital basic
a. latch,Flipflop,register,fsm(important).
 b. Draw encoder,mux,4:1 mux to 2:1 mux(code)
c. priority encoder
4. verilog question
a) FSM question.
b) coding style
c) if vs case
d) Fifo vs ram(list ports)
e) Encoder,priority encoder.
f) Blocking and non-blocking
5.STA (slack,setup,hold,skew)
6.fpga based
7.CDC
8.some question :debugging error in code.
9.logical reasoning questions.
10.Asynchronous and Synchronous Reset in FF.
All the best.

Interview 6:
1) Tell me about yourself.
[Note: He said to visualize everything, nothing is written in paint or
written on the paper for explanation purposes.]
2) What are the universal gates and why are they called universal gates?
3) Some Combinational Circuits using universal gates. Had to explain the
normal steps.
4) Which universal gate is better and why?
5) Why do we need sequential circuits?
6) Asynchronous and Synchronous Reset in FF.
7) Explain above Q in Verilog context. For Synchronous reset what circuit will
infer.
8) Continuing the same Q if different input vectors are passed to FF then how
can we minimize this reset circuit.(circuit which i had explained to him in
prev Q)
 9) He gave some extra conditions on FF and How can i see the expected result
with the help of testbench.( Had to explain in Form of transcript window for
eg. at t=0 d=1 rst=0 clk=1 q=1 etc..)
10) Timing Criticality in FF. (Setup and Hold Time explanation)
11) Blocking and Non blocking assignment with the example.
12) Is it okay if i use Blocking for Combinational and Nonblocking for
sequential and why?
13) What is a sensitivity list?
14) Based on Above Concept asked some particular Q’s gave different
conditions in the sensitivity list.

15) Asked me to explain some of the work I have done in perl.

16) Asked me to explain About one of my projects in detail.
17) Some Personal Q like Family information etc. and Career Motivation.

Interview 7:
1.Introduce yourself and tell about ur btech nd mtech projects.
2.What are the subjects you have in current semester?
3.Tell me Asic Design Flow?
4.What are the check-ins we do in GDSII?
5. Explain setup and hold time violations, how to overcome them?
Explain it using time instants.
6.Questions based on my projects?
7.Explain MOSFET. How can threshold voltage be reduced?
8.Basic question on Networks
9. Nmos pmos given vgs vts given what will be output voltage
10.logic for swapping values of two variables w/o using 3rd variable(without using
verilog, Perl or tcl)
11. Logic for Fibonacci series

Interview 8 : Phone Interview

1. Tell about yourself
2. Difference between latch and flip flop.
Ans:
3. What is time borrowing? (since I told latch can be used in time borrowing
technique)
Time borrowing is the property of a latch by virtue of which a path ending at a
latch can borrow time from the next path in pipeline such that the overall time of
the two paths remains the same. The time borrowed by the latch from next stage in
pipeline is, then, subtracted from the next path's time. To understand even better→
https://www.physicaldesign4u.com/2020/05/time-borrowing-concept-in-
sta.html

https://www.youtube.com/watch?v=mrY0MzCBgAo
Above video watch from 31.00 mins
 https://www.youtube.com/watch?v=uiBuEKZxIxA

4. Which application do you use?

For faster logics latch based design is helpful, there for meeting time latch
Borrowing technique is useful, for detail understanding go through above
links.

5. Blocking and non blocking

 For more understanding : Better to watch these lectures for crystal clear
understanding
https://www.youtube.com/watch?v=QUwRRafjVvc
https://www.youtube.com/watch?v=JMxEZIIsNnM
https://www.youtube.com/watch?v=hsASVmlqvsg
https://www.youtube.com/watch?v=kHDPW_VdPZw

6. Different types of delays

I said to Inter assignment and intra assignment delay only to stick the
interviewer not to go other subjects although there are many types of delays
are there for eg. Rise delay, Fall Delay, Wire Delay , Gate Delay, Net Delay,
Cell Delay, Combinational path delay, clock-q delay, parasitic delay,
7. Difference between Inter assignment delay and Intra assignment delay?

8. Why do we need both Inter assignment and intra assignment delays? Explain
exactly why they are?
For this question you need to understand the above all delays properly and
relate them with various types of delays in real cases . To simulate and see
the results caused by these various types of delays we use those two
different types of delay assignments.

9. Two blocks are there A and B both will transfer data to each other which one
you use wire or reg or any other?
 Testing of basic data types in verilog. Net data type and Reg data type. I
answered We need to use a back to back connection of Active High and
Active low, a tri-state buffer.
10. 8 x1 mux using 2 x 1 how many 2 x 1 required ?
7
11.56 x 1 mux using 2 x1 how many 2 x 1 required?
We requires 56 → check this
[ Final Suggestion : Learn application oriented like whatever we are
learning, actually where you're going to use it and why you are using that?]

Interview 9:Phone interview

1.Tell me about yourself
2.Detailed explanation about projects.
3.Few questions regarding application of project.
4.Some basic concepts like what are digital and analog signals
5.How would you describe the RTL flow to a layman.(had to specify the
Frontend flow and how circuit is working at various abstraction
levels,starting from behavioral to layout).
6.He discussed about post Si validation at Intel graphics unit, like how do
we analyse chips after it comes from fab(had to specify GPU’s , emulators).

Interview 10:

1) Tell me about yourself

2) Difference between asynchronous and synchronous circuit
3) Difference between combinational and sequential circuits
4) Difference between logical and case inequality
5) Blocking and non blocking statement
6) How to design and , not ,nand using mux
7) How to design a circuit with input signal frequency f and output signal
frequency f/2
8) Difference between latch and flip flop , task and function
 9) Project related question
10) Hold time , set uptime
11) Difference between encoder and priority encoder

Interview 11:
1. Introduce yourself.
2. Difference between simulation and synthesis?

3. What is difference between synchronous and asynchronous circuit?

Whis is faster?Applications of it.
4. What is set up time and hold time?
5. Given one circuit having two ff with combinational circuit between
them, Tcq=1ns , Tpd=2ns , Tsetup=1ns , Thold=1ns what is minimum
time period to met constraint? Again one buffer inserted for clock
which is going to second ff giving 1ns of skew, what will happen to
time period?
 6. As insertion of skew is increasing frequency, can you increase it till
any extent?Is there any limit?
7. What will be change in hold time after changing the time period of
clock?
8. What is meaning of DFT?
9. What is motivation to work in Intel?

Interview:12

1. Introduce yourself.
2. Basics of Inverter and what will be the output if PMOS and NMOS are
interchanged and also effect on result.
3. Difference between Latch and FF and how positive edge triggered FF works
and design.
4. Low power concept(switching,leakage,short circuit).
5. Timing.
6. Issues in different logic style and how to remove that.
7. Why keeper circuit is used in domino logic style.
8. Way to reduce output falling and rising time.
9. Design of FF and Latch using MUX.
10.Loading effect.
11.Logical effort.

Interview -13:
1. Introduce yourself.
 2. Tell about your project.Industrial application and other questions
related to project. Your contribution in the project. Explain how the
code was done briefly.
3. Asked how test vectors have been applied for the project. System
tasks related question.
4. Asked about the skills mentioned in resume.
5. Why perl and tcl is required in VLSI?
6. File handling related questions like how to generate testbench.
7. How to invoke modelsim and do simulation through perl script.
8. I was asked to explain the system commands for above codes. Refer
scripting da’s .
9. Asked about cdc and fifo.
10.Verilog basic questions.
11.What certifications i have done and what did i learn from each of
them.
12. Try to relate the answers with applications related to industry.
Interview -14
1. First he explained about his department .
2. Tell me about the project(30-40min,cross questions). Its application ,how
did you analyse whether you got correct outputs or not.
3. Some questions about Industrial training.
4. Setup and hold violations.
5. Stability and observability
Interview -15
1. Tell me about urself and explain the btech project
2. ASIC design flow
3. Mtech project
4. DFT struck at faults how to find them .
5. And gate input struck at 0 which input pattern will detect fault and struck at
1
6. Design for testability will it add another logic to circuit or existing
7. Scan mode normal mode inputs to a multiplexer and what will happen based
on select lines
8. Fibonacci series logic
9. Ascending order logic
 10.CMOS basic theory
11.Nmos region of operations with equations
12.Basic electronics active and passive elements

Interview -16.
1. Explain the mtech projects.
2. Explain the working of nmosfet and region of operation .
3. Asked commands in python and TCL.
4. Linux commands in depth.

Interview -17
1.Tell me about strengths and weaknesses..
2.Questions based on inverter circuit..more of analytical kind.
2a. If you connect one more PMOS parallel to the PMOs in inverter what would
be the effect
3.Aptitude question.

4.If you have done an assignment and given it to your friends and all of them
copied it and submitted.Teacher found that everyone has copied and she/he caught
you?What would be your response?
5.Say something about a situation of conflict in your college life.If you are
supposed to do a project with a person you dont like personally what will you do?
6.What are setup and hold time?
7.why do we need them?
8.Given a circuit asked to derive setup and hold conditions.
9.How can you make a edge triggered filpflop.
10.What all logic types you know apart from CMOS.
11.What are the different types of oscillators.

12.If the characteristics is like in the red colour then what defect does the
circuit have?
13.Difference between PERL and python
14.If you have any questions you can ask..

Interview 18:
1. Give a brief introduction of yourself.
2. What is setup and hold time?
3. What is difference between latch and flip flop
4. Diff between asynchronous and synchronous reset?
5. What is sensitivity list?
6. Difference between synchronous and asynchronous circuits and
examples.
7. Difference between a=#5 b and #5 a=b ?
8. Difference between a==b and a===b?
9. Output for various input combinations of jk and sr flipflop
10.What is a buffer?
11.What is blocking an non blocking statements?
12. Difference between task and function?
 13.What is a mux?
14.What are universal gates? Why is Xor not a universal gate?
15.Difference between synthesizable and non synthesizable code? Give
examples.
16.What is glitch?
17.What is forever loop?

1. What is FSM.
2. Why we use POS and SOP ?
3.

4. Characteristics of inverter for various types of input waveforms ?

5. How output will change in inverter. What is diagram for waveform?
6. 3D structure of MOSFET ? (will ask regarding doping depletion etc layers) ?
7. Which is faster NMOS or PMOS. How will u decide which is faster. Plz
explain
8. Types of Power in inverter.
9. Verilog code for asynchronous reset.
10.He gave a circuit and asked different faults (Stuck at faults) and asked what
test vectors you will give for checking the operation of the vectors ?
11.What is mod10 counter Its code in verilog.
12.Implement the OR gate using NAND gates.
13.Why are NAND and NOR are universal GATES.
14.What is setup and hold time ?
15.What is your project ?
16.Verilog code of mod10 counter ?
 17.Difference between block and nonblock statement ?
18.What is STA ?
19.Explain in detail ? Is it new or What is optimization u have done in existing
one ? Explain how it is better then the existing circuits.

Interview 18.
Introduce yourself.
About project
Asic flow
Question on produceral blok
What is metastability. How it affect the system
About Mosfet working
Tell me about ur weakness and Some general question
……………………………………………………………...
INTERVIEW 19
1.Introduce yourself & strength and weakness
2.Tell me abt ur project. (said low power design implemented in prjt)
3.how can u reduce power consumption (said vdd reduction, etc)
4.if vdd must be constant to particular rail how can u reduce (said power gating)
5.what is power gating
7.what is clock gating
8.types of power dissipation
9.if used power gating technique which power will be reduced
10.have u written any verilog code (i said simulated & synthesized in IQP)
11.What is synthesis
12.will setup and hold time come in synthesis
13.how to overcome setup violations
14.different paths in STA
15.how can u reduce area of soc
16.do u know about fabrication
………………………………………………………………………..

Interview -20

1. Introduction
 2. Define your projects then after she asking ques from projects

3. Explains what you learns when u was go for industrial visit

4. Question on basic of computer architecture

5. Strength and weakness

6. Why do you want to work at intel

7. Which domain would u like and why

8. Question related to memory

9. How quaternary is different from normal logic gate

10. How good are you in Verilog and C

11. Have u any question from my side

………………………………………………………………….

Interview 21

1. Tell me about yourself

2. What subjects do you like

3. What is an oscillator?

4. What are the types of oscillators you know?

5. How will you design full adder?

6. How will you design half adder?

7. What do you know about DSP?

8. Que based on my b.tech and m.tech projects?

9. What is a diode?

10. Any question do you want to ask?

 Interview 22:

1.Introduce yourself

2.Tell me about your project.

3.What will happen if W/L ratio will increase.

4.What is ratioless logic?

5.What is example of ratioed logic?

6.Draw the diagram of frequency divider?

7.What is meant by edge triggered circuit?

8.Draw the circuit of edge trigger?

9.Write the verilog code for aynchronous reset?

10.How functionality will change if we increase the W/L ratio of inverter?

11.Define set up and hold time

12.Numerical on Timing ,asked to calculate frequency.

13.What is antenna radiation?

14.What is crosstalk?

15.Draw the structure of Whitestone Bridge?

16.Why we use posedge and negedge?

17.Tell the ASIC flow

18.What is difference between previous and after design formal verification?

19.Tell me about power consumption in CMOS ?

20.Where is diode present in CMOS?

21.Tell the OOPS concept

22.Write the equation for total Time?

23.Write the equation for hold Time?

24.If we give the one input to the inverter ,how we will make it to 0.5?

25.How many terminals does MOSFET have?

Interview 23

1. General question about college curriculum, what subjects have been taught.
2. Which technology nodes have you worked with?
3. What does a technology node represent?
4. What does W/L mean for a transistor
5. Draw Inverter and NAND gate
6. Size them properly(NMOS of inverter = 1um)
7. Propagation and transition delay in CMOS circuits.
8. For NAND gate, which NMOS in the pull down circuit should have large
sizing?
9. Different Capacitors present in CMOS NAND circuit
10.Path taken for charging and discharging different capacitors
11. How much you will rate yourself in Python?
12. How do we implement Place and Route in Synopsys?

Interview 24

1) Explain about yourself and your field of interest in VLSI Domain.

2) Shared me a Verilog code and asked to explain each and every line.
3) What is module instantiation and what happens if the same module is
instantiated multiple times with the same name.
4) Explain synthesis of Verilog code and what exactly happens during
synthesis. What all are the inputs required for synthesis.
5) Relevance of input and output delay in synthesis.
6) Shared a diagram having power, area and speed as the axis, asked to explain
the diagram with current design trends and tradeoffs required.
 7) Basics of CMOS with explanation about sizing of gates and how it
corresponds to both power, area and speed.
8) How leakage power can be reduced using multi-Vt cells.
9) What is signal transition (clock or any other signal) and explain different
types of delays.
10) In-depth explanation about STA (setup, hold, skew etc.) and how the
violations can be mitigated. Also given a small problem to find if any setup
violation occurs.
11) How asynchronous flip flop can be realized, Explain the difference
between latch and flip flop with diagram.
12) Questions related to basic gates and universal gates and asked to
realize basic gates from universal gates.
13) Given an expression and asked to realize using mux.
14) A sequence was given and asked to draw a state transition diagram
for the same sequence detector.

Interview 25

1) Explain to me any one of your mtech projects.

2) Explain any one of your btech projects.
3) In which technology node did you work on for your projects?
4) Explain various reasons for the operation of a MOSFET. Gave on biasing
conditions and asked for which region the MOSFET is in now.
5) What are the advantages of CMOS technology?
6) What are second order effects.Asked to explain DIBL and Body Effect out
of which i have told.
7) Asked to implement nor gate using 2:1 MUX.
8) What are the differences between LATCH and FLOP.
9) Implement LATCH using 2:1 mux, and then using the same convert this to
FLOP.
10) What is the advantage, one of LATCH and one of FLOP, discussed
about metastability .
11) STA problem, gave all the parameters and asked to find out Tclk, and
then violated hold condition and again asked to calculate Tclk, with new
hold condition.
12) Asked backend questions, what is metal resistance and capacitance
and what are methodologies to reduce them.
13) How many metal layers we have on silicon and what are its purpose.
14) Static and Dynamic power, what are ways in which we can reduce
dynamic power.
 15) What is antenna effect, crosstalk, IR, OCV, LVS and ways to reduce
them.

INTERVIEW 26 (Panel: Abha Gupta)

1) Tell me about yourself ?

2) What are your areas of interest ?

3) Why analog circuits are prone to noise and digital circuits are less
prone to noise ?

4) When you are designing any particular MOSFET (NMOS or PMOS)

which design parameters you will take into considerations ?

5) What is MOSFET ? and What is CMOS ?

6) Draw the schematic of any particular MOSFET (NMOS or PMOS),

Draw its equivalent cross-section and explain the regions in detail.

7) How can we get the resistor and capacitor from the MOS Device ?

8) Why IDsat called as Saturation current ?

9) How can we make the MOSFET as a switch? Why MOSFET can’t give us
an ideal switch characteristics ?

10)What is the direct current path for circuits?

11) Draw a schematic of NAND circuit and its layout diagram?

12) How we can differentiate the Latch and Flops? Explain it using the
diagram.

13) Draw the D-Flip Flop and also give its implementation circuit using
the basic gates. Explain the working on basis of this basic gate diagram.

14) How can you make level sensitive clock to edge sensitive clock?

(Don’t use any R-C circuit).

15) How can you met the frequency for the block which contain the two
D-Flops and Combo logic which is placed in between two flops so that
data from Flop1 to Flop2 can pass efficiently.
16) What happen when there is a delay between clocks ? 15th

17) What is setup and hold?

18) what is the condition to meet hold time?

19) Why we can’t change the hold condition after the silicon is taped out?

20) Give the timing constraint if the clock skew present in the design ?

Interview 27

1. Tell me about yourself ?

2.Question based on inter and intra assignment delay

3.difference between $display,$monitor,$define

4. difference between task and function

5.concept of pointer in c language and its code

6.how you decide clock frequency

7.question based on STA, System verilog

8.Asked to implement and,xor gate using 2:1 MUX.

9.some question on power,speed ,area why there is trade off between them .

INTERVIEW 28

1.Tell me about yourself

2.explain one of the projects in your resume

3difference between task and function

4.draw the xor gate using cmos logic

5. Difference between blocking and nonblocking with some statements

6.pointers and with program

Interview 28

1.basic of sequential circuits.

2.write a verilog code for d_latch.

3.write a verilog codefor normal dff.

4.use dff (if en is there dout<=din)(en is not there its hold previous valu).write
verilog code and circuit diagram.

5.write a verilog code for right shift and left shift depends on sel input.

6.dff working ,truthtable.

7.difference b/w asic and fpga.

8.in dff use only if latch is infer r not?

9.difference between latch and ff.

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Interview 29

Intel:
1. Was asked about the work location
2. Introduce yourself
3. Was asked whether you are good at digital electronics
4. Say about multiplexer
5. Asked to design a logic level circuit to find leap year or not
6. Questions on STA
7. Asked about setup and hold time with example
8. Asked about its violation in circuit
9. Why cmos or mos are preferred
10. Say about the chip design flow
11. What is DFT
12. Methods you know in DFT
 13. Explain about your favorite project that you have done

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Interview 30

INTEL
1.Introduce yourself and tell about ur btech nd mtech projects.
2.What are the subjects you have in current semester?
3.Tell me Asic Design Flow?
4.What are the check ins we do in GDSII?
5. Explain setup and hold time violations, how to overcome them?
Explain it using time instants.
6.Questions based on my projects?
7.Explain MOSFET. How threshold voltage can be reduced?
8.Basic question on Networks
9. Nmos pmos given vgs vts given what will be output voltage
10.logic for swapping values of two variables w/o using 3rd variable(without
using verilog, Perl or tcl)
11. Logic for Fibonacci series

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Interview 31

Intel :
1st interview:
1. Introduce yourself
2. Difference between c and c++
3. Define object oriented programming
4. Features of oops
5. Inheritance and polymorphism
6. Projects and practical challenges faced while doing them
7. Pure virtual function
8. Friend function
9. Function overloading
10. Operator overloading

2nd interview:
1. Introduction
2. Draw the CMOS inverter fabrication diagram (with p-well and n-well) and
make connections accordingly.
3. Denote the parasitics in the above diagram
4. Explain CMOS inverter. What is it's significance
5. Effect when Width(W) and length(L) are changed in CMOS inverter
6. Explain a few points about placement and routing in PD
7. Write a structural verilog code of full adder using half adder as leaf cell.
Write the testbench for the same.
8. Write the d flip-flop verilog code with synchronous reset.
9. Setup and hold times and their violations
10. Different timing paths that are possible in digital ICs
11. Write the setup and hold timing equations
12. Denote the timing arcs in the circuit with a launch flip-flop and a capture
flip-flop.

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Interview 32

Intel round 1:
1. Give a brief introduction in 2 min?

2. What are the power components involved in CMOS inverter or any CMOS
circuit?
 3. When the circuit is not switching where the power going (how its
dissipating)?

4. Where does the static power consumption happen saturation or linear mode
of operation?

5. The leakage current flows from where to where (G, S, D)??

6. What happens if gate is thick and thin regarding leakage and power?

7. Explain Latch and flop? Basic difference between both, which is more
flexible to work?

8. If I give 1amp current through a resistor what is the output current, what is
the law involved there?

9. What is the output if I give a ramp signal to a capacitor? What will the
capacitor do? What is the time constant?

10. Can you explain the inductor how it reacts (working principle)? How does it
work for DC?

11. What automation scripts have you written?

12. What is a hash array and how is it different from a regular array?

13. Do you mean both the arrays are the same?

14. Where have you used tcl?

15. What are tools you have used for digital ic design, other tools?

16.What does Synopsys vcs tool will do?

17.What does a dc compiler do?

18.What is synthesis?

19.What is a wire load model and what does it contain about?

20. Do you have any questions for me??

Intel round 2:
1. Give a brief intro about yourself?

2. About gate rank and passing year normal discussion?

3. What is your set project or interesting project u have done in VIT?

4. How you have obtained specific knowledge on project, what steps you have
followed?

5. What is the output you have got, with what you have compared and how do
u come to a conclusion that you have achieved the advantage?

6. Do you know what are the low power techniques used in the design?

7. What courses do you have in the first semester?

8. What is the usage of proc in tcl?

9. Have you learnt about timing, setup, hold, why we do timing?

10. Are you familiar with SDC?

11.What are the constraints available in SDC?

12.To analyze the timing what is the basic constraint required?

13.Basic constraints of setup and hold?

14. Timing exceptions like false, multi cycle path?

15. If there are two designs one is running at higher frequency and other at
lower frequency in both designs where the setup and hold?

16. Equations for setup and hold?

17. Why is CMOS a better transistor, why not BJT, others? How do you explain
that?

18. Second order effects of CMOS?

19.What do you mean by 180nm, 120nm 360nm?

20.Is it good if we go high or lower technologies? (which is better 360nm 0r

540nm)
 21. How lower technology nodes are better in terms of speed?

22.Are you good at regular expressions? Some ques on regular expression to

match a string?

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Interview 33

Intel:
1. Tell me about yourself and projects?
2. What if we miss one input variable in always sensitivity list wrt
inferring hardware logic?
3. Draw a 3 bit shift register and name the flops and conditions for tpd
and hold of first two flip flops, and fmax of the ckt?
4. Asked about area of interest?
5. Brief your M.tech project?
6. Asked about work location?
7. Vit process for mtech seat?
8. Torch and bridge puzzle with 4 members and two scenarios for the
total time taken to cross the bridge if they have only one torch?
9. Define positive and negative skew ? how it affects setup and hold in
both positive and negative skews?
10. Cube which have resistance at all edges of resistance 1 ohm , find
the equivalent resistance wrt diagonals?

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Interview 34

Intel:
1. Give a brief intro about yourself?
2.Area of interest
3.Brief your M.tech project (last sem and current sem). Qstns related to projects.
(B.Tech project also)
What do you mean by 180nm, 90nm 45nm?difference
(physical design/synthesis)
4.Standard cells
5.Delay of standard cell
6.What are timing arc
7.list of arcs we see in a .lib
8.Factors that affect cell delay?
9.Isolation cell,level shifters
10.Skew,metastability,clock uncertainty
11.difference between positive and negative skew.
12.Positive Skew helps setup or hold violations ?
13.Why is setup frequency dependent?
14..What are the constraints available in SDC
15.Hash and array
16.tcl:list, array and associative array difference
17.set b "one two three"
set a "x"
set clk(clk1) 40
a , b , clk : string, list, array
18.linux command : sort based on 2nd field
print 2nd column of a file
19.Power dissipation,static power,dynamic power,switching related qstns
20. Do you have any questions for me?

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Interview 35

Intel:

1. Introduction
2. Asked questions about work done in previous job.
3. Asked to explain about 2 projects (from resume) in detail and asked how it
could have been done better
4. Difference between synchronous and asynchronous resets (in terms of how
the structure of the circuit)
5. Asked to cite some power reduction techniques in flip-flops
6. Why does metastability happen when timing violation occurs?
7. What is clock jitter and why does it occur?
8. How to choose between Mealy and Moore FSM for an application?
9. Asked Domain preference
10. Asked about hobbies

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Interview 36

Intel:
Round1
1.Intoduction.
2.Overview of resume.
3.On which FPGA have you implemented your projects?
4.Setup and hold time definition. How have you done timing analysis in your
project?
5.For a combinational circuit do setup and hold time exist? If yes explain
with example.
6.What have you done in power analysis? Procedure followed for power
analysis.
7.What is static and dynamic power dissipation?
8.How did you verify your project?
9.Difficulties faced during the project.
10.Is pass transistor and transmission gate logic better than CMOS logic?
11.Brief discussion on BE project.
12.Basic questions on DFT, types of faults and simulation techniques.
13.What do you mean by synthesis of design?
14.Files required for synthesizing the design.
15.What is a standard cell?
16.Any other areas of interest which are not covered in your resume?
Round2
1.Introduction, project overview. Details of SET project implementation and
the difficulties encountered.Clock frequency for the implemented project?
2.Draw block level diagram of 4bit counter.(Write a verilog code for it)
3.Draw a 2 bit adder at gate level. Convert this adder into a 2bit counter.
4.Given a lookup table, if the output of this table is feedback to input but by
inverting it what will be the output? Draw output waveform for this condition
5.Can the output of a combinational circuit which looks similar to a clock
signal be used as a clock signal for a sequential circuit?
6.Do you have any questions for me?

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Interview 37

INTEL

1) Can you introduce yourself?

2) What are your areas of interest?
3) Why digital is preferred over analog?
4) Do you know combinational circuits? Can you design?
5) Draw truth table and logic diagram of full adder circuit. (in paint)
6) Gave truth table and asked to draw logic diagram. (in paint)
7) Do you know verilog coding? Are you good in verilog?
8) Can you write a verilog code for Electronic Voting Machine (EVM)?
Gave specifications and asked to write a code in paint using text box.
9) Explained the job profile and asked if i am interested in? And if i have
any questions?
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Interview 38

INTEL

1)Introduce yourself
2)Tell about ur btech and mtech projects and overview of the resume
3)Area of Interest
4)Asic Design Flow?
5)draw all the logic gates using mux
6)Why RTL coding is done?
7)Explain how would you design an EVM Machine
8)Write the program for an EVM Machine
9)Asked to explain the significance of each line of the code i wrote
10)Questions on Verilog (sensitivity list ,synchronous and asynchronous
reset,parameter and define diff)
11)Why did you choose VLSI?
12)What do you expect to take from the internship
13)Explained the job profile .And if i have any questions?

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Interview 39

Intel
1. Tell me about yourself.
2. Why did you choose VLSI in particular?
3. Explain ASIC design flow as simple as possible and name inputs and
outputs at each stage.
4. What is Design Verification?
5. What’s your interest in design flow (either frontend or backend)
6. Why backend?
7. Explain Floorplanning, placement,CTS?
8. Write verilog code for D-ff (synchronous).
9. What is the difference between sequential and combinational logic
circuits?
10. What is the difference between latch and flip flop, which one is
faster?
11. Why do we need a clk in the design?
12. What is the purpose of using a reset signal in designs?
13. Explain the RLC effects on the nets. (draw two back to back
connected inverters and explain).
14. What are the different types of coupling capacitors involved?
 15. Why do we consider/not consider the effects of inductance?
16. What is crosstalk?
17. How to reduce crosstalk?
18. What is latchup in CMOS devices?
19. Among NAND and NOR, which one is preferred and why?
20. What would happen if i connect 10 NAND gates together one
after the other and what would be the difference if i replace them with
the NOR gates?
21. What is pulse width modulation?
22. What is minimum pulse width and what is the effect of using
NAND or NOR gates connected one after another on the minimum
pulse width.
23. What is setup, hold time.
24. What is the sampling window?
25. What are the different types of power dissipation in CMOS
devices?
26. What is Leakage power and how to reduce it. Explain at least two
methods to reduce it.
27. How would you reduce the dynamic power consumption.
28. What is body effect/back gate effect and how does it affect the
threshold voltage of the device.
29. Explain the tradeoff between Vth and Leakage current.
30. Explain subthreshold conduction.
31. A brief discussion on job switch, academics and interests.
32. Discussion on M.tech project.
33. What is the tradeoff that you observed in your project.
34. What is PPA tradeoff (power performance and Area).
35. Was there any other way to optimize the parameters other than
what you tried doing.
36. Explain about the B.tech project. (Use pictures/slides if there’re
any to explain).

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Interview 40

INTEL :
Round 1:
1. What are Universal gates
2. Implement and, or, inverter using nand
3. 2*1 and 4*1 mux using nand
4. Basic definitions of mux and other logic devices
5. Blocking, non-blocking statements examples with timing diagrams
6. Intra assignment and inter assignment delays with a example question
7. Scheduling semantics of verilog
8. Inverter using mux
9. Synchronous and async resets definitions
10. Verilog codes for all resets
11. Perl testbench simulation code
12. Rise time & fall time
13. What is Setup time and hold time, what happens to data when it
doesn’t reach on time?
14. What’s the impact of violation
15. What is Metastability
16. All M.Tech Projects and how did u achieve the outputs
Round 2:
1. Intro
2. Projects - tools, versions, vendors
3. Areas of interest & why
4. What do u know about verification
5. Difference between verification and synthesis
6. What are steps after synthesis
7. Pre layout STA and post layout STA
8. What is Physical synthesis
9. Difference between Physical and Logical synthesis
10. Current projects in this sem
11. Some hr questions
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Interview 41

INTEL
1.explain about ur projects
2.what are logic gates?
3.what are universal gates and why?
4.what is mux?
5.what is microprocessor?
6.types of microprocessor?
7.What is program counter?
8.What are the registers in 8086 microprocessor?
9.what are address anbd data lines

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Interview 42

INTEL
1.Intro
2.Projects-Tools,
3.Leakage currents techniques
4.Vlsi design flow
5.C programming-heap,stack
6.Explain Global, local,static, automatic variables
7.Verification, Testing difference
8.Testing environment
9.Inverter basics
10.memory classification

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Interview 43

Intel
1) Explain about your project (All mtech projects) ?

2) What is the difference between latch and flipflop ?

3) What is bit toggling , how it is avoided ?

4) what is asynchronous and synchronous sequential circuits ?

 5) Explain Nmos ?

6) What are Second order effects in mosfet , explain any 2 ?

7) What are setup and hold time ? one problem on STA.

8) What is cross talk ?

9) Types of power dissipation in the circuits , explain them ? How will you reduce the

Dynamic power dissipation ?

10) Difference between blocking and non blocking assignments ?

11) write a Parameterized verilog code for 2 to 1 mux code using gate level , data flow ?

12) what is synthesizable and non synthesizable coding style ?

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Interview 44

INTEL

1.explain about ur projects

2.what are logic gates?
3.what are universal gates and why?
4.what is mux?
5.what is microprocessor?
6.types of microprocessor?
7.What is program counter?
8.What are the registers in 8086 microprocessor?
9.what are address and data lines in 8086 microprocessor?
10.What is the difference between 32 bit and 64 bit processor?
11.what is the difference between linux and window os?
12.swap 2 numbers -logic?
13. Sorting an array of numbers -logic?
14.Reversing an array -logic?
15.What is a sequential circuit?
16.If there are 7 consonants and 4 vowels, what is the number of words that
can be formed using 3 consonants and 2 vowels?
17.Tell me ur experience in teamwork?
18. Describe urself?

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Interview 45

INTEL:
1.Tell me about yourself
2.can u briefly explain the difference between ASIC and FPGA,explain the
ASIC flow in detail
3.can u briefly explain the FPGA and components present in it,How actually
the FPGA works
4.write a verilog code for D-flip flop with enable input,draw the circuit
diagram
5.some tricky questions on latches and flip flops
6.explain the working of mosfet
7.why we use mosfets instead of bjt
8.explain cmos inverter and draw transfer characteristics
9.what is clock gating and power gating
10.whats is f.s.m and explain mealy,moore fsm
11.what is glitch and why it is occured
12.difference between synchronous and asynchronous reset

Interview 46

Intel (Telephonic)
 1. Introduce yourself
2. Questions on device side, CMOS inverter basics, how to improve rise
time?
3. Timing concept related to setup and hold time: how to improve,
how frequency affects the setup and hold time, what if setup time
is violated in part of circuit, should we discard it or we can improve
with the varying frequency.
4. In CMOS inverter if we interchange nmos and pmos it will give
output if yes how?
5. Different logic styles like domino, resistive load etc (named and
explained) asked for comparison in terms of power and delay.
6. Difference between sequential and combinational
7. If we give clock as one of the input to AND gate it will work as
sequential or combinational and how
8. What is power dissipation? What affects dynamic power, how we
can improve?
9. Techniques to reduce Power dissipation, How supply voltage affects
the threshold voltage?

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Interview 47

Intel (Telephonic)

1.Introduce yourself briefly.

2.What were you doing in the gap between btech and mtech.
3.Explain your first project (from that project asked questions regarding
pipeline structure)
(a)what is pipeline, when do we prefer it what are its advantages
(b)what are improvements of your projects to the existing ones
(c)what is your contribution in this project
4.Explain 2nd project what are improvements from existing ones
5.(a)What is delay
(b)On what parameters it depends on (internal and external i.e,
transistor(CMOS)level and circuit level)
(c)How do we model it
(d)What are the two important models in interconnects and explain
them(T and pi)
(d)How do you calculate it
 (e)How can we reduce it.
6.Given a general question on charge distribution on capacitors:
Assume a 3pF capacitor is initially charged with a 5V battery, after it is
fully charged 5V battery is disconnected.
Now to this 3pF capacitor another 2pF capacitor is connected in
parallel with a switch in between them such that whenever the switch is
open charge flows from 3pF to 2pF.
In steady state, what will be the charge distribution on each capacitor?
(tell exact answer in numerical)
7.(a)What are setup and hold times, define them.
(b)Given two FFs with a combinational logic in between them, how to
rectify setup and hold time violations.
8.What domains or profiles you would like to work in?
9.What are your strengths.
10.Do you have any questions to ask?

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Interview 48

INTEL

1) Introduce yourself

2) what was your experience in learning Python. Have you done any
projects using Python?

3) input data like "abcdefffffgklmpqrs..." is taken in verilog as data[150:0]

considering 8 bits for each alphabet.

a) What logic would you apply to find if any alphabet is

repeated more than 4 or 5 times ?

b) How do you optimize the logic for faster/better results?

c) Can you show how would you implement your logic in Verilog?

4) What was your target FPGA device for your project and how many logic
elements, LUTs etc in FPGA device that you used for your project ?

5) Have you performed any timing analysis for your FIR/IIR project and
how have you performed it?
6) How many gates are required to implement 4 input XOR gate using 2
input XOR gate

a) in how many ways can it be implemented?

b) Is there any change in no of gates required to implement in

different ways?

c) Which type of representation would you use for better timing?

7) How many gates are required to implement 17 input XOR gate using 2
input XOR gate and how many levels are required to implement it for
better timing?

8) Which domain are you interested in frontend or backend?

9) Write TCL code to create list and display all elements in the list

10) How many ports(inputs & outputs) are required to implement a D

latch and what are they? Write Verilog code for D – latch.

11) Why is posedge not used in sensitivity list for D- latch?

12) How many bits are required to represent product of two 8-bit
numbers in Verilog for signed and unsigned multiplication?

13) A FIFO is given with has 8 elements in it. What logic would you
implement to create a new FIFO having elements of input FIFO in random
order?

Interview 49:

1. Introduce about yourself

2. What is STA?
3. What are the violations in STA?
4. How to check setup and hold time violations?
5. What do you know about MOSFET?
6. Tell me what you know about NMOS?
7. What is the effect of Vg on the operation of MOS?
8. What is the effect of Vd on the operation of MOS?
9. What do you know about the second order effects in MOSFET?
10. Explain the second order effects.
11. What do you know about Physical design?
 12. Explain the components of Physical design
13. Brief about your previous work experience

interview 50 : 1) About yourself

2) project in detail ( algorithm , language used delay, comparison)

3)area of interest in VLSI

4) Difference between flip-flop and latch

5 )setup and hold time ( violation and how to avoid that )

6) AND gate using 2:1 MUX

7 )how many 2:1 MUX are required to construct 2^n:1 MUX ,

Number of NAND required for EX-OR and Ex- NOR

8) what is buffer , and its use

9) About MOSFET ,it's region of operations

10) physical design flow

11) floorplaning algorithm (it was in my j comp)

12) perl : length of word syntax and try same in python

13) verilog: task , function , code for full adder , what is gate level
modelling

14 ) what is RTL

15) About CMOS

16) Leakage power , how to reduce that

17) power gatting

● 18 ) ABOUT Btech projects in detail ( as it was contain IOT)

Interview 51

1) Introduce about yourself

2) Project in detail
3) Blocking and nonblocking
4) Task and function diff
5) Make not gate from exor

Interview 52

1) encoding and decoding levels

2) code converter....binary to great
3) RTL to GDS flow
4) questions on all projects
5) glitch?
6) shielding?
7) use of always block

Interview 53

1. About project
2. Asked about verilog as my project was on verilog. And went in
depth of the project.
3. Asked to write code for 4:1 mux using 2:1 mux.
4. What is delta simulation time?
5. Given a block of code with delays and asked difference between the
2 codes.
6. Given a C program with pointers and asked output of the program

Interview 54

Tell me about your syllabus

What projects have you done?

What was your role in the project?

Few project specific qns

Tell me what you know about pipelining

Probability of signal related qn

What is Logic and Physical synthesis? Which is better?

What are library files? what do they contain? Why do we use it?

Can you tell me about few constraints?

Which language do you write the scripts in?

Tell me about your assignments in TCL

Taught a concept in STA, gave few values for delay and asked qns on it

What do you know about FSMs

Can you design an AND gate with FSM

Difference between Mealy and Moore? Which is better?

Tell me about ur assignments on verilog, have you done any FSM system
in verilog?

What exactly is the formal definition of FSM

Tell me about your interests

Tell me few achievements of yours and some challenges you have faced
in your life

Any questions for me?

Interview 55

1. Give your intro

2. About project
3. Cross questions on project and its output, applications, reason for power
improvement

4. Draw CMOS

5. Can you use this for analog and digital design both, how

6. CMOS characteristics

7. I-V characteristics of MOSFET

8. Transfer c/s of MOSFET

9. Draw graph to show input and output voltage in CMOS

10. Load curve for nmos and pmos transistor in cmos

11. Draw VT C/S of cmos

12. What is Latch-up

13. What is SRAM & DRAM

14. What is 6T-SRAM, draw it

15. In that asked about read and write operation

16. Asked to replace the cmos in that with inverter(as i mentioned four of
the transistors are a part of Cmos)

17. Said to adjust inverter one over the other

18. Draw CMOS cross section, in that asked how u say it as MOS from the
diagram

19. Body effect

Company 2 : Qualcomm :- 1/4/2021

Interview 1
 1. Asic flow
2. In that Asic flow he asked what is synthesis
3. Tools used for synthesis
4. What is leakage current
5. What is the current technology in the market
6. What are chip manufacturing companies in India
7. Why did you choose vlsi domain only
8. Does the job experience really important or not in any company before
joining Mtech
9. What made you to choose only ECE but not other streams
10.

Interview 2

1. Why you choosed vlsi.

2. Explain about your projects.
3. Make 4:1 mux from 2:1 mux.
4. Make buffer from xor gate.
5. Make and gate from 2:1 mux.
6. What is difference between cmos vs ttl .
7. Draw inverter using cmos and explain its working.
8. How power is dissipated in cmos inverter.
9. What are the regions of operation of mosfet.
10.Write verilog code for swapping variables without 3rd variable (using
blocking and non blocking).
11.Difference between intra and inter assignment delay.
12.What are universal gates.
13.Draw xnor from nand gate.
14. Explain asic flow and synthesis step.
15.What are files added in synthesis step.
16.Explain content of sdc file.
17.How you will define constraints of sdc file.
 18.What is false path explain with figure how you will define its constraint in
sdc file.
19.What is multicycle path explain with figure how you will define its
constraint in sdc file.
20. If there are 3 ostriches given which statement is true.
1. Ostriches can fly.
2. Ostrich can fly.
(Answer is both statements are wrong as ostrich cannot fly..)

Interview 3

1. Tell me about yourself

2. Numerous questions about my projects.
3. About my extracurricular activities (conferences and certificates)
4. How many programming languages did I know (mostly stressed on python
and c language)
5. What will the following command do in C language: static int x=0;
6. Verilog basics
7. Wrote two commands using blocking and non blocking statements and
asked which one is what
8. Output for the above
9. Code of any basic shifter
10. What will be the last digit of 2^123
11.Explain the approach used to find the above.
12.Change the code for the shifter by including reset. Shifter works for reset = 0
and skips for reset =1

Interview 4
1. Tell me about yourself and abt my fav subject
2. As I chose my fav sub as testing and testability, he asked me to find out the
i/p Test pattern for detecting fault at one node(he mentioned) in the given
combinational ckt and explain how?
3. And similarly controllability and observability of some other node with clear
explanation.
4. Draw 8*1 mux using 2*1 mux with truth table.
5. And he modified the truth table,and ask me to modify the ckt.
6. How many 2*1 mux are required to design n*1 mux and why?
7. Draw a fsm for sequence detector of 1001?
8. If there r 16 badminton teams in a knockout tournament, how many matches
will be conducted in the whole tournament?If we say any ans,he asked how
and why with our approach?
9. Write the program logic to find a missing num in an array tht consists of all
numbers b/w 1 to n (example n as 100)?
10.What type of searching approach will be used to find a num in an array tht
consists of all adjacent numbers to any num will be differ by 1(i.e., 1 or -1)?
(Array ex: 5 6 5 4 3)
11.Puzzle ques on 100 floors and 2 eggs ?
12.Framed much ques on tht puzzle by modifying the assumptions?
13.If the puzzle can be solved by using a binary tree method, how many max
num of eggs tht r required ?
14.Finally asked abt my prev intern exp and the prev sem sub?

Interview 5
1 . Difference between FF and latch
2 RTL to GDS flow
3 output prediction of c program given by interviewer
4 perl regular expression
5 swapping of value between two register
6 obtained circuitry for verilog code given by interviewers
7 logical questions- 8 balls with one heavy ball in it ....How many iterations
are required to find a heavier ball if weight balance is given to you.
Company 3 : Mediatek :- 5/4/2021

Interview 1 :
1.Can you tell me something about you ?
2.Have you done any Design based project ? Can you explain your project
design?
3. Explain the implementation of floating point adder and multiplier
modules (project specific).
4. What does shifting of the bits in the register do to the values in the
register?
5.How did you choose the clock frequency for your project?
6. What tool did you use for synthesis ?
7.What are inputs to your synthesis?
8.Describe setup and hold time and write the equations for both.
9. If the setup time is violated for a design because of a very slow data path
does it mean that your hold time will definitely not be violated ?
10. Verilog concept of blocking and non blocking ?
11.What hardware will happen if a for loop is synthesised ?
12. What is an optimization that can be done to bypass the disadvantage of a
for loop ?
13.Synthesis output of various verilog codes.
14. Logic question - how many square in matrix 4*4 ?

Interview 2:
2 Interviewers:
Int1:
(a)STA concepts
Setup and Hold time
Gave conditions and asked whether setup and hold was violated, and
if so, how to overcome.
Ex. If we have 2 circuits, one with skew 100ns and hold time 20ns,
another with skew 500ns and hold time 20ns, which one would you choose
and why.

(b)Programming:
 Suppose a file has ‘n’ numbers, find the unique number.

Suppose a file has 2 columns, one containing the cell

number(cell1,cell1,cell2,cell1..), and the other containing the slack values(-
0.56,-0.46,-0.23,-0.15..), print the worst slack value from each cell.

Int2:
A. Gave a CMOS circuit with pmos and nmos, asked output
voltage(output considering threshold voltage concepts)
B. HVT cells, LVT cells..
Why are they used..
What are the leakage power components?
Why do HVT cells have high leakage?
How does temperature depend on the leakage?
C. Master-Slave Level triggered Latch-
a. How should clk and clk’ be connected
b. Setup and Hold times.

Interview 3 :

1. Inverter transfer characteristics, beta ratio, Switching threshold, region of

operations, Noise margin
2. Threshold voltage equation. Factors affecting Vth, Dependence with respect
to doping concentration
3. Subthreshold leakage, Power dissipation - Static, Dynamic
4. Setup and hold definitions, Gave an example circuit containing two flops
and combination logic to analyse setup and hold.
Ways to avoid setup and hold violations.
On buffers, High Vt, Low Vt cells
Which does more harm - setup or hold violations. What can be done if such
violations noticed after tape out
Interview 4 :
1. Device physics around W/L ratio
2. Device physics around temperature affecting a MOSFET
3. What is antenna theory ( physics related)
4. Metric..(some 4 unknown questions which I heard first time)
5. And gate using mix
6. Verilog code for decoder 2 to 4
7. Memories eeprom and other non volatile things in depth structures and
explanation.

Interview 5:

1. Introduction.
2. Asked questions about my participation in the events in btech which I had
mentioned in my resume.
3. Went into the details of the projects, asked many questions (most time spent
here)
4. Combinational delays.
5. Arrival time, required time, skew.
7. Gave a problem statement on skew and asked me if it would create setup time
violation or hold time violation and how.
8. How can you reduce skew?
9. Difference between for loop and foreach loop.
10. Blocking and non-blocking assignments.
11. What is the threshold voltage?
12. What is routing?

Interview 6 :
1)Introduction
2)Form all projects he asked questions related to frequency,delay,power
3)setup and hold time definitions
4)one setup time sum
5)scripting:lists,arrays,grep command,for and foreach loop
6)blocking and non blocking assignments
7)power reduction techniques
8)area optimization how can be done
9)parasitic elements and its effect on setup time
10)cross talk
11)pass transistor
12)transmission gate
13)why low vth increases leakage
14)Why do I want to do an internship and not a thesis?
15)which domain I am interested in and why ?
16)Effect on setup time when implemented on actual chips and why?
17)What was my BE project ?
18)Is there any project in which I used scripting language?

Interview 7:
1.CMOS inverter working with graphs and regions of operation.
2.Device physics in depth.
3.MOS theory, drawing graphs etc
4.Set up ,hold violation

Interview 8:
1. Introduction
2. Setup and hold with equations
3. VLSI design flow (from specifications to Tapeout)
4. And using mux
5. For a certain frequency , there is a violation in the design and cant be
optimized , what can be done. (can declare as multicycle path or increase the
time period)
6. About synthesis, inputs to synthesis
7. What tech file contains
8. Blocking and non blocking, synthesis of blocking and non blocking
statements
9. Clock skew, and how does it affect timing
10. If there is clk net and reset net to a flip flop which will be routed first
11.Clock jitter and uncertainty, will it be included in both setup and hold check
 12. If there is high frequency signal, in which layer will it be routed
13.A reasoning question (in a 4x4 square array, how many squares were there)
14.Questions on DRC, antenna violations(as i spoke about it in PD flow)
All the questions are follow up questions, they will ask what you say, if you
answer any thing on which you are not clear then you will get stuck.

Interview 9

1. Inverter transfer characteristics, beta ratio, Switching threshold, region of

operations, Noise margin
2. Threshold voltage equation. Factors affecting Vth, Dependence with
respect to doping concentration
3. Subthreshold leakage, Power dissipation - Static, Dynamic
Setup and hold definitions, Gave an example circuit containing two flops
and combination logic to analyse setup and hold.
4. Ways to avoid setup and hold violations.
5. On buffers, High Vt, Low Vt cells

Company 4 :- Amd ,16/4/2021

1. Interview 1:-
1)Some MCQs were displayed and have to answer one by one
Mainly from digital electronics,DFT,microcontroller,memory
2)Tell me about yourself
3)Explain project:some questions from project
4)Design 7 bit comparator using XOR gates
5)Blocking and Non-blocking assignment
6)How to swap two variables using non blocking assignment
7)Fibonacci series code in any language.
8)How to synchronize two systems operating at different frequencies
9)How to calculate depth of FIFO.
10)How to design latch from mux
11)4-5 puzzles
2) Interview 2:-
1) Tell me about yourself
2) Some MCQs were displayed and had to answer one by one mainly from
digital electronics,DFT,microcontroller,and memory.
3) 4-5 puzzles were asked
4) Uvm related questions
5) Describe inheritance concept
6) Difference between synchronous and asynchronous reset
7) Difference between flip flop and latch
8) What is the setup and hold time?
9) Few questions from verilog.

Company 5 : infineon (26/4/2021)

Interview 1
1)Questions regarding Projects.
2)2 Puzzles
3)Temperature dependance of Vt
4)Mos device basics. Drain current etc.
5)dependence b/w device speed and Vt

Interview 2
1)MOSFET (inshort), drain current equations(for linear sat and conditions), related
qtns)
2)Max clock frequency equation
3) Temperature and threshold voltage relation. Temperature and mobility relation
4)XNOR using MUX. Is MUX universal?
5)What is setup and hold. Ways to avoid setup and hold violations.
6)Can setup or hold be zero or negative
7)Combinational and sequential
8)flipflop and latch
9)level and edge triggered
10)Functions of Flipflop
11)What is saturation region in mosfet ? How does it occur?
12)Sizing of transistor example and related qstns
13)ASIC flow
14)SDC file and content of sdc file.
15)Puzzle
16)Verilog code for D-FF
17)CMOS inverter working .What is the output if PMOS and NMOS interchanged
18)Beta ratio, Switching threshold, region of operations
19)If 4-bit data how many outputs will be there? And how many 0 to 1Transitions?
20)

Interview 3 :

1. What is testing?
2. What are the faults that can be seen in a basic gate eg-and gate?
3. How to detect faults for basic gates? What vector will u use to detect each of
them.
4. How can u detect SA0 fault on the output of the and gate ?
5. If there are two SA0 faults one in the input of the and gate and one at the
output, then how can you distinguish between the two faults ? or How can
you be certain that the fault is at the output and not the input. ?
6. Describe what is Noise Margin?
7. How does a circuit know what range of inputs is high input and what range
of inputs is low inputs?
8. What is depletion region in a diode? How is it formed?
9. What is pinch off voltage in a mosfet ?
10.Why does current get saturated at the pinch off voltage ? Physics behind it ?
11. What is a use of buffer other than delay unit ?
12.If a voltage source is overloaded with loads that take lot of current how can
you use an op amp in to regulate this ? Hint: Use opamp as a voltage
follower
13.What is virtual ground in an opamp ?
14.Setup and hold time ?
15.Why depletion region width stops after becoming a certain level ? What is
the physics behind this?
 16.What is saturation region in mosfet ? How does it occur?
17.C programing basics.

Interview4:
3 rounds
Round 1
Q1. Run me through your CV.
Q2. Explain me about the internship i had done in my UG(LabVIEW based)
Q3. Projects in LabVIEW I had done, basic questions on LabVIEW
Q4. Sir Explained about company.
Round 2 (with different Panel)
Q1. Explain about ur CV
Q2. Experience on Round1
Q3. Explained about domain of internship-Type C cable Verification.
Q4. Asked to design a mod 4 UP counter(in paint), draw truth table verify
functionality.
Q5. Asked about OPAMP architecture, its characteristics and asked to draw some
opamp configuration(Inverting amp...) and calculate gain
Q6. C program to take n input nos and find avg, min, max, of those.
Q7. Basic question of Testing(how modern day IC are tested)

Round 3(first panel +3 others)

They shared my resume and asked every nook and corner of my UG and PG
project, regarding what hardware u used, how eah and every component work, also
regarding on my BE internship work.
At last they told about company.

Interview 5:
Q1. He asked me about the projects to explain everything in detail by mentioning
all the component details like for example if we use an adc, what is the type of adc
and which is the ic used in that adc.
Q2.design of dlatch using 2 to 1 mux.
Q3. difference between synchronous and asynchronous reset and asked me to write
the verilog code for it.
Q4. i was asked to write a verilog code for d flipflop.
Q5.two flipflops of different frequencies.how will they be connected.what is the
component to be placed in between them
Q6. how do you explain velocity saturation without going into equations
Q7.Draw state diagram for 1010 non overlapping sequence.
Q8. what is the voltage at which we operate the device when we say that device is
used for high power applications
Q9. xor as inverter and buffer
Q10. what is noise margin.whether having noise margin is better or worst
Q11. difference between blocking and non blocking assignment.
Q12. difference between inter and intra assignment delay
Q13. what is the dynamic power. How do we reduce it.
Q14.what is setup time and hold time
Q15. calculation of maximum clock frequency giving tcq,tcomb,tsetup. And was
asked whether holdtime depends on clock or not
Q16.what is clock gating. And the circuit for clock gating
Q17.puzzle on bridge crossing
Q18.Brief about yourself
Q19.Questions based on tools we have used like LT spice.
Q20.gave a timing diagram of input and output showing a ckt sharing his screen
and asked to find unknown element.

Interview 6:
Round 1
Q1 brief about urself and projects u did along with area of interest
Q2 Brief about ASIC Design flow
Q3 why we require STA what will happen if we don't use STA
Q4 what is setup and hold violations
Q5What will happen if we don't consider them and how to reduce or eliminate
those violations.
Q6 what is DFT
Q7 what are faults
Q8 what is scan mode test mode
Q9 realise a latch using mux and explain
Q10 difference between synchronous and asynchronous reset
Q10 latch Vs flipflops
Q11 where will we use flipflops
Q12 where will we use latches in sequential circuits (ans we will use in rare
condition like in ASIC multi cycle paths half cycles concept in that we use latches
to help our circuitry)
Q13 HDL explain
Q14 Difference between HDL and C
Q15 verilog Vs C
Q16 projects I had done what I understand from them are there any issues I faced
during that time(please explain elobarately)
Q17 how I overcome the issues during my projects
Q18 in current project u are doing what are the advancements u are doing apart
from what others did tell about it briefly
Q19 what are your greatest obstacles that u faced in our academics point of view
tell me everything about it how u overcome that
Q20 Good luck only 1 round asked.

Interview 7:

1) Explain your projects (MTech) in detail?

2) What happens if we use nmos in pullup and pmos in pulldown network of a

cmos inverter?

3) Explain the terms pinch off, velocity saturation, mobility degradation.

4) What is subthreshold conduction, explain with the help of graph.

5) Draw practical voltage source and its output waveform?

6) High pass filter circuit with different input waveforms and what happens to
the output waveform and the frequency response when we change the values of
R and C in the circuit.

7) What is meant by scaling, if we go from 180nm to 90nm technology what

are parameters that get changed?

8) Explain the current conduction in diode, how the junction is formed, what is
reverse leakage current, on what factors it depends.
 9) What is doping, junction barrier, how the width of the junction depends on
the doping concentration .

Interview 8:
1. Introduction
2. Tell me about project
3. FinFet technology
4. MOSFET current equation in saturation and linear
5. AND gate using one 2:1 MUX

Company 6 :- Stmicroelectronics (27/4/2021)

Interview 1 :-
1) Comparison of 45nm, 90nm, 180nm (project based qstn)
2) What all affects Power ? How is delay and drain current related
3) Threshold voltage dependence on temperature, current
4) Does W/L ratio affect Vt.
5) Threshold equation and related qstns. (Cox, Tox, ϕb dependence on Vt ,
how doping and channel length affect Vt)
6) For a NMOS if Positive voltage is applied to source and Source is
grounded what will happen?
7) Turnon time, body biasing, Vt roll off , Inversion and related qstns
8) How does body effect occurs
9) Subthreshold conduction
10) Difference between latch and flip flop
11) Draw waveform for latch and flip flop
12) Level triggered and edge triggered
13) Nand and Nor gate Using CMOS
14) Sizing of transistor
15) Which is Fast NAND or NOR?And Why?
Interview 2-
1. Intro
2. About project, cross question on Project
3. Why u switched from EE to EC
4. Whpower IC design, how we can attain thaty we seek for low
5. How you attain low power optimization on 2architectures(based on project)
6. Region of operations in MOSFET, effect of change in voltage.
7. Role of p substrate and n substrate in Mosfet
8. What do you mean by Scaling Mosfet
9. Scaling in vlsi should be greater then or equal to 1?
10. In a pmos connected ckt find effective W/L ratio
11. What is the role of Gate oxide.
12. CMOS logic
13. Layout design rule
14. DRC rule
15. Difference between blocking and non blocking
16. Difference between sequential and combinational
17. Difference between latch and flip-flop
18. How latch can be used to make FF
19. If input is give as 1100 what will be the output in Johnson counter and Ring
counter
20. Difference between Ripple adder an carry look ahead adder, which is better
21. Effect of capacitor and inductor on frequency in LPF
22. AND gate using mux
23. Can we use xor as delay element
24. Buffer and Inverter using exor gate
25. setup and hold time
26. Find for setup and hold violation for the given values in ckt
27. Intra and inter assignment delay
28. In given circuit find the current depending on the resistance value
29. Power optimization factor
30. Do you have any question for me.

Interview 3-
1)Describe your Sem2 projects.
2)Gave numerical value of VGS,Vth and told to plot Cgs Vs VGs graph
3)Asked to derive gm for Nmos transistor
4)Asked the regions of operation for NMOS
5)Are you GATE qualified
7)Unity gain bandwidth question.

Interview 4
1) Introduce yourself
2) Project explanation in detail.
3) What is the difference between digital flow and analog flow in detail?
4) What is synthesis and simulation.?
5) What is latchup in Cmos?
6) Operation of Cmos?
7) Plot the output wave , DC analysis of Cmos?
8) What is W/L in transistors and how does it effect the transistor?
9) Swaping of number in perl
10) Draw the FSM for 0111
11) What is the value of pi? Explain?
12) What is mass and weight?

Company 7 :- Seagate (offcampus)

Why is cmos preferred?
Why is power consumption less in cmos? Compare with any and explain
What are universal gates?
Why universal?
Difference between flip flop and latch
Can latch be clocked?
Draw output waveforms for both for given input waveform
Construct not and buffer from xor
One circuit was given, and input waveform, draw output waveforms
If nmos and pmos are switched in a cmos, what will happen?
Why are cascaded inverters used? Why do we prefer them?
Drawbacks of cascaded inverters
Difference between asic and fpga, which one is better?
Input files required for physical synthesis
Explain what is done in physical design in brief (you should explain the flow
here)
Which input files are required for physical design?
Tools required for physical design
About projects in brief
Your introduction

Company 8 :- Intel (29/4/2021)

1. Interview 1
In the introduction tell me about your education, project, experience and what
you know about this domain? (VLSI)
This semester is your offcampus so what things have you done in this period?
What do you know about analog?
Draw any waveform for analog and digital. Explain?
Write a verilog code for a 2-bit counter with circuit and truth table.
What is FIFO? How it works.
Difference between a behavioural code and the code you write for a test bench
or a normal RTL code? How you differentiate that.
Difference between always and initial block.
Difference between synchronous and asynchronous?
Do you have any questions for me?

2. Interview 2
The interviewer told about his profile and domain of working
1)About project
2)specifics of project
3)What type of logic is used in the project?(combinational or sequential)
4)Difference between asynchronous and synchronous circuits
5)Difference between combinational and sequential circuits(cover all points)
6)What is clock gating?
7)How to overcome setup and hold violations?
8)Does fixing setup violation effect the operating frequency?
9)What should a designer keep in mind while designing a counter?
10)Gave a sequence(0011220).Asked how many flipflops are required to make
this type of counter?
11)Which specific domain are you interested in?
12)Do you have any questions for me?

3. Interview 3
1) Introduce yourself.
2) Explain all your Projects in detail.
3) In which domain are you more interested? Analog or Digital.
4) Draw the diagram of Nmos and explain its working.
5) Draw its characteristic graph and explain each region.
6) What is latch up?
7) What is antenna effect? How can it be improved?
8) What is current Mirror?
9) What is shielding?
10) What can you do to ensure proper clock distribution in all the
blocks?
11) Do you have any questions?
12) Are you ready to relocate?
4.Interview 4
1.tell me about yourself
2.daily routine
3.how much comfortable in verilog,python,perl,tcl
4.Asic design flow
5.Blocking and Non blocking
6.set and hold time and how to remove the violation
7.logic synthesis and physical synthesis
8.explain the challenge u faced in ur life
9.regarding project
10.write program in python to remove the duplicate
11.write program for merge sort
12.draw cmos diagram for Nand,Nor,And,or
13.can u draw cmos diagram of AND and OR with Inverter
14 what is fft and dft
 15.Nyquist Criteria
15.what is ADC
16.expalin the communication channel(input from mic analog signal and
receive in receiver end)
17.what all subject are there in this sem
18.Area of interest

Interview 5 :
1) Explain Your MTech projects in brief
2) What is Mosfet, explain the different region of operation of
Mosfet.
3) Difference between Microprocessor and microcontroller.
4) What is Stack pointer, program counter.
5) Difference between RISC and CISC processor.
6) What is sequential and combinational circuits.
7) What is tristate logic.
8) Implement Exor logic nor gates.
9) How Mosfet works as a switch.
10) Write a C program to – Swap two variables without using the third
variable.
11) Write a C program to – print pyramid of stars.
12) 2 puzzle questions.

Company 9 :- Nxp semiconductor (30/4/2021).

1. Interview 1:-
 1) He gave one STA problem and asked to find the maximum operating frequency of
the circuit.

2) What is setup time, hold time, what is violation in this.

3) What is metastability, how it is eliminated with the help of synchronizer, draw the
synchronizer circuit and explain in depth how this works.

4) What is the difference between latch and flip flop.

5) Write a Verilog code such that it infers a latch, how this can be avoided.

6) Write a Verilog code of a priority encoder using if else, case statement, explain what
will be the hardware changes in both the circuits.

7) What are blocking and non-blocking statements?

8) He asked the questions which I have not attempted in the written test.

9) Draw a state machine of mealy overlapping and non-overlapping sequences.

10) 2 puzzles.

Company 10: Microchip

1. Introduction
2. Difference between sequential and combinational circuit
3. What code do you use in sequential and combinal circuit (like
always@(.....))
4. Difference between latch and flip flop
5. What is the difference between in this code
Intra and inter assignment
always@(posedge clk)
begin
a=#5 b
#5 a=b
end
6. What are the Modulation techniques and what are they generally done
(like you have a carrier and have data etc.)?
7. Design fsm 010110 - give output 1 else give output 0.
 8. What are all gates used in verilog? What is a universal gate? Draw the
truth table of OR gate and NOR gate. Design a circuit of NOR gate using
OR gate (he said u can use AND gate also).

That’s all!!
All the best

2. Interview 2

● Basic device physics. Regions of operation and equations.

● Comparison between BJT and MOSFETS
● Difference between combinational and sequential circuits.
● Draw Mux using nand gates.
● Questions on STA: Definitions and how to decide frequency of circuits.
● Transistor sizing in basic gates.
● Which is preferred Nand gates or Nor gates in circuits.
● Delay models in digital circuits and gates.
● Questions on parasitics in gates.
● Which is more difficult to correct: Set up violation or hold violation.
● What is Race condition.
● Difference between latches and flip flops.
● Puzzle.

Company 11:Synopsys (May 18th 2021)

1) Introduction
2) 2 puzzles
3) What is mux?
4) Equation for 2:1 mux
5) Verilog code for asynchronous flip flop
6) Difference between flip flop and latch
7) What is race around condition?
8) Design of inverter and buffer using mux
9) Waveform of master slave JK flip flop
10) What is setup and hold time

11) Waveform for this circuit