Lecture 07
Interfacing Hardware to MPUs
7.1. Memory Interface
Issues
Memory Devices
Address Decoding
8086 (8-bit) Memory Interface
Memory Devices
Memory unit:
A collection of cells capable of storing a large quantity of
binary information and
• to which binary information is transferred for storage
• from which information is available when needed
Together with associated circuits needed to transfer
information in and out of the device
• write operation: storing new information into
memory
• read operation: transferring the stored information
out of the memory
Memory Devices…cntd
Two major types:
RAM (Random-access memory):
Read + Write (RW)
For storing temporary working data
ROM (Read-only memory): …is also random access
Perform only read operation
PROM: Programmable ROM(one time programmable-OTP)
EPROM: Erasable & Programmable ROM
EEPROM (FLASH): Electrically erasable PROM
Memory Types
Random vs. Sequential
Random-Access Memory:
• Each word is separately accessible
• Equal access time
e.g. Semiconductor memories, like RAM
Sequential-Access Memory:
• Information stored is not immediately accessible
• Access time is variable
e.g. Magnetic/optical disks
Memory Types…cntd
Static vs. Dynamic
SRAM: (Static RAM)
• Consists of flip-flop latches......takes more chip area
• Shorter read and write cycle….faster
DRAM: (Dynamic RAM)
• Data is stored as charge on capacitors…less chip area
• Each capacitor is controlled by a MOS transistor
• Capacitors tend to discharge with time…needs a
periodic re-charge (refresh)…more power consumption
• Requires complex address decoding & control…slow
Memory Devices…cntd
n+1 byte of SRAM & DRAM internally
D7 D6 … D0 D7 D6 D0
R/W An
CLK
…
D Q D Q D Q
An …
> > >
An-1
Q Q
…
D Q D D
An-1
> >
… >
…
…
A0
D Q D Q D Q …
…
A0 > > >
SRAM…..with D latches DRAM
Memory Types…cntd
DRAM:
Pros:
• High density (capacity) -> 1GB x 8, currently
• Cheaper cost per bit
Cons:
has to be refreshed every 2ms – 4ms
• While it is being refreshed, data can’t be accessed
• Larger access times
• Complex address decoding
• Higher power consumption
Memory Types…cntd
DRAM…addressing
Memory Types…cntd
DRAM…timing
DRAM…packaging
DRAMs are typically placed on SIMM (Single In-line Memory Modules) boards.
Refresh time example:
For a 256K DRAM with 256 rows, a refresh must occur every 15.6µs (4ms/256)
For the 8086, a read or write occurs every 800ns, This allows 19 memory
reads/writes per refresh or 5% of the time
Memory Types…cntd
Volatile vs. Non-volatile
Volatile:
• stored information is lost when power is turned off
Typical example: RAM
Non-volatile:
• Data is retained even after power is off
• suitable for permanent storage
Typical example: ROM devices
Memory Capacity
The number of bits that a memory device
can store; for semiconductor memories:
In parallel mode:
• Each memory chip contains 2 x locations
x = number of address pins on the chip
• Each location contains y bits:
y = number of data pins on the chip
Thus, the entire chip will contain 2x * y bits
In serial mode, two pins are required (data & clock)
• address and Data are time-multiplexed
• (x + y) times slower…x, y as defined above.
Memory Control
Each memory device has at least one Chip select (CS) or
Chip enable (CE) pin that enables the memory device.
Each memory device has at least one control pin:
• For ROMs, an output enable (OE) is present. The OE
pin enables and disables a set of tri-state buffers.
• For RAMs, a read-write (R/W) or write enable (WE)
and read enable (RE) are present.
Min mode 8086 µC system memory circuitry
Memory Interface
Address Bus System
Memory Interface
Address Bus system…Address latches
ALE
BHE
Memory Interface
Address Bus system…Address decoder
Before going to the address decoder logic, we have
to revise the 8086 memory addressing scheme
Memory address is 20-bit and I/O address is 16-bit wide
There are reserved locations, like interrupt vector table…
A given memory device can be mapped to any address space
by properly designing the address decoder logic.
Memory Interface
Address Bus system…Address Selection
RAM
Address bus
or
EPROM
Data bus
CS
Memory
Address SEL
IO/M Decoder
IO/M
A0 – A19 Valid
SEL
Memory Interface
Address decoder
E.g. 1
A 32KB RAM is to be interfaced to an 8086 based system, so
that the first address of the RAM is at 48000H.
• What is the entire range of the RAM Address?
• How is the address bus used to enable the RAM?
• What address lines should be used?
Memory Interface
Address decoder…cnt’d
Memory Interface
Address decoder…cnt’d
Address decoder for:
48000h – 4FFFFh
range
Memory Interface
Address decoder…cnt’d
E.g. 2
Given a 2K x 8 (2KB) EPROM, 27C16 for storing the BIOS
A0 D0
A1 D1
. .
27C16
Intel
. .
. D7
A10
CS
CS
How would you decode the address to map this EPROM in
an 8086 system?
Memory Interface
Address decoder…cnt’d
The BIOS should be
located starting at
FFFF0H: i.e.
CS: F000h IP: FFF0h
Memory Interface
Address decoder…cnt’d
E.g. 3 A0 D0
A1 D1
. .
Now assume you have eight
27C64
Intel
. .
8K x 8 (8KB) EPROMs 27C64 . D7
to be mapped from F0000h to FFFFFh A12
CS
to form a total of 64KB:
Memory Interface
Address decoder…cnt’d
Memory Interface
Address decoder…74138 (3 to 8 decoder)
• A13, A14, A15 selects one of the memory chips at a time
• G1, G2A and G2B enables the decoder, thus address lines
A16-A19 enable the decoder
In this case A16-A19 = 1111 (b/c the mapping starts at
F0000)
• Therefore, data can be latched to the selected memory chip
(one of the eight) at the desired address.
7.2 I/O Interface
Issues
Introduction
I/O ports and devices
Programmable peripheral Interfaces (PPI)
Introduction
I/O Problems
Wide variety of peripherals
o Delivering different amounts of data
o At different speeds
o In different formats
All slower than CPU and RAM
Need I/O modules
Introduction
I/O Modules
Interface to CPU and Memory
Interface to one or more peripherals
Introduction
External Devices
Human readable
Screen, printer, keyboard
Machine readable
Monitoring and control
Communication
Modem
Network Interface Card (NIC)
Introduction
I/O module functions
Control & Timing
CPU Communication
Device Communication
Data Buffering
Error Detection
Introduction
I/O steps
CPU checks I/O module device status
I/O module returns status
If ready, CPU requests data transfer
I/O module gets data from device
I/O module transfers data to CPU
Introduction
I/O Techniques
Programmed
Synchronous
Asynchronous with hand-shaking
Interrupt driven
Direct Memory Access (DMA)
I/O ports
Two types
1. Memory mapped I/O
2. Isolated I/O
I/O ports
Memory mapped I/O
Uses instructions that transfers data between
microprocessor & memory
Treated as memory location in the memory map
Portion of memory is used as I/O map
8086 uses M/IO control signal to select b/n
memory and I/O devices.
I/O ports
Isolated I/O
I/O locations are isolated from memory system in a separate
address space.
User can expand the memory to its full size
Data transferred between I/O and microprocessor must be
access by IN/OUT instructions
In PC, isolated I/O ports are used for controlling peripheral
device
8-bit port address access devices located on system board.
16-bit port access serial, parallel ports, video & disk drive
I/O ports
I/O Addressing
Two addressing modes
1) Immediate port address
- Can only be 1 byte immediate address
- Can only address ports 00h through ffh
2) Port address present in DX
- Can address all ports 0000h through ffffh
- Can only use DX for port addresses
- Can only use AL,AX for port data
I/O ports
I/O Instructions
Two I/O instructions:
Transfers information to an I/O device (OUT)
Read information from an I/O device (IN)
When data are transferred using IN/OUT instruction, I/O
address (port number) appears on the address bus
8-bit fixed port appears on address bus A7-A0
with A15-A8 bits equal to 00000000b
16-bit variable port appears on address connection
A15-A0
I/O ports
I/O Instructions…e.g.
IN AL, p8 ;Read from port p8 to AL
IN AX, p8 ;Read from port p8 to AX
IN AL, DX ;Read from port addressed by DX to AL
IN AX, DX ;Read from port addressed by DX to AX
OUT p8 , AL ;Output from AL into port p8
OUT p8 , AX ;Output from AX into port p8
OUT DX, AL ;Output from AL into port addressed by DX
ECEg - 4501 Daniel D. DECE, AAU
I/O Ports
I/O Port
Parallel I/O Serial I/O
A simple shift register can be used to change a serial Port
to parallel or vice versa
I/O Ports
Parallel I/O
Input
Basic input device has a set of tri-state buffers.
When microprocessors executes an IN instruction, I/O
port is decoded to generate logic 0 on SEL
I/O Ports… a simple I/P ckt.
I/O Ports
Parallel I/O
Output
Basic output interface receives data from microprocessor
and must hold it.
Flip-flop latches (buffers) are built into these devices
I/O Ports…a simple O/P ckt.
I/O Ports
e.g. Blinking an LED at an O/P port with a delay loop
I/O Ports
…cnt’d
MOV DX, 8000h ;initialize address of port 0
MOV AL, 00h ;load data with bit 7 as logic 0
ON_OFF:
OUT DX,AL ;turned on
MOV CX,FFFFh ;load delay count of FFFFh
HERE: LOOP HERE
XOR AL,80h ;complement bit 7
JMP ON_OFF
PPI (Programmable peripheral interfaces)
Several developed by Intel to ease design burden
Provide a complete I/O interface on a single chip
Examples of common I/O interface chips:
8255A Programmable Peripheral Interface (PPI)
8259 Programmable Interrupt Controller (PIC)
8253/4 Programmable Interval Timer (PIT)
8237 Programmable DMA Controller
IBM PC/XT had these chips on system board
Modern PCs have functionality included in system chipset
PPI (Programmable peripheral interfaces)
- Download the datasheet for 8255 and refer to
- The internal structure
- How to interface with the microprocessor
- how to control data transfer between the ports and the
microprocessor
PPI
8255 - Programmable Peripheral Interface
(Parallel Port Interface)
8 8
Data
Port A
RD 8
Port B
WR
4
RESET
CH
CS
A1
Port C
{ CL
4
A0
PPI example
8255 – stepper motor control
