8 Ways to Use a Digital Module in a CompactRIO System

Publish Date: Feb 05, 2016

Overview
National Instruments offers over 20 digital modules that you can use to input and output digital signals within a NI CompactRIO
System. C Series digital modules are available in a variety of signal levels, speeds, and channels so you can build a system to
meet your specifications. Each module provides an excellent way to accomplish basic tasks such as monitoring states or turning
machines on and off. When combined with the power of LabVIEW and FPGA through the NI CompactRIO, the capabilities of each
module are multiplied exponentially.

This paper examines eight ways that you can increase the functionality of your digital module. Some advanced functionality on
certain modules can be programmed in Scan Mode using precompiled FPGA personalities, also known as Specialty Digital. The
examples below show how to program using LabVIEW FPGA and the FPGA Interface. In order for these examples to work
properly they must be configured properly for your specific NI CompactRIO chassis. For more information see Moving Examples to
Another FPGA Target (http://www.ni.com/white-paper/5075/en).

Note: Each C Series digital module provide different timing characteristics. Make sure to select a module with the timing
characteristics that meet your application needs.

Table of Contents
1. Event Counting
2. PWM
3. Encoders
4. Frequency
5. Digital Filtering
6. Synchronization
7. Communication
8. Custom Triggering
9. Next Steps
1. Event Counting
Event counting is one of the simplest tasks that you can accomplish with a digital module. Event counting, the process of counting
every rising and/or falling edge on a digital signal, is useful in a wide variety of applications, from measuring a motor to accounting
for the volume of liquid flowing through a pipe. Traditional systems require a dedicated on-board counter or a separate counter
module to perform counting operations. With CompactRIO and a module such as the NI 9403 (
http://sine.ni.com/nips/cds/view/p/lang/en/nid/208811), you can create your own counter applications using the FPGA. The
number of counters you can create is only limited by the number of digital lines in your system and the size of your FPGA. Use a
wide range of digital input modules to count digital signals as high as 250 VDC (NI 9435 (
http://sine.ni.com/nips/cds/view/p/lang/en/nid/208820)) and as low as 2.5 V (NI 9402 (
http://sine.ni.com/nips/cds/view/p/lang/en/nid/208810)).
The following example demonstrates how to implement an event counter using LabVIEW FPGA and the CompactRIO system. The
example uses Boolean logic to determine whether a rising or falling edge has occurred. This example can be found in the
LabVIEW Example Finder and navigating to Hardware Input and Output >> CompactRIO >> FPGA Fundamentals >>
Counters >> Event Counters >> Event Ctr, Either Edge – cRIO.lvproj.
Configuring Your Event Counting VI
1. Connect the line you want to be counted to any digital input line.
2. Open and modify the block diagram of the Quad Ctr VI so the digital input channel of the physical signal replaces the A and B
Boolean controls.
3. Run the VI to compile it and use it in interactive mode.

Figure 1 – Modify Your Code for Counting External Signals

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 Figure 1 – Modify Your Code for Counting External Signals

2. PWM
Use pulse width modulation (PWM) to output a series of digital pulses to control an analog circuit. You can vary the length and
frequency of these pulses to determine the total power delivered to the circuit. PWM signals are most commonly used to control
DC motors, but apply to many other applications, such as controlling valves or pumps or adjusting the brightness of an LED.

The digital pulse train that makes up a PWM signal has a fixed frequency and varies the pulse width to alter the average power of
the signal. The ratio of the pulse width to the period is referred to as the duty cycle of the signal. For example, if a PWM signal has
a 10 ms period and its pulses are 2 ms long, the signal is said to have a 20 percent duty cycle. By controlling the duty cycle of the
PMW, you can control how much power the analog circuit uses. You can use NI digital modules to output your controlling PWM or
measure the duty cycle of an existing PWM.

Figure 2 - Pulse Width Modulation

The following example uses the Loop Timer.vi to control the length of a pulse’s high and lows This example can be found in the
Example Finder and navigating to Hardware Input and Output >> CompactRIO >> FPGA Fundamentals >> Counters >>
Event Counters >> PWM Out, Simple - cRIO.lvproj.

Configuring Your PWM VI

1. Connect the line you want counted to any digital input line.
2. Modify the block diagram of the PWM Out, Simple VI with the digital output channel on which you want to generate your PWM.
3. Run the VI to compile it and use it in interactive mode.

Figure 3 – Modify Your Code to Generate a PWM Signal

3. Encoders

An encoder is an electromechanical device used to measure motion or position, in applications such as medical device or
industrial machine testing. Most encoders use optical sensors to provide electrical signals in the form of pulse trains. Multiple pulse
trains provide more information about the signal. A digital module such as the NI 9401 (
http://sine.ni.com/nips/cds/view/p/lang/en/nid/208809), can capture these pulse trains and use the FPGA, to translate the signals
into motion, direction, or position information. You can also use NI digital modules to mimic the output of an encoder for other
applications such as Hardware in the Loop (HIL) testing. Because they service so many types of applications, encoders can come
in many different shapes, sizes, and output levels. NI offers multiple digital modules you can integrate with the specific encoder
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in many different shapes, sizes, and output levels. NI offers multiple digital modules you can integrate with the specific encoder
your application requires. Use the NI 9421 (http://sine.ni.com/nips/cds/view/p/lang/en/nid/208813) to read 0 – 24V signals in an
industrial environment. Use the NI 9401 (http://sine.ni.com/nips/cds/view/p/lang/en/nid/208809) to read Transistor-to-Transistor
Logic (TTL) or 0 – 5V signals in a clean laboratory environment.
The following example demonstrates how to use LabVIEW FPGA and your CompactRIO system to implement encoder
measurements. The example uses Boolean logic to determine whether an AB Quadrature encoder is turning and which direction it
is turning. This example can be found in the Example Finder and navigating to Hardware Input and Output >> CompactRIO >>
FPGA Fundamentals >> Counters >> Quadrature Input >> Quad Ctr – cRIO.lvproj .

Configuring Your Encoder Application

1. Connect your A and B signals to two digital lines.
2. Modify the block diagram of the Quad Ctr.vi with the digital input channel of the physical signal to replace the A and B
Boolean controls.
3. Run the VI to compile it and use it in interactive mode.

Figure 4 – Use Boolean logic within the FPGA to Track Position

4. Frequency
The frequency of a digital signal is the rate at which the period occurs, where the period is the time between either rising or falling
edges, or the inverse of the period with a unit of Hertz (Hz). The frequency of a digital signal can be extremely useful in a wide
variety of applications, from determining speed or angular velocity to decoding the intensity of a light source. Use LabVIEW and
CompactRIO to program your C Series digital module to transfer the digital signal to the FPGA, which uses a period decoding
algorithm. The period is then transferred to a host application, which extrapolates the frequency. After you acquire the frequency,
you can map it to a known physical phenomenon.

Figure 5 - Period and Frequency of a Digital Signal

The following example describes how to implement frequency measurements using LabVIEW FPGA and a CompactRIO system.
The example uses Boolean logic to determine when an edge occurs and then uses the FPGA clock to determine the time between
pulses. This example can be found in the Example Finder by going into LabVIEW and navigating to Hardware Input and Output
>> CompactRIO >> FPGA Fundamentals >> Counters >> Frequency Measurement >> Count and Period – cRIO.lvproj.

Configuring Your Frequency Measurement

1. Physically connect signal of interest to a digital line.
2. Modify the block diagram of the Count and Period (FPGA) VI with the digital input channel of the physical signal to replace the
A and B Boolean controls.
3. Run the VI to compile it and use it in interactive mode.

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 Figure 6 – Determine the Period and Frequency of a Digital Signal

5. Digital Filtering
Environmental factors such as ambient noise or the mechanical “bouncing” of an industrial switch or sensor can make it difficult for
your data acquisition system to receive clear signals. A CompactRIO system with FPGA allows you to implement a technique
known as digital filtering or digital de-bouncing. Digital filtering is the process of verifying that a signal has remained at its new level
for a specified period of time before allowing the signal change to propagate to the processing aspect of the system. This method
filters glitches or noise on the line and reduces unwanted behavior in the system.
The following example demonstrates how to filter digital lines using Boolean logic, LabVIEW FPGA, and a CompactRIO system.
The signal must remain at its new level for the specified amount of time before the filtered input will reflect the change. This
example can be found in the Example Finder by going into LabVIEW and navigating to Hardware Input and Output >>
CompactRIO >> FPGA Fundamentals >> Digital Filter >> Digital Filter – Sampled – cRIO.lvproj.

Filtering Your Digital Line

1. Physically connect the signal of interest to a digital line.
2. Modify the block diagram of the Digital Filter – continuous VI with the digital input channel of the physical signal to replace the
input control.
3. Run the VI to compile it and use it in interactive mode.

Figure 7 – Filter Your Digital Signal Using the FPGA

6. Synchronization
Timing and synchronization are essential elements of design, test, and control applications and should be key considerations in
any system. CompactRIO supports both signal-based synchronization and time referenced synchronization.
Signal-Based Synchronization
Signal-based synchronization connects all of your systems together with cabling, which allows you to share clocks and trigger
signals across systems. In signal-based synchronization, the master system creates a clock and then shares that clock with all
other systems through cabling. When the master system initiates an action, such as data acquisition, a trigger signal is shared with
the other systems to begin the action. Signal-based synchronization is more precise than time referenced systems because clock
and trigger signals are physically connected to each system. The NI 9469 (http://sine.ni.com/nips/cds/view/p/lang/en/nid/210832)
was designed to synchronize modules with simultaneous delta-sigma analog-to-digital converters for high-channel-count systems
that require more than one chassis. Delta-sigma modules require a separate oversample clock to operate. Each delta-sigma
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that require more than one chassis. Delta-sigma modules require a separate oversample clock to operate. Each delta-sigma
module has an onboard clock for normal operation that is physically routed through the CompactRIO chassis to synchronize all
delta-sigma modules within a single chassis. For multi-chassis systems, the NI 9469 generates the required oversample clock for
delta-sigma modules and routes it to both the local CompactRIO chassis and any other CompactRIO chassis connected by an NI
9469. It can also be used to send digital triggers and clocks for on-demand modules much like other digital I/O modules.
The following example uses the NI 9469 to synchronize NI delta-sigma devices within two CompactRIO systems. One system is
configured as a master while the other is configured as a slave. This example can be found in the Example Finder by going into
LabVIEW and navigating to Hardware Input and Output >> CompactRIO >> Module Specific >> Synchronization >>NI 9469
Getting Started.lvproj.

Synchronizing Multiple CompactRIO Chassis

1. After transitioning, each of the FPGA Vis will show broken wires. To resolve this, rename your modules and channels within
the project to match the names the VI uses, or re-associate the property, method, and IO nodes with the appropriate
channel or module within your project. Right-click the property and method nodes and select Select Item, then navigate to
the appropriate channel or module. Reconfigure IO nodes can be by left clicking and choosing the appropriate channel.
2. Move and recompile the FPGA Vis, and then configure the Open FPGA VI References to used the appropriate master and
slave FPGA VIs.
3. Run the NI 9469 Getting Started (Host) VI.

Time Referenced Synchronization

Time referenced synchronization shares a common time reference across a system, which you can use to correlate
measurements. The time reference can be a GPS, IEEE 1588, IRIG or a Pulse per Second (PPS) signal. These time references
provide a good level of synchronization and can be distributed across very large distances. Use a digital module, such as the NI
9402 (http://sine.ni.com/nips/cds/view/p/lang/en/nid/208810), to accept signals like IRIG and PPS. Use the NI 9467 (
http://sine.ni.com/nips/cds/view/p/lang/en/nid/210834) to accept GPS signals. Use LabVIEW FPGA and the CompactRIO system
to synchronize the FPGA clocks on chassis in your system to correlate all measurements to a single time reference.
Note: IEEE 1588 does not use a digital module but is implemented through the Ethernet port.
Simplify timing and synchronization tasks with the NI TimeSync: FPGA Timekeeper API, a set of Vis, libraries, and examples you
can use to synchronize your system to GPS, PPS, or RT clock. The FPGA Timekeeper also includes a metronome function to
generate a timing signal.
Note: The FPGA Timekeeper API is still in its lab (or beta) stage and is not yet a fully supported API.
Download the FPGA Timekeeper API from the NI-TimeSync: FPGA Timekeeper (
https://decibel.ni.com/content/projects/ni-timesync-fpga-timekeeper?view=overview) community site and launch /
examples/Synchronize to GPS - cRIO/Synchronize to GPS - cRIO.lvproj for an example demonstrating how to synchronize the
time used by the FPGA clock to International Atomic Time (TAI).

Synchronize Your NI CompactRIO Chassis over GPS

1. After transitioning, each of the FPGA Vis will show broken wires. To resolve this, rename your modules and channels within
the project to match the names the VI uses, or re-associate the property, method, and IO nodes with the appropriate
channel or module within your project. Right-click the property and method nodes and select Select Item, then navigate to
the appropriate channel or module. Reconfigure IO nodes can be by left clicking and choosing the appropriate channel.
2. Compile and run the VI to synchronize the FPGA clock to TAI Time.

7. Communication
CompactRIO systems and C Series modules include many standard communication protocols, which vary from serial and
Ethernet to industrial protocols like PROFIBUS and MODBUS. However, these standard protocols can be limited in their ability to
communicate to devices that use different protocols or connectors. A CompactRIO system allows you to still communicate with
these devices, using a digital module and LabVIEW FPGA.

Figure 8 - Implement the SPI Communication Protocol Using LabVIEW and LabVIEW FPGA
Refer to Understanding the SPI Bus with NI LabVIEW (http://www.ni.com/white-paper/9119/en/) for a deeper explanation of this
protocol, and Implementing SPI Communication Protocol in LabVIEW FPGA (http://www.ni.com/white-paper/9117/en) for a
detailed example of how to implement the SPI bus protocol using LabVIEW FPGA.

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8. Custom Triggering
Triggering is an essential feature in any data acquisition or control system. Use triggering for synchronization, alarms, or
startup/shutdown tasks. However standard trigger functions do not offer custom functionality, such as the ability to use multiple
input triggers or to trigger off of either edge or both edges. Use FPGA with a CompactRIO system to create custom triggering
applications.
Refer to Creating Triggers and Counters (FPGA Module) (
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/customizing_i_o/) for an example of how to generate a
trigger only when a digital pattern occurs.

Figure 9 – Generate a Trigger only when a Digital Pattern Occurs

9. Next Steps
Watch short videos on Writing Your First LabVIEW FPGA Program (http://www.ni.com/tutorial/14532/en/)
Learn how to Simplify System Design (http://www.ni.com/simplify-system-design/) with the CompactRIO platform.

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