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Proyecto Parte 1

This document describes a VHDL code for a traffic light controller. It defines the ports for a clock input, count input, and outputs for three traffic lights (q, y) and four street signals (a). The code contains a process that uses a case statement to set the output signals based on the count value, implementing the timing and sequences for a standard traffic light cycle.

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Carlos Daniel Amezquita Becerra
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30 views2 pages

Proyecto Parte 1

This document describes a VHDL code for a traffic light controller. It defines the ports for a clock input, count input, and outputs for three traffic lights (q, y) and four street signals (a). The code contains a process that uses a case statement to set the output signals based on the count value, implementing the timing and sequences for a standard traffic light cycle.

Uploaded by

Carlos Daniel Amezquita Becerra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity semaforo is
port(
clk: in bit;
count: in std_logic_vector(7 downto 0);
q: out std_logic_vector(2 downto 0);--semaforo E O || R A V
y: out std_logic_vector(2 downto 0);--semaforo N S || R A V
a: out std_logic_vector(3 downto 0));--Calles
end semaforo;

architecture arc of semaforo is


begin
process(clk)
begin
if clk'event and clk = '1' then
case count is
when X"00" => q <= "001"; y <= "100"; a <= "0000";--1
when X"01" => q <= "010"; y <= "100"; a <= "0000";--1 AMARILLO

when X"02" => q <= "100"; y <= "001"; a <= "0001";--6


when X"03" => q <= "100"; y <= "001"; a <= "0010";--6
when X"04" => q <= "100"; y <= "001"; a <= "0011";--6

when X"05" => q <= "100"; y <= "010"; a <= "0100";--2


when X"06" => q <= "001"; y <= "100"; a <= "0100";--2

when X"07" => q <= "001"; y <= "100"; a <= "0101";--5 E O verde 20 seg
when X"08" => q <= "001"; y <= "100"; a <= "0101";--5
when X"09" => q <= "001"; y <= "100"; a <= "0101";--5
when X"0A" => q <= "001"; y <= "100"; a <= "0101";--5
when X"0B" => q <= "001"; y <= "100"; a <= "0101";--5
when X"0C" => q <= "001"; y <= "100"; a <= "0101";--5
when X"0D" => q <= "001"; y <= "100"; a <= "0101";--5
when X"0E" => q <= "001"; y <= "100"; a <= "0101";--5
when X"0F" => q <= "001"; y <= "100"; a <= "0101";--5
when X"10" => q <= "001"; y <= "100"; a <= "0101";--5
when X"11" => q <= "001"; y <= "100"; a <= "0101";--5
when X"12" => q <= "001"; y <= "100"; a <= "0101";--5
when X"13" => q <= "001"; y <= "100"; a <= "0101";--5
when X"14" => q <= "001"; y <= "100"; a <= "0101";--5
when X"15" => q <= "001"; y <= "100"; a <= "0101";--5
when X"16" => q <= "001"; y <= "100"; a <= "0101";--5
when X"17" => q <= "001"; y <= "100"; a <= "0101";--5
when X"18" => q <= "001"; y <= "100"; a <= "0101";--5
when X"19" => q <= "001"; y <= "100"; a <= "0101";--5
when X"1A" => q <= "001"; y <= "100"; a <= "0101";--5
when X"1B" => q <= "010"; y <= "100"; a <= "0101";--5 AMARILLO
when X"1C" => q <= "100"; y <= "001"; a <= "0101";--5 N S verde 5 seg
when X"1D" => q <= "100"; y <= "001"; a <= "0101";--5
when X"1E" => q <= "100"; y <= "001"; a <= "0101";--5
when X"1F" => q <= "100"; y <= "001"; a <= "0101";--5
when X"20" => q <= "100"; y <= "001"; a <= "0101";--5

when others => q <= "000"; y <= "000"; a <= "0000";


end case;
end if;
end process;

end arc;

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