How-to: Programmable logic devices (CPLD)

Complex
programmable logic
devices (CPLDs)
contain the building
blocks for hundreds of
7400-serries logic ICs.
Complete circuits can
be designed on a PC
and then uploaded to a
CPLD for instant
implementation. A
microcontroller
connected to a
CPLD is like a
microcontroller
paired with a reprogrammable circuit board and a fully stocked electronics store.

At first we weren’t sure of the wide appeal and application of CPLDs in hobbyist projects, but we’ve been
convinced. A custom logic device can eliminate days of reading datasheets, finding the ideal logic IC
combination, and then waiting for chips to arrive. Circuit boards are simpler with CPLDs because a single
chip with programmable pin placement can replace 100s of individual logic ICs. Circuit mistakes can be
corrected by uploading a new design, rather than etching and stuffing a new circuit board. CPLDs are
fast, with reaction times starting at 100MHz. Despite their extreme versatility, CPLDs are a mature
technology with chips starting at $1.

We’ve got a home-etchable, self programming development board to get you started. Don’t worry, this
board has a serial port interface for working with the CPLD, and doesn’t require a separate (usually
parallel port) JTAG programmer.

Intro to CPLDs

When to use a CPLD

Consider using a CPLD when a design calls for more than one 7400 series logic ICs. A CPLD will be
cheaper, faster, and can be programmed with your ideal pin-out configuration for simpler PCBs.
How-to: Programmable logic devices (CPLD)

Use a CPLD in tricky designs that might require several iterations. It’s easier to design a new circuit in
software and upload it to the CPLD than it is to design, etch, and stuff a new circuit board.

For maximum speed and instant response, choose a CPLD. The difference in speed is amazing; CPLDs
start at a 100MHz, while microcontrollers respond to interrupts at a few MHz. CPLD designs form circuits
that react to external stimulus, reactions occur almost instantaneously. A microcontroller executes code to
react to events, even interrupt routines have comparatively high latency.

CPLD vs FPGA

FPGAs are better known than CPLDs, but they share many characteristics. This analogy isn’t perfect, but
we like it: where FPGAs are a reprogrammable processor core, a CPLD is a reprogrammable circuit
board or breadboard. FPGAs replace microcontrollers, memory, and other components. CPLDs absorb
logic ICs, and work well with a microcontroller.

Manufacturers

Altera and Xilinx, the biggest CPLD manufacturers, are better known for their FPGAs. Lattice
Semiconductor is another large CPLD manufacturer with less community following. Atmel makes pin-
compatible versions of old industry-standard CPLDs.

If you plan to work at 5volts, your options are limited. Xilinx XC9500 CPLDs are still available as new old
stock, but cost four times more than newer 3.3volt equivalents. Atmel’s ATF1502 series works at 5volts,
but they don’t offer a free development environment.

At 3.3volts there’s more options, but new CPLDs increasingly have a core that runs at 2.5volts, 1.8volts,
or lower. The Altera MAXII and the Xilinx XC9500XL series are probably the most popular 3.3volt CPLDs.
Xilinx also makes the CoolrunnerII CPLD, but it only comes in a TQFP package and requires a separate
1.8volt supply for the core.

Packages

Most manufacturers offer one or two CPLDs in a hobbyist friendly PLCC 44 package, though this is
starting to disappear. PLCC is an SOIC-sized surface mount chip with pins on all four sides. PLCC44
sockets are commonly available in through-hole and SMD versions. Unfortunately, newer CPLD families
are starting to eliminate the PLCC package and offer only 44 pin and larger TQFP chips, such as Xilinx’s
CoolrunnerII.

Development environments

Most manufacturers offer a free development environment that supports design entry using simple
schematics, as well as Verilog or VHDL. Many won’t support the latest FPGAs in the free version, but we
only need the CPLD parts anyway. Altera has Quartus, Xilinx has ISE, and Lattice has ispLever. Atmel
has ProChip Designer for the ATF15xx series, but they only offer a 6month trial license — which they
wouldn’t actually give us.

Programmers

The development board we present doesn’t need a separate JTAG programmer because the PIC
microcontroller already programs the CPLD. If you want an external programmer, the cheapest are the
parallel port programmers: Parallel Cable III for Xilinx and BytleBlaster for Altera. Inexpensive clones, and
schematics, are available at SparkFun. The OpenOCD is a generic USB JTAG programmer that will work
with many CPLDs, FPGAs, and ARMs.
How-to: Programmable logic devices (CPLD)

Our choice

We eventually settled on the Xilinx XC9500XL series because it had a cheap development kit we could
use to test our JTAG programmer prior to implementing an entire design.

The DO-CPLD-DK from Digilent includes a XC9572XL, a CoolrunnerII, and parallel port programmer. Nu
Horizons has some old non-ROHS models for $40, but due to sloppy variable type handling in their credit
card processing scripts, we couldn’t complete an order online. We tried to do it over the phone but they
refused to take such a small order on the phone, even during a website malfunction. In the end, it was
cheaper to pay full price at Digikey (#122-1512-ND) after including New Horizon’s exorbitant shipping
charges. We wouldn’t normally mention this, but with only two places to buy the board it’s probably worth
noting our experience.

CPLD development board

Click here for a full size schematic image (PNG). The circuit and PCB are designed using the freeware
version of Cadsoft Eagle. All the files for this project are included in the project archive linked at the end of
the article.

Circuit

A PIC 24FJ64GA002 microcontroller (IC1) provides the user and programming interface to the CPLD. We
use this $4 PIC in a lot of projects because the peripheral pin select feature makes board routing really
easy. Check out our introduction to the PIC24F for more details. The PIC needs to communicate with a
PC serial port, so we added an inexpensive MAX3232 RS232 transceiver. The serial interface should
work with a USB->serial adapter.

Our choice of CPLD (IC3), a Xilinx XC9572XL (PDF), is connected between the PIC and several other
components. We can create an endless variety of circuitry between the PIC and other chips using the
reprogrammable logic inside the CPLD. The PIC will program the CPLD with code sent from a PC serial
port, but we still brought the JTAG pins to a header for easy external debugging.

A DS1085 digital programmable oscillator (IC4) generates clock frequencies between 8KHz and 133MHz,
at 10KHz increments. This is very similar to the DS1077 we covered earlier, but it has even steps
between all frequencies. The DS1085 requires a 5volt supply (VR2). The I2C interface also runs at 5volts,
so we connected it to 5volt tolerant PIC pins. It’s possible to use the 3.3volt 66MHz 1085L instead, and
remove the 5volt supply.

We used a cheap 3.3volt SOT223 voltage regulator (VR1) to power most of the circuit. The 5volt supply
(VR2) can be excluded if you use a slower 1085L 3.3volt oscillator.
How-to: Programmable logic devices (CPLD)

CPLDs are commonly used as a memory controller, so we included 32K of SRAM (IC5) on the
development board. A 3.3volt latch with 5volt tolerant inputs interface the memory inputs to a wide range
of external voltages (IC6). The latch inputs are held low with a 1Mohm resistor network (RN1). We’ll
discuss this section extensively in an upcoming article.

PCB

The board is a quasi one-sided design. We made several compromises so we could prototype this highly
experimental PCB ourselves. We present the board ‘as is’ for other die-hards that might want to etch this
board at home. If you send the PCB to a board house, try to correct these issues prior to producing a
‘real’ double-sided board.

One power pin of the CPLD is missing a decoupling capacitor entirely; there was no way to put a
capacitor in that area. One CPLD decoupling capacitor, and the SRAM decoupling capacitor, are through-
hole parts. Using these through-hole parts eliminated a few jumper wires.

The jumper wires on the back of the board are optimized for single-sided production, rather than good
design practices. We faked a double-sided board by soldering the power bus on the back. A real double-
sided board design should route the power bus to avoid crossing signal paths, and include the missing
decoupling capacitors.

We used an surface mount PLCC chip socket, but a through-hole version is definitely a better idea. We
though the SMD version would be easy to solder, but it turned out to be a nightmare. We really wanted
the CPLD to be on the front of the board for the coolest possible presentation. A proper two-sided board
with plated through-holes can have a through-hole socket on the front, but this wasn’t possible with our 1-
sided prototype board.

Parts list

Click here for a full size placement diagram (PNG).

Part Value
IC1 PIC25FJ64GA002 (SOIC)
IC2 MAX3232CSE (SOIC-N)
IC3 XC9572XL-10PCG44C (PLCC)
How-to: Programmable logic devices (CPLD)

– PLCC44 socket, SMD

IC4 DS1085 or DS1085L (SOIC)
IC5 32Kx8, 3.3v, SRAM (SOJ)
IC6 74LVT573D (SOIC)
VR1 3.3v regulator, LD1117S33 (SOT223)
VR2 5v regulator, LD1117S50 (SOT223)
C1-11,13-17 0.1uF decoupling capacitors (0805)
C12 0.01uF capacitor (0805)
C15,16 0.1uF decoupling capacitors (through-hole)
C18 10uF tantalum capacitor (A)
R1,2 390ohm resistor (0805)
R3-5 2000ohm resistor (0805)
RN1 1Mohm resistor network (9 pin)
LED1,2 LED (0805)
X1 db9 female serial port connector *untested
J1 2.1mm power jack
ICSP, JTAG, SV1 0.1″ pin header, right angle
S1 Tactile switch (DTSM-6)

Firmware

The firmware is written in C using the free demonstration version of the PIC C30 compiler. Learn all about
working with this PIC in our introduction to the PIC 24F series. The firmware is included in the project
archive at the end of the article.

We wanted a super easy way to interact with the hardware on the board without endless compile-
program-test cycles. We made a custom version of the Bus Pirate firmware that provides a simple ASCII
terminal interface to the DS1085 clock chip (I2C), the CPLD programing interface (JTAG), and a 3 wire
(SPI) interface to the CPLD. Check out the Bus Pirate tutorial for background on the simple syntax used
with the firmware.

The original Bus Pirate firmware handles several protocols that share the same pins. For the CPLD
version, we changed the pin assignments to fit the connections on the development board. We also
removed unused modules and options.

CPLD blinky LED examples

We prepared several designs in Xilinx’s ISE development environment. The schematics, pin placement
files, and compiled designs (XSVF) are included in the project archive linked at the end of the article. A
full explanation of ISE is beyond the scope of this article; we found the help files sufficiently useful to
make these examples.

The first design simply lights the LED connected to pin 8 of the CPLD.

Prepare the XSVF file

XSVF is a compressed JTAG programming format, as described by Xilinx in this application note (PDF).
XSVF isn’t limited to programming Xilinx devices, and can be prepared for any chip that provides a
common BSDL JTAG definition file.
How-to: Programmable logic devices (CPLD)

Open the iMPACT programming tool from the ISE Design Suite project panel under Configure target
device->iMPACT.

 Choose the option to create a boundary scan file, and set the type to XSVF.
 Give the XSVF output a file name and then add a compiled CPLD image (ex1.jed) when
prompted to add a device.
 You should see a JTAG chain that contains a single device.

Click on the device and choose program; iMPACT will record the programming sequences to an XSVF
file.

With XSVF file in hand, it’s time to open up a terminal and program the CPLD. We like Tera Term and
Hercules on Windows. You must enable XON/XOFF flow control in the client to use the JTAG interface.
The default PC side setting for the development board terminal is 115200bps, 8N1.

HiZ>m <–select mode

1. HiZ

2. I2C

3. JTAG

4. RAW3WIRE

MODE>3 <–JTAG

900 MODE SET

602 JTAG READY

JTAG>(2) <–probe JTAG chain macro

xxx JTAG INIT CHAIN

xxx JTAGSM: RESET

xxx JTAGSM: RESET->IDLE

xxx JTAGSM: IDLE->Instruction Register (DELAYED ONE BIT FOR TMS)

xxx JTAGSM: IR->IDLE

xxx JTAGSM: IDLE->Data Register

xxx JTAGSM: DR->IDLE

xxx JTAGSM: RESET

xxx JTAGSM: RESET->IDLE

How-to: Programmable logic devices (CPLD)

xxx JTAGSM: IDLE->Data Register

xxx JTAG CHAIN REPORT:

0×01 DEVICE(S)

#0×01 : 0xC9 0×02 0×06 0×9A <–XC9572XL responds

xxx JTAGSM: DR->IDLE

JTAG>

In the terminal we enter the mode menu (m), and choose JTAG (3). Macro 2 probes the JTAG chain, in
our case this is just the CPLD. The chain report tells us that the chip is connected and responding. Read
more about the JTAG interface.

Now we can run the XSVF programmer, macro (3), and upload the XSVF file from the terminal in binary
mode. The first example just lights the LED on pin 8. If the LED lights, we can verify that programming
was successful. If your LED doesn’t light, don’t despair; sometimes the JTAG programmer sticks and a
reset macro (1) will get the chip going.

LED at full brightness.

74LS32/4071 OR gate, blink at half rate (/2)

A major component of the CPLD development board is the 1085(L) frequency synthesizer connected to
pin 7 of the CPLD. The next example uses a logic OR gate, like a 74LS32 or 4071 IC, to blink the LED
whenever the clock signal is high. At even the slowest clock rate the blinking will be too fast to see, but
we should get a nice PWM dimming effect compared to the first example.

JTAG>m <–select mode

1. HiZ
How-to: Programmable logic devices (CPLD)

2. I2C

3. JTAG

4. RAW3WIRE

MODE>2 <–I2C interface to DS1085

900 MODE SET

202 I2C READY

I2C>(1) <–address search macro

xxx Searching 7bit I2C address space.

Found devices at:

0xB0 0xB1 <–found the DS1085 address

I2C>

Program the CPLD as before, and then switch to I2C mode to access the DS1085 clock. We could look
up the device address in the datasheet, but we save a few seconds by running the address search macro;
the report tells us the chip answers to 0xb0 (write) and 0xb1 (read).

I2C>{0xb0 0×02 0b00011111 0b10000000}<–max prescaler

210 I2C START CONDITION

220 I2C WRITE: 0xB0 GOT ACK: YES

220 I2C WRITE: 0×02 GOT ACK: YES

220 I2C WRITE: 0×1F GOT ACK: YES

220 I2C WRITE: 0×80 GOT ACK: YES

240 I2C STOP CONDITION

I2C>{0xb0 1 0b11111111 0b11000000}<–max divider

210 I2C START CONDITION

220 I2C WRITE: 0xB0 GOT ACK: YES

220 I2C WRITE: 0×01 GOT ACK: YES

220 I2C WRITE: 0xFF GOT ACK: YES

220 I2C WRITE: 0xC0 GOT ACK: YES

How-to: Programmable logic devices (CPLD)

240 I2C STOP CONDITION

I2C>

The DS1085 is almost exactly like the DS1077 we covered earlier, but has a DAC controlled oscillator for
even steps between all frequencies. We programmed the clock to the slowest frequency using the
commands shown above. The LED is dimmed by the pulse-width modulation effect of the clock signal.

LED at half brightness.

74F269 16bit synchronous counter, blink slowly (/65535)

We just programmed the CPLD with a logic OR gate similar to a 74LS32. Now, we’re going to reprogram
the chip with a 16bit counter like two cascaded 74F269s. At $1.15 each, two 74F269 Ics are more
expensive than the XC9572XL CPLD. A 16bit counter rolls over once per 65535 ticks, so a LED attached
to the last bit will toggle once every 65535/2 ticks.

Now we can see the cool part of CPLDs. The CPLD is like a programmable breadboard; we just popped
out the 74LS32 and put in a 74F269, without buying parts, reading datasheets, etching, wiring, etc. A
microcontroller connected to a CPLD can reconfigure its own circuit board to fix errors, add features, or
re-purpose it for entirely different applications.

We upload the new design as before, but now the clock is divided by 65535 and the LED toggles about
once per second.

Taking it further

Next time we’ll look at discrete 7400-series logic chips, and implement a ton of them in the CPLD to make
a high-speed bus sniffer and logic analyzer.

Download: bitclone.v1.zip

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It's hard to figure out what our variety of XS Board products do if you don't understand what complex
programmable logic devices and field-programmable gate arrays are! This short tutorial will introduce
the main concepts of these types of chips.

In the beginning (OK, actually in the 60's) there was discrete logic. Systems were built from lots of
individual chips with a spaghetti-like maze of wiring between them. It was difficult to modify such a
system after you built it. Heck, after a week or two it was difficult to remember what each of the chips
was for!

Manufacturing such a system took a lot of time because each design change required that the wiring
be redone which usually meant building a new printed circuit board. The chip makers solved this
problem by placing an unconnected array of AND-OR gates in a single chip called a programmable
logic device (PLD). The PLD contained an array of fuses that could be blown open or left closed to
connect various inputs to each AND gate. You could program a PLD with a set of Boolean sum-of-
product equations so it would perform the logic functions you needed in your system. Since the PLDs
could be rewired internally, there was less of a need to change the printed circuit boards which held
them.
How-to: Programmable logic devices (CPLD)

Simple PLDs could only handle up to 10–20 logic equations, so you couldn't fit a very large logic
design into just one of them. You had to figure out how to break your larger designs apart and fit
them into a set of PLDs. This was time-consuming and meant you had to interconnect the PLDs with
wires. The wires were a big no-no because eventually you would make some design change that
couldn't be handled just by reprogramming the PLDs and then you would have to build a new circuit
board. The chip makers came to the rescue again by building much larger programmable chips called
complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). With
these, you could essentially get a complete system onto a single chip.

A CPLD contains a bunch of PLD blocks whose inputs and outputs are connected together by a global
interconnection matrix. So a CPLD has two levels of programmability: each PLD block can be
programmed, and then the interconnections between the PLDs can be programmed.

An FPGA takes a different approach. It has a bunch of simple, configurable logic blocks arranged in an
array with interspersed switches that can rearrange the interconnections between the logic blocks.
Each logic block is individually programmed to perform a logic function (such as AND, OR, XOR, etc.)
and then the switches are programmed to connect the blocks so that the complete logic functions are
implemented.

CPLD and FPGA manufacturers use a variety of methods to make the connections between logic
blocks. Some make chips with fuses or anti-fuses that are programmed by passing a large current
through them. These types of CPLDs and FPGAs are one-time programmable (OTP) because you can't
rewire them internally once the fuses are blown.
How-to: Programmable logic devices (CPLD)

Other manufacturers make the connections using pass transistors that are opened or closed by storing
a charge on their gate electrodes using a high-voltage pulse. This type of programmable device
resembles an EPROM or EEPROM: you can erase it and then place it in a special programmer socket
and reprogram it. That's fine unless you have the CPLD or FPGA soldered into a circuit board.

Finally, some manufacturers use static RAM or Flash bits to control the pass transistors for each
interconnection. By loading each bit with a 1 or a 0, you can control whether the switch is closed or
opened and, therefore, whether two logic elements are connected or not. CPLDs and FPGAs built using
RAM/Flash switches can be reprogrammed without removing them from the circuit board. They are
often said to be in-circuit reconfigurable or in-circuit programmable.

Regardless of the interconnection method used, you can see that figuring out which switches to open
and close in order to create a logic circuit would be quite a chore. That's why the chip manufacturers
provide development software that takes a description of the logic design as input and then outputs a
binary file which configures the switches in a CPLD or FPGA so that it acts like the design.

Implementing a logic design with the FPGA or CPLD development software usually consists of the
following steps (depicted in the figure below):

1. You enter a description of your logic circuit using a hardware description language (HDL) such
as VHDL or Verilog. You can also draw your design using a schematic editor.
2. You use a logic synthesizer program to transform the HDL or schematic into a netlist. The
netlist is just a description of the various logic gates in your design and how they are
interconnected.
3. You use the implementation tools to map the logic gates and interconnections into the FPGA.
The configurable logic blocks in the FPGA can be further decomposed into look-up tables that
perform logic operations. The CLBs and LUTs are interwoven with various routing resources.
The mapping tool collects your netlist gates into groups that fit into the LUTs and then the
place & route tool assigns the gate collections to specific CLBs while opening or closing the
switches in the routing matrices to connect the gates together.
4. Once the implementation phase is complete, a program extracts the state of the switches in
the routing matrices and generates a bitstream where the ones and zeroes correspond to open
or closed switches. (This is a bit of a simplification, but it will serve for the purposes of this
tutorial.)
5. The bitstream is downloaded into a physical FPGA chip (usually embedded in some larger
system such as an XS Board). The electronic switches in the FPGA open or close in response to
the binary bits in the bitstream. Upon completion of the downloading, the FPGA will perform
the operations specified by your HDL code or schematic. You can apply input signals to the I/O
pins of the FPGA to check the operation of your design.

That's really all there is to it. Software such as Xilinx Foundation or WebPACK provides the HDL and
schematic editors, logic synthesizer, fitter, and bitstream generator software. The XSTOOLs from XESS
provide utilities for downloading the bitstream into a CPLD or FPGA contained in an XS Board.
How-to: Programmable logic devices (CPLD)
How-to: Programmable logic devices (CPLD)

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In the world of digital electronic systems, there are three basic kinds of devices: memory, microprocessors, and logic.
Memory devices store random information such as the contents of a spreadsheet or database. Microprocessors
execute software instructions to perform a wide variety of tasks such as running a word processing program or video
game. Logic devices provide specific functions, including device-to-device interfacing, data communication, signal
processing, data display, timing and control operations, and almost every other function a system must perform.

Fixed Logic Versus Programmable Logic

Logic devices can be classified into two broad categories - fixed and programmable. As the name suggests, the
circuits in a fixed logic device are permanent, they perform one function or set of functions - once manufactured, they
cannot be changed. On the other hand, programmable logic devices (PLDs) are standard, off-the-shelf parts that offer
customers a wide range of logic capacity, features, speed, and voltage characteristics - and these devices can be
changed at any time to perform any number of functions.

With fixed logic devices, the time required to go from design, to prototypes, to a final manufacturing run can take from
several months to more than a year, depending on the complexity of the device. And, if the device does not work
properly, or if the requirements change, a new design must be developed. The up-front work of designing and
verifying fixed logic devices involves substantial "non-recurring engineering" costs, or NRE. NRE represents all the
costs customers incur before the final fixed logic device emerges from a silicon foundry, including engineering
resources, expensive software design tools, expensive photolithography mask sets for manufacturing the various
metal layers of the chip, and the cost of initial prototype devices. These NRE costs can run from a few hundred
thousand to several million dollars.

With programmable logic devices, designers use inexpensive software tools to quickly develop, simulate, and test
their designs. Then, a design can be quickly programmed into a device, and immediately tested in a live circuit. The
PLD that is used for this prototyping is the exact same PLD that will be used in the final production of a piece of end
equipment, such as a network router, a DSL modem, a DVD player, or an automotive navigation system. There are
no NRE costs and the final design is completed much faster than that of a custom, fixed logic device.

Another key benefit of using PLDs is that during the design phase customers can change the circuitry as often as
they want until the design operates to their satisfaction. That's because PLDs are based on re-writable memory
technology - to change the design, the device is simply reprogrammed. Once the design is final, customers can go
into immediate production by simply programming as many PLDs as they need with the final software design file.

CPLDs and FPGAs

The two major types of programmable logic devices are field programmable gate arrays (FPGAs) and complex
programmable logic devices (CPLDs). Of the two, FPGAs offer the highest amount of logic density, the most features,
and the highest performance. The largest FPGA now shipping, part of the Xilinx Virtex™ line of devices, provides
eight million "system gates" (the relative density of logic). These advanced devices also offer features such as built-in
hardwired processors (such as the IBM Power PC), substantial amounts of memory, clock management systems,
and support for many of the latest, very fast device-to-device signaling technologies. FPGAs are used in a wide
variety of applications ranging from data processing and storage, to instrumentation, telecommunications, and digital
signal processing.

CPLDs, by contrast, offer much smaller amounts of logic - up to about 10,000 gates. But CPLDs offer very
predictable timing characteristics and are therefore ideal for critical control applications. CPLDs such as the Xilinx
CoolRunner™ series also require extremely low amounts of power and are very inexpensive, making them ideal for
cost-sensitive, battery-operated, portable applications such as mobile phones and digital handheld assistants.

The PLD Market

Today the worldwide market for programmable logic devices is about $3.5 billion, according the market researcher
Gartner/Dataquest. The market for fixed logic devices is about $12 billion. However, in recent years, sales of PLDs
have outpaced those of fixed logic devices built with older gate array technology. And, high performance FPGAs are
now beginning to take market share from fixed logic devices made with the more advanced standard cell technology.
How-to: Programmable logic devices (CPLD)

According to the Semiconductor Industry Association, programmable logic is now one of the fastest growing
segments of the semiconductor business, and for the last few years, sales for PLDs have increased at a greater pace
than sales for the overall semiconductor industry.

Says EDN Magazine, a leading electronics design trade publication: "Programmable-logic devices are the fastest
growing segment of the logic-device family for two fundamental reasons. Their ever-increasing logic gate count per
device 'gathers up' functions that might otherwise spread over a number of discrete-logic and memory chips,
improving end-system size, power consumption, performance, reliability, and cost. Equally important is the fact that in
a matter of seconds or minutes you can configure and, in many cases, reconfigure these devices at your workstation
or in the system-assembly line. This capability provides powerful flexibility to react to last-minute design changes, to
prototype ideas before implementation, and to meet time-to-market deadlines driven by both customer need and
competitive pressures." (EDN, "Annual PLD Directory," August 17, 2000.)

The PLD Advantage

Fixed logic devices and PLDs both have their advantages. Fixed logic devices, for example, are often more
appropriate for large volume applications because they can be mass-produced more economically. For certain
applications where the very highest performance is required, fixed logic devices may also be the best choice.

However, programmable logic devices offer a number of important advantages over fixed logic devices, including:

 PLDs offer customers much more flexibility during the design cycle because design iterations are simply a
matter of changing the programming file, and the results of design changes can be seen immediately in
working parts.
 PLDs do not require long lead times for prototypes or production parts - the PLDs are already on a
distributor's shelf and ready for shipment.
 PLDs do not require customers to pay for large NRE costs and purchase expensive mask sets - PLD
suppliers incur those costs when they design their programmable devices and are able to amortize those
costs over the multi-year lifespan of a given line of PLDs.
 PLDs allow customers to order just the number of parts they need, when they need them, allowing them to
control inventory. Customers who use fixed logic devices often end up with excess inventory which must be
scrapped, or if demand for their product surges, they may be caught short of parts and face production
delays.
 PLDs can be reprogrammed even after a piece of equipment is shipped to a customer. In fact, thanks to
programmable logic devices, a number of equipment manufacturers now tout the ability to add new features
or upgrade products that already are in the field. To do this, they simply upload a new programming file to
the PLD, via the Internet, creating new hardware logic in the system.

Over the last few years programmable logic suppliers have made such phenomenal technical advances that PLDs
are now seen as the logic solution of choice from many designers. One reasons for this is that PLD suppliers such as
Xilinx are "fabless" companies; instead of owning chip manufacturing foundries, Xilinx out sources that job to partners
like IBM Microelectronics and UMC, whose chief occupation is making chips. This strategy allows Xilinx to focus on
designing new product architectures, software tools, and intellectual property cores while having access to the most
advanced semiconductor process technologies. Advanced process technologies help PLDs in a number of key areas:
faster performance, integration of more features, reduced power consumption, and lower cost. Today Xilinx is
producing programmable logic devices on a state-of-the-art 0.13-micron low-k copper process - one of the best in the
industry.

Just a few years ago, for example, the largest FPGA was measured in tens of thousands of system gates and
operated at 40 MHz. Older FPGAs also were relatively expensive, costing often more than $150 for the most
advanced parts at the time. Today, however, FPGAs with advanced features offer millions of gates of logic capacity,
operate at 300 MHz, can cost less than $10, and offer a new level of integrated functions such as processors and
memory.

Just as significant, PLDs now have a growing library of intellectual property (IP) or cores - these are predefined and
tested software modules that customer can use to create system functions instantly inside the PLD. Cores include
everything from complex digital signal processing algorithms and memory controllers to bus interfaces and full-blown
software-based microprocessors. Such cores save customers a lot of time and expense --it would take customers
months to create these functions, further delaying a product introduction.
How-to: Programmable logic devices (CPLD)

Conclusion

The value of programmable logic has always been its ability to shorten development cycles for electronic equipment
manufacturers and help them get their product to market faster. As PLD suppliers continue to integrate more
functions inside their devices, reduce costs, and increase the availability of time-saving IP cores, programmable logic
is certain to expand its popularity with digital designers.

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