DE Module 2
DE Module 2
Logic Gates
Overview
Introduction
Logical Operators
Basic Gates
Universal Gates
Realization of Basic Gates using Universal Gates
Other Logic Gates
Introduction
AND OR NOT
0·0=0 0+0=0 0=1
0·1=0 0+1=1 1= 0
1·0=0 1+0=1
1·1=1 1+1=1
Truth Tables
Truth table - a tabular listing of the values of a function for all possible combinations of values
on its arguments
Example: Truth tables for the basic logic operations:
AND OR NOT
X Y Z = X·Y X Y Z = X+Y X Z = ̅X
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1
Logic Function Implementation
A NOT gate accepts one input signal (0 or 1) and returns the opposite signal as output
AND Gate
NAND gates are sometimes called universal gates because they can be used to
produce the other basic Boolean functions.
A A A AB
B
Inverter AND gate
A A
A+B A+B
B B
NOR gates are also universal gates and can form all of the basic gates.
A A A A+ B
B
Inverter OR gate
A A
AB AB
B B
XNOR X Y Z
X
Z 0 0 1
Y
0 1 0
1 0 0
1 1 1
Constructing Gates
Transistor
A device that acts either as a wire that conducts electricity or as a resistor that blocks the
flow of electricity, depending on the voltage level of an input signal
A transistor has no moving parts, yet acts like a switch
It is made of a semiconductor material, which is neither a particularly good conductor of
electricity nor a particularly good insulator
A transistor has three terminals
A source
A base
An emitter, typically connected to a ground wire
If the electrical signal is grounded, it is allowed to flow through
an alternative route to the ground (literally) where it can do
no harm
AND Gate OR Gate
Timing Diagram
t0 t1 t2 t3 t4 t5 t6
1
Input A 0
1 Transitions
signals B 0
1
F=A•B 0 Basic
Gate
1 Assumption:
Output G=A+B 0 Zero time for
Signals 1
H=A’ 0
signals to
propagate
Through gates
Gate Delay
In actual physical gates, if one or more input changes causes the output to change, the
output change does not occur instantaneously.
The delay between an input change(s) and the resulting output change is the gate delay
denoted by tG:
1
Input
0
tG tG tG = 0.3 ns
1
Output
0
Boolean Algebra
Overview
Introduction
Boolean Algebra
Properties
Algebraic Manipulation
De-Morgan Theorem
Complementation
Truth Table
Introduction
Understand the relationship between Boolean logic and digital computer circuits.
Learn how to design simple logic circuits.
Understand how digital circuits work together to form complex computer systems.
In the latter part of the nineteenth century, George Boole suggested that logical
thought could be represented through mathematical equations.
Computers, as we know them today, are implementations of Boole‟s Laws of
Thought.
In this chapter, you will learn the simplicity that constitutes the essence of the
machine (Boolean Algebra).
Boolean algebra
Truth Logic
Table Circuit
Digital computers contain circuits that implement Boolean functions.
The simpler that we can make a Boolean function, the smaller the circuit
that will result.
Simpler circuits are cheaper to build, consume less power, and run faster
than complex circuits.
With this in mind, we always want to reduce our Boolean functions to their
simplest form.
There are a number of Boolean identities that help us to do this.
Properties of Boolean Algebra
as follows:
With respect to duality, Identities 1 – 8 have the following
relationship:
1. X + 0 = X 2. X • 1 = X (dual of 1)
3. X + 1 = 1 4. X • 0 = 0 (dual of 3)
5. X + X = X 6. X • X = X (dual of 5)
7. X + X’ = 1 8. X • X’ = 0 (dual of 8)
Algebraic Manipulation
G = F’ = (xy’z’ + x’yz)’
= (xy’z’)’ • (x’yz)’ DeMorgan
= (x’+y+z) • (x+y’+z’) DeMorgan again
Introduction
SOP and POS
Minterms and Maxterms
Canonical Forms
Conversion Between Canonical Forms
Standard Forms
Introduction
Canonical Sum-Of-Products:
The minterms included are those mj such that F( ) = 1 in row j of the truth table for F( ).
Canonical Product-Of-Sums:
The maxterms included are those Mj such that F( ) = 0 in row j of the truth table for F( ).
Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared in
the original form with those that do not.
Example:
f1(a,b,c) = a‟b‟c + a‟bc‟ + ab‟c‟ + abc‟
= m1 + m2 + m4 + m6
= ∑(1,2,4,6)
= ∏(0,3,5,7)
= (a+b+c)•(a+b‟+c‟)•(a‟+b+c‟)•(a‟+b‟+c‟)
F = XY Z XYZ XY Z XYZ = m0 m2 m5 m7 = m(0, 2, 5, 7)
F = XY Z XYZ XY Z XYZ = m1 m3 m4 m6 = m(1, 3, 4, 6)
F = m1 m3 m4 m6
F = m1 m3 m4 m6 = m1 m3 m4 m6
F = M 1 M 3 M 4 M 6 = ( X Y Z )( X Y Z )( X Y Z )( X Y Z )
= M (1, 3, 4, 6)
Standard Forms
• Standard forms are “like” canonical forms, except that not all
variables need appear in the individual product (SOP) or sum
(POS) terms.
• Example:
f1(a,b,c) = a‟b‟c + bc‟ + ac‟
is a standard sum-of-products form
• f1(a,b,c) = (a+b+c)•(b‟+c‟)•(a‟+c‟)
is a standard product-of-sums form.
Conversion of SOP from standard to canonical form
Minimization Techniques
Overview
Introduction
Karnaugh Map (K-Map)
Simplification Rules
K-Map Simplification for Two Variables
K-Map Simplification for Three Variables
K-Map Simplification for Four Variables
Don‟t Care Conditions
Redundancy
Design of Combinational Circuits
Introduction
Truth Boolean
Table Function
Truth
Table
Simplified
Karnaugh Boolean
Map Function
Boolean
function
Karnaugh Map (K-Map)
2-variable Karnaugh maps are trivial but can be used to introduce the
methods you need to learn. The map for a 2-input OR gate looks like this:
A
A 0 1
Y B
B
0 1
A
A B Y 1 1 1
0 0 0
0 1 1 B
1 0 1
1 1 1 A+B
K-Map Simplification for Three Variables
Its K-map is shown below. There are (only) two groupings of 1s.
Can you find them?
In this K-map, we see an example of a group that wraps around the
sides of a K-map.
f = (0,4) = B C f = (4,5) = A B f = (0,1,4,5) = B f = (0,1,2,3) = A
BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1
1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0
f = ∑ (1,3) = A’C
f = (0,4) = A C f = (4,6) = A C f = (0,2) = A C f = (0,2,4,6) = C
BC BC BC BC
A 00 01 11 10 A 00 01 11 10 A 00 01 11 10 A 00 01 11 10
0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1
1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1
K-Map Simplification for Four Variables
CD CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
00 0 0 1 1 00 0 0 0 0 00 0 0 1 1 00 1 0 0 1
01 0 0 1 1 01 1 0 0 1 01 0 0 0 0 01 0 0 0 0
11 0 0 0 0 11 1 0 0 1 11 0 0 0 0 11 0 0 0 0
10 0 0 0 0 10 0 0 0 0 10 0 0 1 1 10 1 0 0 1
CD CD CD CD
AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10 AB 00 01 11 10
00 0 1 1 0 00 1 0 0 1 00 0 0 0 0 00 1 1 1 1
01 0 1 1 0 01 1 0 0 1 01 1 1 1 1 01 0 0 0 0
11 0 1 1 0 11 1 0 0 1 11 1 1 1 1 11 0 0 0 0
10 0 1 1 0 10 1 0 0 1 10 0 0 0 0 10 1 1 1 1
Real circuits don‟t always need to have an output defined for every possible
input.
For example, some calculator displays consist of 7-segment LEDs. These
LEDs can display 2 7 patterns but all patterns are not used.
If a circuit is designed so that a particular set of inputs can never happen, we
call this set of inputs a don’t care condition.
They are very helpful to us in K-map circuit simplification.
In a K-map, a don‟t care condition is identified by an X in the cell of the
minterm(s) for the don‟t care inputs, as shown below.
In performing the simplification, we are free to include or ignore the X‟s
when creating our groups.
In one grouping in the K-map below, we have the function:
F = W’X’ + YZ
A different grouping gives us the function:
The truth table of:
F (W, X, Y, Z) = W’X’ + YZ
differs from the truth table of:
However, the values for which they differ, are the inputs for which we have
don‟t care conditions.
Redundancy
Design of combinational digital circuits
Example: Design a 3-input (A,B,C) digital circuit that will give at its
output (X) a logic 1 only if the binary number formed at the input has
more ones than zeros.
Inputs Output
A B C X X = (3, 5, 6, 7)
0 0 0 0 0
1 0 0 1 0 X
BC
2 0 1 0 0 A 00 01 11 10
3 0 1 1 1 0 0 0 1 0
4 1 0 0 0 1 0 1 1 1
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1 X = AC AB BC
A B C
Example: Design a 4-input (A,B,C,D) digital circuit that will give at its output (X) a
logic 1 only if the binary number formed at the input is between 2 and 9 (including).
Inputs Output
A B C D X X= (2,3,4,5,6 ,7,8,9)
0 0 0 0 0 0
1 0 0 0 1 0 X
2 0 0 1 0 1 CD
3 0 0 1 1 1 AB 00 01 11 10
4 0 1 0 0 1 00 0 0 1 1 Same
5 0 1 0 1 1
01 1 1 1 1
6 0 1 1 0 1
7 0 1 1 1 1 11 0 0 0 0
8 1 0 0 0 1 10 1 1 0 0
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0 X = AC AB A B C
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 0 A B C D X
Conclusion