Experiment 5 Lab Manual

American International University- Bangladesh (AIUB)

Faculty of Engineering (EEE)

Course Name: Digital Logic Design Lab Course Code: D0407

Semester: Spring 20-21 Sec: E
Lab Instructor: Naheed Hossain

Experiment No: 3
Experiment Name: Study of Universal Gates

Student Name: Shanin,Nafis Imtiaz Student ID: 17-35525-3

Group Members ID Name

1. 17-35499-3 Imon, A.N.M. Ahsanul Islam
2. 17-35663-3 Tanveer Md Tanjeem
3. 18-37405-1 Dibakar Barua
4. 18-36467-1 Ahmed, Shafin
5. 17-35834-3 Hasan,Md.Atik

Performance Date: Due Date:

Marking Rubrics (to be filled by Lab Instructor)

Proficient Good Acceptable Secured
Category Unacceptable [1]
[4] [3] [2] Marks
All information, All Information Most information
Theoretical Much information
measures and variables provided that is corrects, but some
Background, Methods missing and/or
are provided and sufficient, but more information may be
& procedures sections inaccurate.
explained. explanation is needed. missing or inaccurate.
Experimental results
All of the criteria are Most criteria are met,
don’t match exactly with
met; results are but there may be some Experimental results are
Results the theoretical values
described clearly and lack of clarity and/or missing or incorrect;
and/or analysis is
accurately; incorrect information.
unclear.
Demonstrates thorough Hypotheses are clearly Conclusions don’t match
Some hypotheses
and sophisticated stated, but some hypotheses, not
missing or misstated;
Discussion understanding. concluding statements supported by data; no
conclusions not
Conclusions drawn are not supported by data or integration of data from
supported by data.
appropriate for analyses; data not well integrated. different sources.
Title page, placement of
figures and figure
Minor errors in Major errors and/or
General formatting captions, and other Not proper style in text.
formatting. missing information.
formatting issues all
correct.
Writing is strong and
Writing is clear and easy
easy to understand; ideas Most of the required
to understand; ideas are
are fully elaborated and criteria are met, but
connected; effective
connected; effective some lack of clarity, Very unclear, many
Writing & organization transitions between
transitions between typographic, spelling, or errors.
sentences; minor
sentences; no grammatical errors are
typographic, spelling, or
typographic, spelling, or present.
grammatical errors.
grammatical errors.
Total Marks
Comments:
(Out of 20):

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 1

 Experiment 5 Lab Manual

Title: Design of a Half, Full and Parallel adder and subtractor circuits.

Introduction:
Adders and subtractors are digital circuits which are capable of adding and subtracting
binary digits. They are the most important part in the design of Arithmetic Logic Unit (ALU).
In this experiment different types of adders and subtractors will be designed and their
behavior will be observed.

Abstract:
The purpose of this lab experiment is to Design and verify half and full adder and subtractor
circuits. Also, with the help of truth table the verification of the simulation and practical of half
and full adder and subtractor circuits is done. This experiment helped us to understand how the
circuits for adding and subtracting works.

Theory and Methodology:

An adder or summer is a combinational circuit that adds binary numbers. There are mainly
two kinds of adders, half adder and full adder. The half adder can add only two single bits of
binary digit and outputs the sum of the bits and a carry which is the overflow of the sum. A
full adder can add two single bit digits and one carry bit which is the overflow of the sum of
the previous stage of addition and outputs the sum and the carry.

A
S
B
A
S Cin
B

C
C
Half Adder

Full Adder

Fig.1: Schematics of Half Adder and Full Adder

The Boolean expression for half and full adder is given below –

Half adder –

S=A B
C = AB

Full adder –

S = A B Cin
Cout = Cin (A B) + AB

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 2

 Experiment 5 Lab Manual

Truth table for half adder –

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Truth table for full adder –

A B Cin S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

A subtractor is also a combinational circuit that calculates the difference of two binary digits.
This is done by taking the two’s complement of the subtrahend and then adding it with the
minuend. So the subtractor circuit can be designed with the help of adder circuits. Like
adders, there are two types of subtractor circuits, half subtractor and full subtractor.

A half subtractor performs a subtraction between two single bits and produces their difference
and another output called borrow. A full subtractor performs a subtraction two single bits,
considering a borrow bit. It outputs the difference of the subtraction and a borrow bit.

Fig.2: Schematics of Half Subtractor and Full Subtractor

The Boolean expressions for half and full subtractor are given below –

Half subtractor –

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 3

 Experiment 5 Lab Manual

D=X Y
B = X’Y

Full subtractor –

D = X Y Bin
Bout = X’Y + X’Bin + YBin

Truth table for half subtractor –

X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Truth table for full subtractor –

X Y Bin D B
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Apparatus:

1. XOR Gates -IC 7486 3[pcs]

2. AND Gates - IC 7408 3[pcs]
3. NOT Gates -IC 7404 2[pcs]

Simulation and Measurement:

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 4

 Experiment 5 Lab Manual

Fig 3: Simulation of a half adder

Fig 4: Simulation of a Full adder

Fig 5: Simulation of a half subtractor

Fig 6: Simulation of a full subtractor

Results/ Findings:

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 5

 Experiment 5 Lab Manual

Using Fig 3 we found that the half adder can add values of one digit (0 to 9) it is also shown
in the truth table that if both A and B are 1 sum(S) = 0 and carry(C) = 1. Now coming to 2-
digit addition (01-99) it can be done using full adder so, if both A, B and Cin are 1 sum(S) =
1 and carry(C) = 1, simulation is shown in Fig 4.
Now coming to Subtractors, we found using the simulation in Fig 5 that the half subtractors
can subtract values of ones (1 to 9) it is also shown in the truth table that if A=1 and B= 0, the
Difference(D) =1 and Borrow(B) = 1. Now coming to 2-digit subtraction (00-99) it can be
done using full subtractor so, if A= 1, B and Bin= 0 Difference(D) = 1 and Borrow(B) = 0,
the simulation is shown in Fig 4.
Thus, by analyzing theoretical and practical data it can be said that both the data is same and
there are no discrepancies. Pin connections for all the ICs were studied. All the connections
were carefully made to avoid errors. The voltage supply was switched off during the
implementation. There was some problem during the experiment due to a faulty IC which
was replaced by a good one instantly. Finally, the experiment was successful both practically
comparing the value we got from the truth table and from what we found in the simulation.

Reference:

http://www.circuitstoday.com/half-adder-and-full-adder

© Dept. of EEE, Faculty of Engineering, American International University-Bangladesh (AIUB) 6