Exercise 3 - Summer Semester 2019

May 15, 2019

This document is part of the laboratory for the exam ”Fundamentals of

IC Deign”. It is for students attending the same-named lecture organized by
the Institute for Integrated Circuits of the TUHH. All information is supplied
without liability.

During this laboratory the simulation software LTSpice by Analog Devices

will be used.

Exercise 3 helps students understand how differential stages are designed with
a focus on designing an operational amplifier in the upcoming task. Once the
students have gained basic understanding on differential stages and simple
amplifier architectures, they should be able to design it on LTSpice for the
specifications provided in this documents. Upon successful implementation of
the design, students have to submit a report in the form of electronic letter.
Institute for Integrated Circuits
Prof. Dr.-Ing. Matthias Kuhl

In exercise 3 a differential stage will be designed as an input stage of the final operational
amplifier. In the beginning, an introduction to amplifier design and to different amplifier
architectures can be found. Those introduction tasks are not mandatory and should not
be part of your report. These subtasks give some step-by-step design approaches and
should improve your understanding of the dis-/advantages of different amplifier types to
guide you to the final approach.

Task 3 Introduction to amplifiers

Task 3.1 Common source amplifier with resistive load

As a first architecture, the common source amplifier with resistive load shown in Figure 1
is discussed.

Figure 1: Common source amplifier with resistive load.

The gain of this amplifier is given by

∆Vout ∂Vout
Av = = (1)
∆Vin ∂Vin

Using the saturation current equation

β
ID = (VGS − Vth )2 (2)
2
where β = β0 W
L
= µ Ctox
ox
The output voltage is given by Vout = VDD − ID R. With this, the
gain of CS amplifier can be written as Av = ∂V out
∂Vin
= −gm R.

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Subtask: Using the technology parameters provided in the below table, design a CS
amplifier that has a voltage gain Av = −20 dB at Vout = 900 mV and ID = 10 µA.

β0 (N M OS) 180 µA/V 2

β0 (P M OS) 60 µA/V 2
Vth (N M OS) 500 mV
Vth (P M OS) 700 mV
VGSef f 200 mV

Task 3.2 Common source amplifier with diode connected transistor

as load

The resistor R can be replaced with a diode connected PMOS transistor as shown in
Figure 2. The simplified equation to calculate the gain of this CS amplifier with diode
load is
gmn
Av = −gm rout = − (3)
gmp

Figure 2: Common source amplifier with diode connected load transistor.

Subtask: Calculate the W/L ratio for the diode connected transistor M2 to acheive the
same specifications as in the previous task.
Subtask: Draw the small signal model of the the CS amplifier shown in Figure 2 and
understand why & how the simplifications are made in equation 3.

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Task 3.3 Introduction to Differential Stage

In the next step we mirror the exact same transistors of the circuit in Fig. 2 as a second
amplification stage (Fig. 3).

Figure 3: Differential stage without biasing.

To build a symmetric circuit, the W/L ratios for M3 and M4 should be the same as for M2
an M1 respectively. First we assume the gate potential of M4 to be at the DC common
mode voltage VCM and the gate of M1 to be the input

Vin = VCM + vin (4)

with vin being the small signal input voltage
Subtask: Draw the small signal equivalent circuit of Fig. 3 and calculate its gain. Think
about if the resulting equation can be simplified by neglecting parts of the term.
Hints: What might be bigger: 1/gm or rds? How big is gm3 compared to gm2 ?
Take the same dimensions for the N- and PMOS transistors from the the previous task
and run an operating point simulation in order to verify the bias currents in both branches
are equal and the same as for the common source amplifier with diode load.
Also extract the necessary gm and rds values to calculate the DC gain with the derived
equation from the small signal equivalent circuit. In case you’re not able to get the
equation, use:

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rds4 rds3
A = gm1 (5)
rds4 + rds3

Next, run an ac simulation to simulate the amplifier gain. Make sure you plot Vout /Vin and
compare the simulated gain to your calculated result (Simulation results are in dB so make
sure you also calculate your gain the same way). Subtask: If your simulated maximum
frequency is high enough, you will see a drop in amplification at high frequencies. Where
does this come from?
Subtask: Also extract all the other necessary parameters that are needed to calculate
the exact gain without the applied simplifications. What do you think? Is the applied
simplification reasonable?

Figure 4: Differential stage without biasing (switched input node).

The circuit in Fig. 4 is equal to the one in Fig. 3, except the input and common mode
nodes have switched.
Subtask: Draw the small signal equivalent circuit of Fig. 4 and calculate its gain. How
big is the gain compared to the circuit in Fig. 3?
Hints: Use the simplified equation for the previous gain for the comparison. Whats the
value for gm1 compared to gm4 ?
After calculating the gain, perform an ac simulation also for this configuration and com-
pare your results to the previous one.
In a next step, increase the common mode voltage by 200 mV (Common mode, so both
input transistors) and run the operating point simulation again. Go through the operating

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conditions of each transistor and make sure the same bias current is flowing through both
branches and compare its value to the simulations for the previous common mode.
As you can see, the currents changed as well as the gm and rds for all the transistors. This
consequently leads to a change in the amplifiers gain due to the change in the common
mode, which should be obvious since the ID for all the transistors have been design for a
certain bias point.
To keep the gain of the amplifier constant over a wide common mode range, a simple
current source can be placed at the source potentials of M1 and M4 as shown in Fig. 5.
In the common mode the current splits up into both branches equally so that, in order to
have 20 µA in each branch, ISS has to be 40 µA.

Figure 5: Differential stage with ideal current source.

Subtask: Draw the small signal equivalent circuit assuming Vin+ to be a DC node and
Vin− to be your input transistor. Have you seen this circuit before?
In case you did no mistake, the small signal equivalent circuit should look the same as
the one for the circuit in Fig. 4. However, looking at the large signal behavior it can be
seen that the current through M1-M4 do not change with a change in the common mode
voltage so that the amplifier gain stays constant.
Verify your calculations by performing both a DC and AC analysis in LTSpice.

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Task 3.4 Differential Stage - Design Task

After the differential stage was introduced, the final architecture (Figure 6) has to be
designed. The specifications for your design are:
• CLoad = 10 pF
• Unity Gain Frequency (UGF) = 900 kHz
• Open-Loop Gain (ADC ) = 45 dB
• Input-Swing = 1 V → VDD − 900 mV
• Maximum Power Consumption including Beta Multiplier (Pmax ) = 200 µW
IMPORTANT:
• Your report should ONLY contain the design of the circuit in this task!
• In LTSpice: Make sure, if you have to connect the bulk to the source potential, that
a dot appears at the connection point!
• Always make sure your transistors are in saturation for this task.
• Make sure you always use the 350nm Models!
• To reach the Input-Swing specification you can’t design your transistors with VGS,eff
of 200 mV anymore. However, try to keep it as high as possible in case you want
to attend the Analog Lab next semester ;).

Figure 6: Differential stage to be designed in combination with the previously designed Beta-Multiplier.

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Hints:
• Start by thinking about how much current you can spend for the differential stage
to stay below the given Pmax
• Think about the Input-Swing: How much VGS,eff can you spend for M6/M5, M1/M4
and M2/M3 in order to fulfill the specifications? Then Design the current mirror.
• Calculate the gm for M1/M4, using the Unity Gain Frequency specification. There-
for use the simplified equation

gm = ωUG ∗ CLoad (6)

with ωUG being the Unity Gain Angular Frequency. For those of you who want to
dig more into this, draw the small signal equivalent circuit of M4 and M3 assuming
M5 to be an ideal current source and Vin+ to be on a DC potential. This time
consider the load capacitance.
• Calculate the W/L ratio for M1/M4 using the resulting gm
• Verify the Open-Loop Gain (using equation (5)). Is the chosen gm sufficient for
your design?
• Start again: Keep in mind that designing a circuit is an iterative process, so check
your simulation results and if you do not reach the specifications think about how
you can improve your results by e.g. giving some margins to your calculations.

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