ELEN0037

Microelectronic IC Design
Prof. Dr. Michael Kraft
 Lecture 2:
Technological Aspects
 Technology
– Passive components
– Active components
– CMOS Process
 Basic Layout
 Scaling
 CMOS Technology
 Integrated capacitive pressure sensor on
8“ wafer using surface micromachining
 → Integrated single chip solution

poly-gate membrane passivation

aluminum

n+- area p+ - area

n-well

PMOS NMOS capacitor EEPROM pressure sensor

 Passive Components
 Passive components:
– Resistors
• Diffused/implanted resistors
• Polysilicon resistors
– Capacitors

Aluminium
SiO2 n+

p-Substrate

n+ diffusion resistor Source: Allen, Holberg, „CMOS Analog Circuit Design“

 Fabrication n+ Diffusion Resistor
Fabrication process Mask layout
n+ - Implantation
Aluminium
SiO2 n+

p - Substrate
p-Substrate

Etch holes Oxide

 Diffusion Resistor:
– Source/Drain n+

diffusion p - Substrate

Aluminium

n+
p - Substrate
 n+ Diffusion Resistor
 Specific conductivity   q( nn  p p)
n  p
   q nn  q nND
 Resistance
𝜎: specific conductivity
𝜇𝑛 , 𝜇𝑝 : charge mobility
1𝐿 1 𝐿
𝑅= = 𝑋𝑗 : p-n junction depth
𝜎 𝐴 𝜎 ∙ 𝑋𝑗 𝑊
n,p: charge concentration
1 𝐿 𝐿
𝑅= : Geometry factor
𝑞𝜇𝑛 𝑁𝐷 𝑋𝑗 𝑊 𝑊
1 ND, NA: donor, acceptor concentration
𝑅∎ = 𝑞𝜇 =“Square Resistance“
𝑛 𝑁𝐷 𝑋𝑗

L
Aluminium
SiO2 n+

p-Substrate
Xj A
 n+ Diffusion Resistor
 Specific conductivity   q( nn  p p) L
n  p X
   q nn  q nND j A

 Resistance
𝜎: specific conductivity
𝜇𝑛 , 𝜇𝑝 : charge mobility
1𝐿 1 𝐿
𝑅= = 𝑋𝑗 : p-n junction depth
𝜎 𝐴 𝜎 ∙ 𝑋𝑗 𝑊
n,p: charge concentration
1 𝐿 𝐿
𝑅= : Geometry factor
𝑞𝜇𝑛 𝑁𝐷 𝑋𝑗 𝑊 𝑊
1 ND, NA: donor, acceptor concentration
𝑅∎ = 𝑞𝜇 =“Square Resistance“
𝑛 𝑁𝐷 𝑋𝑗

 Square resistance only depends on process parameters

– L=W → R□ = R
– Resistors are specified as multiples of their square resistance
L = 7W

R W

R = 7R
 n+ Diffusion Resistor
 Typical values for R□:
– Drain-source regions: 10..100 W/
– N-well: 1000…10000 W/
 Absolute values for diffusion resistors
– 𝑁𝐷 , 𝑋𝑗 , 𝜇𝑛 depend on process parameter
• Diffusion concentration
• Implantation dose
• Diffusion temperature
• Diffusion time
• etc
– W, L depend on lithography, etch process, lateral diffusion, etc
• Edge definition has tolerance of Δ𝐿, Δ𝑊 ≈ 0.1𝜇𝑚
– → high tolerance for absolute values of resistance, 10-50%

 For high resistance values, large areas are required

 Electrical Equivalent Model

RK ,A R0 RK ,B
A B

Aluminium
SiO2 n+

p-Substrate

Substrat

 Contact resistances (Rk) add to resistance value

 Parasitic diode (pn-junction) to substrate → leakage currents, voltage
dependent depletion layer capacitance,
 Resistor Matching
 How accurate can a resistor ratio be fabricated
 Example: R2 = 2 R1

R1 ND 2 X j 2 n 2 L1 W2 LW
    1 2
R2 ND1X j 1n1 L2 W1 L 2W 1
ND 2 X j 2 n 2 Depend on the process, so should be (pretty)
ND1X j 1n1 equal across a wafer L1
L1 W2 R1 W1
 Depend on the geometry
L 2 W1
L2

R2 W2

 If the resistors are fabbed in the same process,

 and are close together
 → process tolerances cancel out!
 → with “good” layout the matching can be better than 1‰
 → for circuit design better use ratios!
 Voltage Dependence Diffusion
Resistance
 Depletion zone width, Wn depends on junction reverse voltage bias, Vpn

Wn Xi
+
Vpn
- P-Substrat n+

X i  f (V pn )
2𝜀 𝑁𝐴 + 𝑁𝐷
𝑊𝑛 = 𝑉𝑏𝑖 − 𝑉𝑝𝑛
𝑞 𝑁𝐴 𝑁𝐷

Xi (V pn )  X i (V pn  0)  Wn (V pn )

 → Resistance increases with junction reverse voltage bias

 Example
X i (0)  0.1m
N A  1.8 1014 cm 3
N D  1019 cm 3
Vbi  0.74V
Wn (VSP  0)  4 10 5 m
Wn (V pn  10V )  1.6 10  4 m
X i  1.6 10  4 m

X i
 1.6 10 3  R  1.6 10
3

Xi R
 Voltage Coefficient Diffusion
Resistance
1  R  1.6 10  4 V 1  160 ppm / V
R V
 Voltage dependency increases with:
– Lower doping
– Higher square resistance
– Thinner layers
 Typical values
– n+ implantation: 20 W/ 100ppm/V
– p+ implantation: 100 W/ 1100ppm/V
– n- Implantation: 8 kW/ 20000 ppm/V
 Temperature Dependency
Diffusion Resistance
 Effective mobility is temperature dependent
m
 T 
  f (T )    ; m  f (ND , N A )
 0  T0 
m
 
 R T  1  R  m  TK
R0  T0  R T T R

 m depends on various scattering mechanisms

 Temperature dependence decreases for higher doping levels
 Typical values:
– n+ implantation: 20 W/ 1500ppm/K
– n- implantation: 8 kW/ 8000ppm/K
Polysilicon Resistors
 Polysilicon Resistors
 highly doped polycrystalline silicon
– used a Gate material, interconnects
Poly-Si Aluminium Spacer-oxide

Field oxide

doping concentration (typ.1020 cm 3 )

p - Substrate

 Current is nonlinear due to

grain boundaries
Electrical equivalent circuit:
R K ,A
R R K ,B
 eLK
I  I s  sinh 

V 
0
 2kTL 

C P
C P – L: resistor length
– Lk: grain length, typ. 20..50nm
Substrate • Relatively good linearity
 Voltage Dependency Polysilicon
Resistors

1  dl  l eLK cosh eLk V 

s
R dV 2kTL  2kTL 
1 dR  1 1  eLKV coth eLKV 
R dV V   2kTL  2kTL 

2
1  eLK 
   V
3  2kTL 

 Long resistors have better linearity

– Typ. Value 10..100 ppm/V
– e.g. W=25 m, L=2500 m → 30 ppm/V
 Temperature Dependency
Polysilicon Resistors

1 dR 1  eLKV  eL V 
 1  coth K 
R dT T  2kTL  2kTL 
2
1  eLKV 
  
3T  2kTL 

 Long resistors have lower temperature dependency

– Typ. Value 100..500 ppm/K
– e.g. L=300 m, V=2 V → 200 ppm/K
 Capacitors
 CMOS technology:
– High quality, thin gate oxide layers are available
– Using MOSFET, one can realize switches with low losses
– Using MOSFET, one can read-out stored voltages without (almost) losses

SiO2 Gate SiO2 Alu Polysilicon

Feldoxid
Field oxide Field
Feldoxid
oxide

n+ Implantation
p- substrate
 Poly Diffusion Capacitor
 CMOS technology:
– High quality, thin gate oxide layers are available
• Thickness 5..50 nm (Field oxide about factor 10 thicker)
– Using MOSFET, one can realize switches with low losses
– Using MOSFET, one can read-out stored voltages without (almost) losses

Aluminium Capacitor-Oxide Poly

Electrical lumped parameter model
A C0 B

n+ n+
CPA CPB
tOX

p-Substrate
Substrat
Field oxide
 0 r , SiO
CO  2
A  Cox A  CoxWL
tOX
 Poly Diffusion Capacitor
 C* depends on the process only
– Typical values 500 pF/mm2 .. 1.5 nF/mm2
 Small temperature and voltage dependency 1 dC
 Absolute accuracy 10%..20%  20 ppm / K
C dT
 Matched pairs accuracy < 0.1%
1 dC
 Disadvantage: diode to substrate  7 ppm / V
C dV

Aluminium Capacitor-Oxide Poly

n+ n+
tOX

p-Substrate

Field oxide
Poly-Poly Capacitor

Poly Top Plate Poly Bottom Plate

Field oxide

Capacitor oxide
p- Substrate
 Poly-Poly Capacitor
Capacitor-Oxide Poly 2
Spacer oxide

Poly 1
Field-
oxide
p-Substrate

A C0 B

CP1 CP2
Electrical lumped parameter model

 0 r , Sio
C0  2
 A  Cox  A  Cox  W  L
tOX
 Poly-Poly Capacitor
Absolute Value
 Source of tolerances
– 1. Edge uncertainty due to tolerances in L
• Lithography
• Etching W
 
– → W+ and L+
2 2
• Area A = WL, circumference U = 2 (W+L)

A` W   L     WL  W  L   2

U U
A´ A    2  A  
2 2
A´ A U

A 2A
– → minimal error for minimum ratio U to A
• → quadratic layout (best spherical)
– 2. oxide thickness
• Process dependent
 Capacitors: Matching
 Area and circumference have to adjusted
– Required capacitor value build up from quadratic unit capacitors
 Oxide thickness changes across a wafer (gradient)
– Common centroid layout

example:
1 1
 parasitic capacitors C C
– Electrodes to substrate 2 1
2 2

– Interconnect
– Fringe field and stray capacitors 1 1
• Can be in the same order as C0 C C
2 2
2 2

• Circuit should be insensitive

 0 r , SiO
C0  2
 A  Cox  A  Cox  W  L
tOX
 Precision of Passive Components

Diffusion Resistor Thinfilm Resistor Capacitor

Absolute 10 – 50 % 1% 10 – 30 %

0.05 – 0.1 % 0.01 - 0.1 % 0.02 – 0.3 %

Matching
(9 – 10 bit) (9 – 12 bit) (7 – 11 bit)
Temperature
2000 ppm/K 100 ppm/K 25 ppm/K
Coefficient
Voltage
(100 – 500) ppm/V  1 ppm/V 10 – 100 ppm/V
coefficient
 MOSFET Fabrication
a) n-well

Well oxide

n-well

p-substrate n-well
Wanne

b) Aktive areas
Field oxide Gate oxide

n-well

p-substrate Field oxide

Feldoxid
 MOSFET Fabrication
c) Poly silicon
Poly-Si Poly-Si
mask

n-well

p-substrate Poly silicon

Polysilizium

d) PMOS-Drain / Source

p+ p+

n-Well

p-Substrate p+-mask
Maske
p-MOS Transistor
 MOSFET Fabrication
e) NMOS-Drain / Source

n+ n+ p+ p+

n-Well

p-Substrate
Substrat n+-Mask
n-MOS Transistor
f) Contacts

n+ n+ p+ p+

n-Well

p-Substrate
Substrat KontaktlContact
öcher holes
 MOSFET Fabrication

g) Metal

n+ n+ p+ p+

n-well

P-substrate Contact holes

MOSFET Structure
 Layout

 Chips are specified with set of masks

 Minimum dimensions of masks determine transistor size (and
hence speed, cost, and power)
 Feature size f = distance between source and drain
– Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing design rules
 Express rules in terms of l = f/2
– E.g. l = 0.3 m in 0.6 m process
Layout Design Rules
 Design Rules Summary

 Metal and diffusion have minimum width and spacing of 4l

 Contacts are 2l x 2l and must be surrounded by 1l on the layers
above and below
 Polysilicon uses a width of 2l
 Polysilicon overlaps diffusions by 2l where a transistor is desired and
has spacing or 1l away where no transistor is desired
 Polysilicon and contacts have a spacing of 3l from other polysilicon
or contacts
 N-well surrounds pMOS transistors by 6l and avoid nMOS transistors
by 6l
 Gate Layout

 Layout can be very time consuming

– Design gates to fit together nicely
– Build a library of standard cells

 Standard cell design methodology

– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
Inverter Layout
 Transistor dimensions specified as W / L ratio
 Minimum size is 4l / 2l, sometimes called 1 unit
 In f = 0.6 m process, this is 1.2 m wide, 0.6 m
long
Example: Inverter Standard
Cell Layout
Example: 3-input NAND
Standard Cell Layout

 Horizontal n-diffusion and p-

diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom
 32 l by 40 l
 Stick Diagrams

 Stick diagrams help plan layout quickly

– Need not be to scale
– Draw with color pencils or dry-erase markers
 Wiring Tracks

 A wiring track is the space required for a wire

– 4 l width, 4 l spacing from neighbor = 8 l pitch
 Transistors also consume one wiring track
 Well spacing

 Wells must surround transistors by 6 l

– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track
 Area Estimation

 Estimate area by counting wiring tracks

– Multiply by 8 to express in l
 Scaling
 The simplest and most common scaling approach is constant field
scaling. The dimensions are scaled in the horizontal & vertical
directions, and proportionally increasing the substrate doping by a
factor l, to keep the electric field distribution unchanged.
 One of the major changes in a short-channel device is that electric
field in the channel region becomes two-dimensional due to the
influence of the drain potential.
 The substrate doping has to be increased to
decrease the depletion width (following from
Poisson’s equation).
 Small transistors have various undesired effects
such as gate oxide degeneration due to ‘hot’
electrons, threshold voltage shift, gate-induced
drain leakage, drain-induced barrier lowering
(DIBL).
 Changes in the fabrication flow have to be
introduced to mitigate these unwanted effects, and
keep short-channel devices operational.
 Constant Field Scaling
t OX

Parameter Factor

Dimensions (W, L, tOX,…) 1/l

Capacitors 1/l

Voltages 1/l

Currents 1/l

Power 1/l2

Noise density (kT/C) l

SNR 1/l3
 Constant Field Scaling

Parameter Scaling Factor

Device Dimensions W, L, tOX 1/l
Capacitance C 1/l
Line Resistance l
Contact Resistance l2
Line Delay 1
Voltage V 1/l
Current I 1/l
Power P 1/l2
"On"-Resistance 1
Delay T = RonC 1/l
Power-Delay Product 1/l3
Transconductance gm 1
Noise Power (kT/C) l
SNR 1/l3
Intel 20nm Technology