System on a Chip

Prof. Dr. Michael Kraft

 Lecture 2:
Revision: MOSFET Operation
and Modelling
 Basic MOSFET Operation
 Small Signal Model
 Spice Models
 Short Channel Effects
 Active Components
MOSFETS

 MOSFET is a symmetrical device.

 Metal on the gate is often replaced by polysilicon.
 L is the parameter characterising a process technology. Modern processes
have a gate length down to 0.065μm for digital circuits. Analogue circuits
~0.35-1μm.
 Gate oxide thickness is in the order of a few nm.
 The ITRS predicts gate lengths of 13nm by 2013 and 6nm by 2020!!!
 For vGS = 0, the source and drain regions are separated by back-to-back pn
junctions resulting in an extremely high resistance (about 1012 Ω)
 MOSFET As A Switch

 For digital operation, the MOSFET is modelled as an ON/OFF switch

– g=1 (High) represents the positive supply voltage (VDD) applied to the gate
– Typical values from 5V (older technologies) to 1.0V (newer technologies)
 MOSFET Symbols

n-channel transistor symbols

P-channel transistor symbols

 All are enhancement transistors (normally off)

– Depletion mode transistors are not used anymore (normally
on)
 Basic Operation

VG<0: accumulated
channel

VG>0: inverted channel,

Current flow gate drain
possible

 Gate – source voltage for which the concentration of electrons is equal to

concentration of holes in the substrate is called the Threshold voltage, Vth
 Charge density in channel is proportional to Veff=VGS-Vth
 Basic Operation
Triode Region
VG>0: inverted channel,
Current flow gate drain
possible

 Charge density (charge per unit area): Qn = Cox(VGS-Vth) = CoxVeff

𝜀𝑜𝑥 𝜀0
 Cox is the Gate Capacitance per unit area: 𝐶𝑜𝑥 =
𝑡𝑜𝑥
– 𝜀𝑜𝑥 is the relative permittivity of SiO2
– tox the SiO2 thickness
 Total charge in channel: QT = WLCox(VGS – Vth)
𝑊 𝑊
 For VDS > 0 but small (VDS<<Veff): 𝐼𝐷 = 𝜇𝑛 𝑄𝑛 𝑉𝐷𝑆 = 𝜇𝑛 𝐶𝑜𝑥 (𝑉𝐺𝑆 − 𝑉𝑡ℎ ) 𝑉𝐷𝑆
𝐿 𝐿
 mn: mobility of electrons near surface (0.14m2/Vs in intrinsic Si,
0.01-0.06m2/Vs in modern NMOS devices
 Behaves like a resistor
 Saturation Region

 For VDS increasing, the channel charge at the

drain end decreases
– Voltage across the gate oxide is smaller at the
drain end
– Charge density has a tapered shaped
– Charge density at x: Qn(x)=Cox(VGS-Vch(x)-Vth)
– At drain end: VG-Vch(L)=VGD
 For VDS further increasing, the gate to channel voltage will become smaller
than the Vth at the drain end → channel is pinched off
– ID saturates
– Pinch off occurs at VDS,sat = VGS-Vth = Veff
 Operating Regions

 Active or saturation region: mainly used for analogue circuits (amplifiers)

– Bias transistor so that VGS-Vth>100mV
– Square law relationship (for BJT: exponential relationship)
– Drain current is impendent of VDS
• This is only true as a first order approximation
 Channel Length Modulation

 For VDS even further increasing, the point where the gate to channel voltage
is equal to Vth moves to towards the source
– The effective channel is shortened: channel length modulation
– It can be shown that:

– λ: channel length modulation parameter or output impedance constant (unit: V-1)

 Channel Length Modulation

 Channel length modulation introduces a dependence of ID on VDS in the

active region  
1
I D 1
– Output resistance: r0    
 VDS  I D

– for even high values of VDS other second order effects (short channel effects)
dominate and cause a stronger dependence of ID on VDS
 Threshold Voltage
Vtno = ΦGS - Qss/COX + 2ΦF + γ sqrt(2ΦF) ΦGS: work function difference,
gate/substrate materials
ΦF: Fermi potential of substrate, ≈0.35V
KS: relative permittivity of Si, 11.9

 The threshold voltage depends on:

– The work-function difference between the gate material and the substrate
material
– The voltage drop between the channel and the substrate required for the
channel to exist
– The voltage drop across the thin oxide required for the depletion region, with
its immobile charge, to exist
– The voltage drop across the thin oxide due to unavoidable charge trapped in
the thin oxide
– The voltage drop across the thin oxide due to implanted charge at the surface
of the silicon.
 Body Effect

 The source - body voltage, VSB influences the threshold voltage hence the
drain current (sometimes the substrate is referred to as a second gate)
 For VSB increasing, the depletion region between the channel and the
substrate becomes wider, hence there is more charge
 Modelled by the Body effect constant:
 Small Signal Model, Low Frequency

 Transconductance, gm Body Transconductance, gmb

I D
 k ' VGS  Vth 1  VDS 
W
gm  I D V
 k ' VGS  Vth 1  VDS  T
W
VGS L g mb 
VSB L VSB
for VDS  1
VT 
  
W
gm  k ' VGS  Vth   2k ' W I D VSB 2 2F  VSB
L L
g mb
with k '  m nCox  typical   0.1...0.3
gm
 Output resistance, ro (or rds):
for VDS  1
1
 I  1
r0   D    k ' (W / L) I D
I D 
 VDS
g mb
 2 2 F  VSB
 Small Signal Model, High Frequency

 For higher frequencies, capacitances need to be considered

– The largest capacitances are Cgs=2/3WLCox and the depletion capacitance at
the source: C’sb = (As + Ach)Cjs with:
 MOSFET Capacitors
CGB

CGD CDB
G B
CGS
CSB
S

 Intrinsic and extrinsic capacitances:

– Intrinsic cap’s are related to the electric field in the gate oxide which
also forms the channel.
– Extrinsic cap’s are caused by parasitic effects.
 Intrinsic capacitances are associated with charge on the gate
electrode and in the channel hence vary with the terminal voltages.
 Two intrinsic capacitances: gate capacitance and source-body and
drain-body depletion capacitance (two reverse biased p-n junctions)
 Small Signal Model, High Frequency

 Cgd is due to the overlap between the gate and the drain and fringing
capacitance, Cgd=CoxWLox
– sometimes called the Miller capacitance, which is important when there is a
voltage gain between gate and drain
 Figure of merit for transistor speed: unity-gain frequency
 MOSFET Capacitors

Region CGS CGD CGB

VGS<VT 0 0 WLCOX

1 1
Triode region WLCOX WLCOX
2 2 0

2
Active region WLCOX 0 0
3
 Subthreshold (Weak Inversion)
lnIDS

Active
region

Subthreshold
region

VTH VGS

 Simple model assumes that MOST turns on suddenly for VGS > Vth and is
completely off for VGS< Vth
 For 0<VGS<Vth negative, there exists already a channel
– weak inversion
– main conduction mechanism is diffusion (not drift as in strong inversion)
– Drain current vs gate-source voltage is exponential (like in a BJT)

 with and
 Mobility Degradation

Electron velocity
107

[cm/s]
vn = mnEx

Ey

 The effective carrier mobility decreases under large electric fields

– due to the vertical electric fields, electrons are pushed to the surface and
scattered
 The effect causes the velocity of carriers to saturate (≈107 cm/s in Si)
 Effective carrier mobility:

– θ and m are device technology parameters

 Incorporating this into the drain current equation:

 The maximum transconductance achievable with:

 Mobility degradation becomes a major effect for smaller technologies
Summary Subthreshold, Mobility
Degradation
 Short Channel Effects

 Short Channel effects include a number of effects that become

important for shrinking dimensions
– Reduced output impedance
– hot-carrier effects
• oxide trapping
• substrate currents
– Threshold voltage dependency on device dimensions W/L
 Short channel transistors have reduced output impedance because
the depletion region at drain end have an increased proportional
effect on drain current
– Additionally a phenomenon known as drain-induced barrier lowering
(DIBL) effectively lowers Vth as VDS is increased, thereby further
lowering the output impedance of a short-channel device
 Hot Carrier Effects

 high-velocity carriers can cause harmful effects

– generation of electron-hole pairs by impact ionization and avalanching
• Extra electron-hole pairs are caused by impact ionization and cause currents
to flow from the drain region to the substrate
• effect can be modelled by a finite drain-to-ground impedance
• can also cause latch-up
– hot-carriers can also cause a tunnel current through the gate oxide
• some get trapped and shift the threshold voltage
• hot carriers limit the long term life time and reliability of MOST
– hot carrier can also cause punch through from source to drain and can
cause transistor breakdown
 Spice Simulation

 The SPICE level 1 model (Schichman-Hodges Model*) is a simple,

approximate model which is essentially the same as used for hand-
calculations
 The model consists of the following components:
– An equation for the threshold voltage
– Equations for the drain/source current
– Equations for the gate capacitances CGS and CGD
– An equivalent circuit
– Model parameters depend on the SPICE version
* [1] H. Shichman and D. A. Hodges, “Modeling and simulation of insulated-gate field-effect transistor switching circuits,” IEEE
Journal of Solid-State Circuits, SC-3, 285, September 1968.
 SPICE Level 1 Parameters
SYMBOL PARAMETER DESCRIPTION
VTO VTO Zero bias threshold voltage
Kp KP Transconductance parameter
λ LAMDA Channel length modulation
 GAMMA Body effect parameter
2ΦF PHI Surface inversion potential
tox TOX Gate oxide thickness
NA NSUB Substrate doping concentration
LD LD Lateral diffusion

μ UO Surface mobility

IS IS S/B & D/B diode saturation current

VBI PB S/B & D/B diode built in voltage

CJ0 CJ S/B & D/B zero bias junction cap./m2

25
 SPICE Level 1 Parameters
MJ MJ S/B & D/B doping profile grading coefficient
S/B & D/B zero bias perimeter doping grading
CJSW CJSW coefficient
S/B & D/B perimeter doping grading coefficient
MJSW MSJW
CGBO CGBO G/B overlap capacitance/m2
G/D overlap capacitance/m2
CGDO CGDO
CGSO G/S overlap capacitance/m2
CGSO
RD RD Drain series resistance

RS RS Source series resistance

26
 SPICE Level 1 Equations (1/2)
From PSPICE manuals (PSPRef.pdf, pp. 198):
Drain current equations
Normal mode: Vds > 0
Case 1
for cutoff region: Vgs-V to < 0
then: Idrain = 0
Case 2
for linear region: Vds < Vgs-V to
then: Idrain = (W/L)·(KP/2)·(1+LAMBDA·Vds)·Vds·(2·(Vgs-V to )-Vds)
Case 3
for saturation region: 0 < Vgs-V to < Vds
then: Idrain = (W/L)·(KP/2)·(1+LAMBDA·Vds)·(Vgs-V to ) 2
where
V to = VTO+GAMMA·((PHI-Vbs)1/2 -PHI 1/2)
Inverted mode: Vds < 0
Switch the source and drain in the normal mode equations above.

27
 SPICE Level 1 Equations (2/2)
From PSPICE manuals (PSPRef.pdf, pp. 199):
MOSFET equations for capacitance
Cbs = bulk-source capacitance = area cap. + sidewall cap. + transit
time cap.
Cbd = bulk-drain capacitance = area cap. + sidewall cap. + transit
time cap.
where
if
CBS = 0 AND CBD = 0
then
Cbs = AS·CJ·Cbsj + PS·CJSW·Cbss + TT·Gbs
Cbd = AD·CJ·Cbdj + PD·CJSW·Cbds + TT·Gds
else
Cbs = CBS·Cbsj + PS·CJSW·Cbss + TT·Gbs
Cbd = CBD·Cbdj + PD·CJSW·Cbds + TT·Gds
where
Gbs = DC bulk-source conductance = dIbs/dVbs
Gbd = DC bulk-drain conductance = dIbd/dVbd
if
Vbs < FC·PB
then
Cbsj = (1-Vbs/PB)-MJ
Cbss = (1-Vbs/PBSW)-MJSW
if
Vbs > FC·PB

28
 SPICE Level 1 Equations (3/3)
MOSFET equations for capacitance (cont.)

then
Cbsj = (1-FC)-(1+MJ)·(1-FC·(1+MJ)+MJ·Vbs/PB)
Cbss = (1-FC)-(1+MJSW)·(1-FC·(1+MJSW)+MJSW·Vbs/PBSW)
if
Vbd < FC·PB
then
Cbdj = (1-Vbd/PB)-MJ
Cbds = (1-Vbd/PBSW)-MJSW
if
Vbd > FC·PB
then
Cbdj = (1-FC)-(1+MJ)·(1-FC·(1+MJ)+MJ·Vbd/PB)
Cbds = (1-FC)-(1+MJSW)·(1-FC·(1+MJSW))

Cgs = gate-source overlap capacitance = CGSO·W

Cgd = gate-drain overlap capacitance = CGDO·W
Cgb = gate-bulk overlap capacitance = CGBO·L

29
 Advanced Spice Models
 BSIM3
– Improved modelling of moderate inversion, and the geometry-
dependence of device parameters. physics-based model
 EKV:
– Relates terminal currents and voltages with unified equations that
cover all modes of transistor operation, hence avoiding
discontinuities at transitions between, for example, weak and strong
inversion. Also handles geometry-dependent device parameters.
 BSIM4
– Improved modeling of leakage currents and short-channel effects,
noise, and parasitic resistance in the MOSFET terminals, as well as
continued improvements in capturing the geometry dependence of
device parameters.
 PSP:
– Improved modeling of noise and the many short-channel and layout-
dependent effects now dominant in nanoscale CMOS devices. Good
for nonlinearities.
 sdfsd
– werwer
– werwer
 MOSFET Equations
 n-Kanal-Enhancement-Transistor
2  
 VGS V T   1  DS
k' W V
lD  
Input characteristics 2 L  VA 
K‘: transconductance parameter [A/V2]

ID k '  m 0Cox

λ: Channel length modulation parameter [V-1]

1
VA 


gm: Transconductance in saturation

I D
gm 
VDS
VT VGS
gm  k '
W
VGS  VT   2k ' W I D
L L
 MOSFET Equations
 Example: n-channel enhancement transistor
Triode Region
Output characteristics
W V 
lD  k ' VGS  VT  DS   VDS
VDS,Sat = VGS-VT L 2 

Triode- Saturation region Saturation Region

ID region
2  
 VGS V T   1  DS
k' W V
lD  
2 L  VA 

VGS Output resistance

1 lD
 g ds 
ro VA  VDS

VDS
Triode: VDS < (VGS-VT)
Saturation: VDS > (VGS-VT)
Comparison BJT - MOSFET
 Comparison BJT - MOSFET

 MOSFET: controlled by an electric field

– Very high input resistance (no current into gate)
 Bipolar devices have a higher gm than MOSFETs for a given bias current
due to its exponential IV characteristics.