1.

Wires

Gisselquist Daniel E. Gisselquist, Ph.D.

Technology, LLC
 Lesson Overview
Ź Lesson Overview ˝ What is a wire?
First design
˝ What can I do with it?
Schematic
Constraints ˝ How do I build a design?
PCF
Build the design
First Success!
Objectives
Simulation
Verilator Driver ˝ To get an initial, basic familiarization with combinatorial logic
Bus Signals
Bit Select
Internal Signals ˝ To learn how to run the tools to build a design
Schematic
˝ To get an initial design running on an FPGA board
Circular Logic
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 First design
Lesson Overview Let’s build a simple Verilog design
Ź First design
Schematic module thruwire ( i_sw , o_led ) ;
Constraints
PCF
input wire i_sw ;
Build the design output w i r e o_led ;
First Success!
Simulation
Verilator Driver assign o_led = i_sw ;
Bus Signals endmodule
Bit Select
Internal Signals
Schematic
Circular Logic
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 First design
Lesson Overview Let’s build a simple Verilog design
Ź First design
Schematic module thruwire ( i_sw , o_led ) ;
Constraints
PCF
input wire i_sw ;
Build the design output w i r e o_led ;
First Success!
Simulation
Verilator Driver assign o_led = i_sw ;
Bus Signals endmodule
Bit Select
Internal Signals
Schematic
Circular Logic ˝ Verilog files contain modules
Dual Assignment ˝ This module is named thruwire
Sim Result
Examples ˝ While Verilog allows more than one module per file,
Exercise
Conclusion
I recommend only one module per file.

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 First design
Lesson Overview Let’s build a simple Verilog design
Ź First design
Schematic module thruwire ( i_sw , o_led ) ;
Constraints
PCF
input wire i_sw ;
Build the design output w i r e o_led ;
First Success!
Simulation
Verilator Driver assign o_led = i_sw ;
Bus Signals endmodule
Bit Select
Internal Signals
Schematic
Circular Logic ˝ The module keyword marks the beginning
Dual Assignment ˝ endmodule marks the end of the module
Sim Result
Examples
Exercise
Conclusion

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 First design
Lesson Overview Let’s build a simple Verilog design
Ź First design
Schematic module thruwire ( i_sw , o_led ) ;
Constraints
PCF
input wire i_sw ;
Build the design output w i r e o_led ;
First Success!
Simulation
Verilator Driver assign o_led = i_sw ;
Bus Signals endmodule
Bit Select
Internal Signals
Schematic
Circular Logic ˝ This module declares two ports, i_sw and o_led
Dual Assignment ˝ The first is declared to be an input
Sim Result
Examples ˝ The second is declared as an output
Exercise
˝ Both are wire’s, but we’ll get to that later
Conclusion

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 First design
Lesson Overview Let’s build a simple Verilog design
Ź First design
Schematic module thruwire ( i_sw , o_led ) ;
Constraints
PCF
input wire i_sw ;
Build the design output w i r e o_led ;
First Success!
Simulation
Verilator Driver assign o_led = i_sw ;
Bus Signals endmodule
Bit Select
Internal Signals
Schematic
Circular Logic ˝ Our one piece of logic sets o_led
Dual Assignment to be the same as i_sw
Sim Result
Examples
Exercise
Conclusion

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 First design
Lesson Overview Let’s build a simple Verilog design
Ź First design
Schematic module thruwire ( i_sw , o_led ) ;
Constraints
PCF
input wire i_sw ;
Build the design output w i r e o_led ;
First Success!
Simulation
Verilator Driver assign o_led = i_sw ;
Bus Signals endmodule
Bit Select
Internal Signals
Schematic FPGA’s are commonly used as:
Circular Logic
Dual Assignment ˝ Traffic cops
Sim Result
Examples
Exercise
A programmable/adjustable wire fabric
Conclusion
˝ Voltage level shifters
˝ This logic would be appropriate for each
. . . it generates a simple “wire” through the chip

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 Schematic
Lesson Overview Here’s what a schematic of this design would look like
First design
Ź Schematic
Constraints
PCF
Build the design
First Success!
Simulation
Verilator Driver
Bus Signals
Bit Select
Internal Signals
Schematic
Circular Logic
All from this assign statemnt
Dual Assignment
Sim Result assign o_led = i_sw ;
Examples
Exercise
Conclusion

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 Schematic
Lesson Overview A very similar design would make a good first serial port test
First design
Ź Schematic
Constraints
PCF
Build the design
First Success!
Simulation
Verilator Driver
Bus Signals
Bit Select
˝ Your circuit board should pass this test before you try to
Internal Signals implement your own serial port within it
Schematic
Circular Logic
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 Schematic
Lesson Overview For many boards, this may look more familiar
First design
Ź Schematic
Constraints
PCF
Build the design
First Success!
Simulation
Verilator Driver
Bus Signals
Bit Select
Internal Signals
Schematic
˝ FTDI FT2232H provides access to both
Circular Logic
Dual Assignment
– UART (i.e. serial port), and
Sim Result – JTAG, to load your design into the FPGA in the first place
Examples
Exercise
Conclusion
˝ Other solutions exist, such as
– A STM chip, as used by the BlackIce, or
– Direct USB, as used by the TinyFPGA BX

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 Constraints
Lesson Overview A fundamental part of any FPGA design maps your ports to the
First design
Schematic
pins
Ź Constraints
˝ This is the purpose of a Constraint File
PCF
Build the design ˝ Different vendors use different forms for their constraint files
First Success!
Simulation
Verilator Driver
– PCF: Used by Arachne-PNR and NextPNR
Bus Signals – UCF: Used by ISE for older Xilinx designs
Bit Select
Internal Signals
– XDC: Used by Vivado for newer Xilinx designs
Schematic – QSF: Used by Quartus for Altera Intel chips
Circular Logic
Dual Assignment ˝ Your board vendor should provide you with a master
Sim Result
Examples constraint file
Exercise
˝ You’ll still need to
Conclusion

– Comment-out pins you aren’t using

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 PCF File
Lesson Overview If you are using nextpnr, you’ll need a PCF file
First design
Schematic set_io i_sw P13
Constraints
Ź PCF
set_io o_led C8
Build the design
First Success!
Simulation ˝ Maps top-level ports to pins
Verilator Driver
Bus Signals ˝ You’ll find P13 and C8 on the schematic
Bit Select
Internal Signals – Find the FPGA pins connected to the switch
Schematic
Circular Logic
. . . and the LED output
Dual Assignment – If your design has no switches, you can use buttons
Sim Result
Examples
(for now)
Exercise Buttons also bounce, but we’ll get to that later
Conclusion

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 UCF File
Lesson Overview If you are using ISE, you’ll need a UCF file
First design
Schematic NET " i_sw " LOC = " P9 " | IOSTANDARD = LVCMOS33 ;
Constraints
Ź PCF
NET " o_led " LOC = " N3 " | IOSTANDARD = LVCMOS33 ;
Build the design
First Success!
Simulation ˝ This would be for the older Xilinx FPGA’s
Verilator Driver
Bus Signals ˝ Make sure you actually look up the correct pins
Bit Select
Internal Signals – P13 for one board might be something else on another
Schematic
Circular Logic On this board, the switch is on pin P9
Dual Assignment
Sim Result
˝ Most development boards use the 3.3V LVCMOS standard
Examples
Exercise – Pins are typically grouped in banks
Conclusion – All pins in a bank use the same voltage
– This voltage is usually fixed
– The master constraint file will help here

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 XDC File
Lesson Overview If you are using Vivado, you’ll need a XDC file
First design
Schematic set_property - dict { PACKAGE_PIN E22
Constraints
Ź PCF
IOSTANDARD LVCMOS12 } [ get_ports { i_sw }]
Build the design set_property - dict { PACKAGE_PIN T14
First Success! IOSTANDARD LVCMOS25 } [ get_ports { o_led }]
Simulation
Verilator Driver
Bus Signals
Bit Select ˝ This would be for the newer Xilinx FPGA’s
Internal Signals
˝ Usually, the vendor will provide a “master XDC” file
Schematic
Circular Logic ˝ From there, you should be able to
Dual Assignment
Sim Result – Rename the appropriate ports to i_sw and o_led
Examples
Exercise – Comment out every other I/O port
Conclusion

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 Build the design
Lesson Overview For an iCE40 design, this will look like:
First design
Schematic % yosys -p ’ synth_ice40 - json thruwire . json ’ \
Constraints
PCF
thruwire . v
Ź Build the design % nextpnr - ice40 -- hx8k -- package ct256 \
First Success! -- pcf thruwire . pcf -- json thruwire . json
Simulation
Verilator Driver % icepack thruwire . asc thruwire . bin
Bus Signals
Bit Select
You’ll need to do this for every project–get used to this flow.
Internal Signals
Schematic
Circular Logic
˝ A makefile can drastically simplify this process
Dual Assignment
Sim Result You should now have a file thruwire.bin that you can load
Examples onto your board.
Exercise
Conclusion
˝ If you aren’t using an iCE40, follow your chip vendor’s
instructions

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 First Success!
Lesson Overview Follow your board vendor’s instructions for loading this file onto
First design
Schematic
your board.
Constraints Notice now that every time you flip the switch, the LED responds
PCF
Build the design
Ź First Success!
Simulation
Verilator Driver
Bus Signals
Bit Select
Internal Signals
Schematic
Circular Logic
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 First Success!
Lesson Overview Follow your board vendor’s instructions for loading this file onto
First design
Schematic
your board.
Constraints Notice now that every time you flip the switch, the LED responds
PCF
Build the design
Yaaaayyyyyy!!! Your first FPGA design.
Ź First Success!
Simulation
Verilator Driver
Bus Signals
Bit Select
Internal Signals
Schematic
Circular Logic
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 Simulation
Lesson Overview Simulation is an important part of design
First design
Schematic
Constraints Simulation Hardware
PCF
Build the design Can trace all signals Can only see some signals
First Success! Extended tests cost GB Extended tests are simple
Ź Simulation
Verilator Driver Easy to debug Very hard to debug
Bus Signals
Bit Select
Internal Signals Because hardware is so hard to debug, simulation is vital
Schematic
Circular Logic ˝ A successful complex project
Dual Assignment
Sim Result
. . . requires simulation!
Examples
Exercise
Conclusion

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 Simulation
Lesson Overview Simulation is an important part of design
First design
Schematic
Constraints Simulation Hardware
PCF
Build the design Can trace all signals Can only see some signals
First Success! Extended tests cost GB Extended tests are simple
Ź Simulation
Verilator Driver Easy to debug Very hard to debug
Bus Signals
Bit Select
Internal Signals Because hardware is so hard to debug, simulation is vital
Schematic
Circular Logic ˝ A successful complex project
Dual Assignment
Sim Result
. . . requires simulation!
Examples
Exercise
Do it the easy way:
Conclusion

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 Simulation
Lesson Overview Simulation is an important part of design
First design
Schematic
Constraints Simulation Hardware
PCF
Build the design Can trace all signals Can only see some signals
First Success! Extended tests cost GB Extended tests are simple
Ź Simulation
Verilator Driver Easy to debug Very hard to debug
Bus Signals
Bit Select
Internal Signals Because hardware is so hard to debug, simulation is vital
Schematic
Circular Logic ˝ A successful complex project
Dual Assignment
Sim Result
. . . requires simulation!
Examples
Exercise
Do it the easy way: use the simulator!
Conclusion

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 Verilator
Lesson Overview Let’s now build our design using Verilator
First design
Schematic % verilator - Wall - cc thruwire . v
Constraints
PCF
% cd obj_dir /
Build the design % make -f Vthruwire . mk
First Success!
Ź Simulation
Verilator Driver
Bus Signals
˝ Verilator compiles Verilog into C++ placed into obj_dir/
Bit Select ˝ The make command then builds this converted C++ file into
Internal Signals
Schematic a shared object file we can now use
Circular Logic
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 Verilator Driver
Lesson Overview You’ll need a main simulation driver too.
First design
Schematic ˝ The code below comes from a file named thruwire.cpp
Constraints
PCF
Build the design #i n c l u d e < stdio .h >
First Success! #i n c l u d e < stdlib .h >
Simulation
Ź Verilator Driver
#i n c l u d e " Vthruwire . h "
Bus Signals #i n c l u d e " verilated . h "
Bit Select
Internal Signals
Schematic i n t main ( i n t argc , c h a r ** a r g v ) {
Circular Logic // Your logic here
Dual Assignment
Sim Result
}
Examples
Exercise
Conclusion

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 Verilator Driver
Lesson Overview You’ll need a main simulation driver too.
First design
Schematic // ...
Constraints
PCF
i n t main ( i n t argc , c h a r ** a r g v ) {
Build the design // Call commandArgs first !
First Success! V e r i l a t e d :: commandArgs( argc , a r g v );
Simulation
Ź Verilator Driver
Bus Signals // Instantiate our design
Bit Select
Internal Signals
V t h r u w i r e * tb = new V t h r u w i r e ;
Schematic
Circular Logic // ...
Dual Assignment
Sim Result
}
Examples
Exercise
Conclusion

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 Verilator Driver
Lesson Overview You’ll need a main simulation driver too.
First design
Schematic i n t main ( i n t argc , c h a r ** a r g v ) {
Constraints
PCF
// ...
Build the design
First Success! // Now run the design thru 20 timesteps
Simulation
Ź Verilator Driver f o r ( i n t k =0; k <20; k ++) {
Bus Signals // We ’ ll set the switch input
Bit Select
Internal Signals
// to the LSB of our step
Schematic tb - > i s w = k &1;
Circular Logic
Dual Assignment
Sim Result
tb - > e v a l ();
Examples
Exercise
Conclusion
// ...
}
}

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 Verilator Driver
Lesson Overview You’ll need a main simulation driver too.
First design
Schematic i n t main ( i n t argc , c h a r ** a r g v ) {
Constraints
PCF
// ...
Build the design f o r ( i n t k =0; k <20; k ++) {
First Success! // We ’ ll set the switch input
Simulation
Ź Verilator Driver // to the LSB of our counter
Bus Signals tb - > i s w = k &1;
Bit Select
Internal Signals
Schematic tb - > e v a l ();
Circular Logic
Dual Assignment
Sim Result
// Now let ’s print our results
Examples p r i n t f ( " k = %2 d , " , k );
Exercise
Conclusion
p r i n t f ( " sw = %d , " , tb - > i s w );
p r i n t f ( " led = % d \ n " , tb - > o l e d );
}
}

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 Building it all
Lesson Overview Last step, let’s put it all together:
First design
Schematic % g ++ -I / usr / share / verilator / include \
Constraints
PCF
-I obj_dir / \
Build the design / usr / share / verilator / include / verilated . cpp \
First Success! thruwire . cpp obj_dir / Vthruwire__ALL . a \
Simulation
Ź Verilator Driver -o thruwire
Bus Signals
Bit Select
Internal Signals
(Double check the location of Verilator in your own installation,
Schematic it might be located in another directory.)
Circular Logic
Dual Assignment Wow, that’s pretty complicated.
Sim Result You should have a Makefile in your ex-01-thruwire directory
Examples
Exercise with both the code and the build instructions.
Conclusion
% cd ex -01 - thruwire /
% make
# ( Make output skipped for brevity )
%

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 Simulation
Lesson Overview We can now run our simulator!
First design
Schematic % thruwire
Constraints
PCF
k = 0 , sw = 0 , led = 0
Build the design k = 1 , sw = 1 , led = 1
First Success! k = 2 , sw = 0 , led = 0
Simulation
Ź Verilator Driver k = 3 , sw = 1 , led = 1
Bus Signals k = 4 , sw = 0 , led = 0
Bit Select
Internal Signals
k = 5 , sw = 1 , led = 1
Schematic k = 6 , sw = 0 , led = 0
Circular Logic k = 7 , sw = 1 , led = 1
Dual Assignment
Sim Result
k = 8 , sw = 0 , led = 0
Examples k = 9 , sw = 1 , led = 1
Exercise
Conclusion
# .... ( Lines skipped for brevity )
%

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 Good habits
Lesson Overview Many Verilog problems can be avoided by some simple steps
First design
Schematic 1. Make ‘default nettype none the first line of your Verilog file
Constraints
PCF ˝ Before your module declaration
Build the design
First Success! ˝ Otherwise mis-spelled identifiers will be quietly turned
Simulation
Ź Verilator Driver
into wires
Bus Signals
Bit Select module thruwire ( i_sw , o_led ) ;
Internal Signals
Schematic
input wire i_sw ;
Circular Logic output w i r e o_led ;
Dual Assignment
Sim Result
Examples assign o_led = sw ;
Exercise endmodule
Conclusion

Without ‘default nettype none, this design would pass

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 Good habits
Lesson Overview Many Verilog problems can be avoided by some simple steps
First design
Schematic 1. Make ‘default nettype none the first line of your Verilog file
Constraints
PCF
2. Fix any errors when you verilator -Wall your design
Build the design 3. Run your design in a simulator
First Success!
Simulation
Ź Verilator Driver
˝ Attempt to recreate any hardware bugs . . . in the
Bus Signals simulator
Bit Select
Internal Signals These three rules will save you a lot of heartache!
Schematic
Circular Logic . . . Get in the habit of using them!
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 Bus Signals
Lesson Overview That was one single wire. We can also declare values consisting
First design
Schematic
of many bits.
Constraints
PCF input wire [8:0] i_sw ;
Build the design output wire [8:0] o_led ;
First Success!
Simulation
Verilator Driver This defines
Ź Bus Signals
Bit Select ˝ i_sw to be 9-input wires, and
Internal Signals
Schematic
˝ o_led to be 9-output wires
Circular Logic
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 Bit Select
Lesson Overview ˝ Select bits of interest from a bus
First design
Schematic assign o_led [ 7 ] = i_sw [ 0 ] ;
Constraints
PCF
assign o_led [ 6 : 5 ] = i_sw [ 5 : 4 ] ;
Build the design
First Success!
Simulation – Bit 7 of o_led is set to bit 0 of i_sw
Verilator Driver
Bus Signals – Bits 5 and 6 of o_led are set to bits 4 and 5 of i_sw
Ź Bit Select
Internal Signals ˝ Concatenate bits together
Schematic
Circular Logic
assign o_led [ 4 : 0 ] = { i_sw [ 2 : 0 ] , i_sw [ 7 : 6 ] } ;
Dual Assignment
Sim Result
Examples
Exercise – The t¨, ¨u operator composes a new bit vector from other
Conclusion
vectors

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 Internal Signals
Lesson Overview You can also declare and work with internal wires
First design
Schematic wire [8:0] w_internal ;
Constraints
PCF
Build the design
First Success! ˝ Internal wires are neither input nor output
Simulation ˝ These wires can now be used in logic
Verilator Driver
Bus Signals
Bit Select
assign w_internal = 9 ’ h87 ;
Ź Internal Signals
Schematic assign o_led = i_sw ˆ w_internal ;
Circular Logic
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 Literals
Lesson Overview A Verilog literal is defined as
First design
Schematic ˝ A width
Constraints
PCF
˝ An apostrophe
Build the design ˝ An optional sign indication, s
First Success!
Simulation
Verilator Driver
Defaults to unsigned
Bus Signals
Bit Select
˝ A numeric type: h (hex), d (decimal), o (octal), b (binary),
Ź Internal Signals sd (signed decimal)
Schematic
Circular Logic ˝ The value: a series of digits, possibly containing underscores
Dual Assignment Underscores can be very useful for longer numbers
Sim Result
Examples
Exercise
Examples include:
Conclusion 1’b0 1’b1 2’b01 4’b0101 4’h5 -7’sd124
32’hdead beef 32’d100 000 000
Place a ’-’ in front of the width for negative numbers

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 Sign Extension
Lesson Overview If the literal is smaller than the context . . .
First design
Schematic ˝ If there is no ’s’, the number is unsigned and it is zero
Constraints
PCF
extended
Build the design ˝ Any literal with an ’s’ is sign extended
First Success!
Simulation ˝ . . . to fit the width
Verilator Driver
Bus Signals If the literal is too big for the context . . .
Bit Select
Ź Internal Signals ˝ It is truncated to fit the context
Schematic
Circular Logic Many tools will create a warning for width mismatches
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 Operators
Lesson Overview The Verilog language supports the following operators
First design
Schematic
` Addition ´ Subtraction
Constraints ăă Left Shift ąą Right shift
PCF
Build the design ´ Unary negation ?: Tertiary operator
First Success! ˜ Bit-wise negation ˆ Bit-wise XOR
Simulation
Verilator Driver | Bitwise OR & Bitwise AND
Bus Signals
Bit Select
|| Logical OR && Logical and
Ź Internal Signals ! Logical negation ąąą Arithmetic right shift
Schematic
Circular Logic ““ Equality !“ Inequality
Dual Assignment
Sim Result ă, ă“ Less than (Equal) ą, ą“ Greater than (Equal)
Examples
Exercise Limited, use with care Avoid within logic
Conclusion
˚ Multiplication { Division
% Remainder
˝ Some FPGA’s support native multiplication
˝ None support a single clock divide or remainder

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 Schematic
Lesson Overview From this code:
First design
Schematic assign w_internal = 9 ’ h87 ;
Constraints
PCF
assign o_led = i_sw ˆ w_internal ;
Build the design
First Success! Get this internal structure:
Simulation
Verilator Driver
Bus Signals
Bit Select
Internal Signals
Ź Schematic
Circular Logic
Dual Assignment
Sim Result
Examples
Exercise
Conclusion

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 Circular Logic
Lesson Overview Avoid circular logic!
First design
Schematic
Constraints
PCF
Build the design
First Success!
Simulation
Verilator Driver
Bus Signals
Bit Select
Internal Signals
Schematic Example:
Ź Circular Logic
Dual Assignment assign o_led = i_sw + o_led ;
Sim Result
Examples
Exercise
Conclusion ˝ This doesn’t work in hardware like it might in software
˝ This is roughly equivalent to creating a short circuit
˝ Most tools will fail to build such designs
This include Verilator

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 Dual Assignment
Lesson Overview You are designing hardware: A value can only be set once
First design
Schematic
This is an error:
Constraints
PCF assign o_led = i_sw | 9 ’ h87 ;
Build the design assign o_led = i_sw + 1 ;
First Success!
Simulation
Verilator Driver
Bus Signals
Bit Select
Internal Signals
Schematic
Circular Logic
Dual
Ź Assignment
Sim Result
Examples
Exercise
Conclusion

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 Let’s build it
Lesson Overview Let’s build this design:
First design
Schematic ‘default nettype none
Constraints
PCF
Build the design module maskbus ( i_sw , o_led ) ;
First Success! input wire [8:0] i_sw ;
Simulation
Verilator Driver output w i r e [8:0] o_led ;
Bus Signals
Bit Select
Internal Signals
wire [8:0] w_internal ;
Schematic
Circular Logic assign w_internal = 9 ’ h87 ;
Dual
Ź Assignment assign o_led = i_sw ˆ w_internal ;
Sim Result endmodule
Examples
Exercise
Conclusion . . . using Verilator

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 Updated Driver
Lesson Overview Let’s update our driver for this wire bus design
First design
Schematic i n t main ( i n t argc , c h a r ** a r g v ) {
Constraints
PCF
// ...
Build the design f o r ( i n t k =0; k <20; k ++) {
First Success! // ...
Simulation
Verilator Driver // Bottom 9 bits of counter
Bus Signals tb - > i s w = k & 0 x 1 f f ;
Bit Select
Internal Signals
Schematic tb - > e v a l ();
Circular Logic
Dual
Ź Assignment // Now let ’s print our results
Sim Result p r i n t f ( " k = %2 d , " , k );
Examples
Exercise p r i n t f ( " sw = %3 x , " , tb - > i s w );
Conclusion p r i n t f ( " led = %3 x \ n " , tb - > o l e d );
}
}

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 Sim Result
Lesson Overview % ./ maskbus
First design
Schematic
k = 0 , sw = 0 , led = 87
Constraints k = 1 , sw = 1 , led = 86
PCF
k = 2 , sw = 2 , led = 85
Build the design
First Success! k = 3 , sw = 3 , led = 84
Simulation k = 4 , sw = 4 , led = 83
Verilator Driver
Bus Signals
k = 5 , sw = 5 , led = 82
Bit Select k = 6 , sw = 6 , led = 81
Internal Signals k = 7 , sw = 7 , led = 80
Schematic
Circular Logic k = 8 , sw = 8 , led = 8f
Dual Assignment k = 9 , sw = 9 , led = 8e
Ź Sim Result
# .... ( Lines skipped for brevity )
Examples
Exercise %
Conclusion

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 Examples
Lesson Overview What can you do with wires and wire logic?
First design
Schematic
Example: Multiplexer
Constraints
PCF input wire i_a , i_b , i_sel ;
Build the design output wire o_out ;
First Success!
Simulation
Verilator Driver assign o_out = ( i_sel ) ? i_a : i_b ;
Bus Signals
Bit Select
Internal Signals
Schematic
Circular Logic
Dual Assignment
Sim Result
Ź Examples
Exercise
Conclusion

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 Examples
Lesson Overview What can you do with wires and wire logic?
First design
Schematic
Example: Multiplexer
Constraints
PCF input wire i_a , i_b , i_sel ;
Build the design output wire o_out ;
First Success!
Simulation
Verilator Driver assign o_out = ( i_sel ) ? i_a : i_b ;
Bus Signals
Bit Select
Internal Signals
Schematic
˝ This is a good example of the tertiary operator
Circular Logic ˝ Interested in making a connection to one of two serial ports?
Dual Assignment
Sim Result
˝ How about connecting one of two bus masters to an
Ź Examples interconnect?
Exercise
Conclusion
We’ll get to these examples later.

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 Examples
Lesson Overview What can you do with wires and wire logic?
First design
Schematic
Example: Parity check
Constraints
PCF input wire [7:0] i_word ;
Build the design output wire o_parity ;
First Success!
Simulation
Verilator Driver assign o_parity = ˆ i_word ;
Bus Signals
Bit Select
Internal Signals
Schematic
Circular Logic
Dual Assignment
Sim Result
Ź Examples
Exercise
Conclusion

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 Examples
Lesson Overview What can you do with wires and wire logic?
First design
Schematic
Example: Parity check
Constraints
PCF input wire [7:0] i_word ;
Build the design output wire o_parity ;
First Success!
Simulation
Verilator Driver assign o_parity = ˆ i_word ;
Bus Signals
Bit Select
Internal Signals
This form of XOR is a reduction operator
Schematic
Circular Logic ˝ It XORs all the word’s bits together
Dual Assignment ˝ Other reduction operators include | and &
Sim Result
Ź Examples
Error Correction Code (ECC) creation logic is very similar
Exercise
Conclusion

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 Examples
Lesson Overview What can you do with wires and wire logic?
First design
Schematic
Example: Interrupt detector
Constraints
PCF input wire [7:0] i_irq_source ;
Build the design output wire o_irq ;
First Success!
Simulation
Verilator Driver assign o_irq = | i_irq_source ;
Bus Signals
Bit Select
Internal Signals
Schematic
˝ i_irq_source contains eight interrupt sources
Circular Logic ˝ o_irq is true if any interrupt source is true
Dual Assignment
Sim Result
Ź Examples
Exercise
Conclusion

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 Examples
Lesson Overview What can you do with wires and wire logic?
First design
Schematic
Example: CPU stall determination
Constraints
PCF assign dcd_stall = ( dcd_valid)&&(op_stall ) ;
Build the design
First Success!
From the ZipCPU, the decode stage must stall if
Simulation
Verilator Driver
Bus Signals
˝ It has produced a valid result, and
Bit Select ˝ The next stage, read operands, is stalled for some reason
Internal Signals
Schematic These stalls can back up through the CPU
Circular Logic Ex. Read operands might be stalled if the ALU is stalled
Dual Assignment
Sim Result
Ź Examples
Exercise
Conclusion

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 Examples
Lesson Overview What can you do with wires and wire logic?
First design
Schematic
Example: Determining if there’s a phase error in a phase lock
Constraints loop
PCF
Build the design assign phase_err = ( output_phase != input_phase ) ;
First Success!
Simulation
Verilator Driver In this case, the loop will adjust if there are any errors
Bus Signals
Bit Select
Internal Signals
Schematic
Circular Logic
Dual Assignment
Sim Result
Ź Examples
Exercise
Conclusion

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 Exercise
Lesson Overview This section has two exercises:
First design
Schematic 1. Build and try the thruwire demo.
Constraints
PCF ˝ Toggle the switch.
Build the design
First Success! ˝ Verify that toggling your switch will toggle the LED
Simulation
˝ Build and run the Verilator simulation
Verilator Driver
Bus Signals
Bit Select
2. Create a test of your serial port connection
Internal Signals
Schematic ˝ Connecting the input serial port wire to the output
Circular Logic Beware: These wires are often marked “TX” and “RX”,
Dual Assignment
Sim Result but not always from the perspective of the FPGA
Examples
˝ Turn off any ‘local echo’
Ź Exercise
Conclusion ˝ Turn off any hardware flow control
˝ Verify that characters typed into your terminal program
show up on the screen

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 Conclusion
Lesson Overview ˝ Wires represent connections within the design
First design
˝ Wires can also represent the outputs of combinatorial logic
Schematic
Constraints ˝ Wires have no memory, circular logic or feedback is illegal
PCF
Build the design
˝ You know how to create constraints for your project!
First Success!
Simulation You can now build and load a design onto an FPGA!
Verilator Driver
Bus Signals
Bit Select
Internal Signals
Schematic
Circular Logic
Dual Assignment
Sim Result
Examples
Exercise
Ź Conclusion

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