Cm6502 Apfc Chip (Epa90+ Zvs Type)

CM6502UHH (1MHz PFC)
http://www.championmicro.com.tw EPA/90+ ZVS-Like PFC CONTROLLER

Design for High Efficient Power Supply at both Full Load and Light Load
GENERAL DESCRIPTION FEATURES

CM6502UHH is a ZVS-Like Single PFC and it is designed Patents Pending
to meet EPA 90+ spec. (total efficiency). It has the following 23V Bi-CMOS process.
key features.
Designed for EPA/90+efficiency
1.) Around 2% efficiency gain when the output load is Selectable Boost output from 380V to 355V during light
below 60% of the full load load for CM6502UHH
2.) High Voltage 420V bulk capacitor can be reduced, Customer Programmable the Low Threshold of PGB
comparator at PGTHL pin
and also PFC Boost Capacitor ripple current can be
“Remember It was Light Load” function to improve the
reduced
efficiency and Hold up Time
3.) Turbo Speed PFC may reduce 420 Bulk Capacitor “Remember It was Full Load” function to improve the
size further
efficiency and Hold up Time
4.) A PGB function is designed for interfacing to next
Initially, Vin at 230Vac , IC internal determine is low line;
stage controller or the House Keeping IC at therefore at light load, Bulk capacitor 380V can drop to
secondary side. The PGB function pull low was 355V for CM6502UHH
decide by IC inside. The PGB Pull high It has a Clean Digital PFC Brown Out
customer programmable by PGTHL low threshold. All high voltage resistors can be greater than 5 Mega
ohm (5 Mega to 8 Mega ohm) to improve the no load
5.) “Remember it was Light Load” function and
consumption.
“Remember it was Full Load” function may reduce
Rail to rail CMOS Drivers with on, 24 ohm and off, 12
PFC 420V Bulk Capacitor size further. It boosts the
ohm with 17V zeners.
total efficiency as well.
Fast Start-UP Circuit without extra bleed resistor to aid
6.) Initially, Vin at 230Vac , IC internal AC high line VCC reaches 13V sooner.
comparator determine is low line; therefore at light Low start-up current (50uA typ.)
load, Bulk capacitor 380V can drop to 355V for Low operating current (2.1mA typ.)
CM6502UHH
Adjustable Long Delay Time for Line Sagging
7.) IAC, Vrms, VFB pin resistor can be use > 5M (Up to 2 Second)
ohm. It will help No Load Consumption to reduce at 17V VCC shunt regulator
270VAC Dynamic Soft PFC to ease the stress of the Power
Device and Ease the EMI-filter design.
8.) Better Power Factor and Better THD
Better Power Factor and Better THD
9.) Clean Digital PFC Brown Out
10.) Dynamic Soft PFC to ease the stress over the entire
Average current mode control, continuous or
discontinuous boost leading edge PFC.
external power device is reduced and EMI noise
Current fed Gain Modulator for improved noise immunity.
reduced
Gain Modulator is a constant maximum power limiter.
11.) Superior Surge Noise Immunity
Precision Current Limit, over-voltage protection, UVLO,
and soft start, and Reference OK.
CM6502UHH is designed to meet the EPA/90+ regulation.
With the proper design, its efficiency of power supply can
easily approach 90+/92+.
2014/11/11 Rev. 1.0 Champion Microelectronic Corporation 1

APPLICATIONS PIN CONFIGURATION

EPA/90+ related Power Supply SOP-14 & DIP-14
TOP View
Desktop PC Power Supply
Internet Server Power Supply
LCD Power Supply 1 IEAO VEAO 14

PDP Power Supply
2 IAC VFB 13
AC Adaptor
IPC Power Supply 3 ISENSE VREF 12

UPS 11
4 VRMS VCC
Battery Charger
5 ISS PFCOUT 10
DC Motor Power Supply
Monitor Power Supply 6 PGTHL PGB 9
Telecom System Power Supply
7 RTCT GND 8
Distributed Power
PIN DESCRIPTION
Operating Voltage
Pin No. Symbol Description
Min. Typ. Max. Unit
PFC transconductance current error amplifier output

1 IEAO 0 VREF V
(GMi).
IAC has 2 functions:

1. PFC gain modulator reference input.
2 IAC 0 100 uA
2. Typical RAC resistor is about 6 Mega ohm to 8 Mega
ohm to sense the line.
PFC Current Sense: for both Gain Modulator and PFC

3 ISENSE -1.3 0.7 V
current ILIMIT comparator.
Line Input Sense pin for multiplier and also it is the PFC
4 VRMS 0 6 V
Brown out sense pin.
1)PFC Soft Start pin: It supplies ~ 10uA to SS pin. It provides a
close-loop soft start function during power supply start up. PFC
Soft Start function can adjust by a simple capacitor to ground and
it can be around 1uF.

5 ISS 0 VCC V
2)When AC turn off VFB voltage sense is lower than
PGTHL(PGB comparator), SS pin is discharged through an
internal ~ 70K Ohm resistor.

PGTHL is an input I/O. The user can program the Low

6 PGTHL Threshold of the Power Good which can determine the 0 VREF V
comparator output of PGB (open drain) to be pulled high.
7 RTCT Oscillator timing node; timing set by RT and CT 0.8 4 V
8 GND Ground
PGB is the PG comparator output. The input of PG

comparator is using Vfb (pin 13) to compare with the high
threshold 2.25V (preset internally) and the low threshold
comparator with PGTHL (pin 6, Set up by user).
9 PGB 0 VCC V
When Bulk Voltage 380V is ready, pin 9 is open-drain
and it will be pulled low.
When Bulk Voltage Drop (VFB=PGTHL) set up point it
will be pulled high.
10 PFC OUT PFC driver output 0 VCC V
11 VCC Positive supply for CM6502UHH 10 15 20 V
Maximum 3.5mA buffered output for the internal 7.5V

12 VREF 7.5 V
reference when VCC=14V
13 VFB PFC transconductance voltage error amplifier input 0 2.5 3 V
PFC transconductance voltage error amplifier output

14 VEAO (GMv) 0 6 V

SIMPLIFIED BLOCK DIAGRAM (CM6502UHH)

Bulk+ VREF
13 12 6 11 9
VFB VREF PGTHL (PGB turn off set point) VCC
PGB
GMv
VEAO -
7.52V 17.0V
14 .
REFERENCE VCC Shunt
+ PGTHL
- 3Kohm
+
2.515V RV1 (Voltage1)

2.35V RV2 (Voltage2) PGTHL-150mV
+
-
.
2.5V -
VFB +
When Veao > 2.5V (RV1)(full load)

.
2V
When Veao < 2.0V(RV2)(light load)
2.5V + VFB +
-
. 2.3V
-
Vrms
AC High Line +
Vrms > AC High Line
. SS +
Vrms - CM6502 Family Only 2.5V -

PGB PULL LOW
Vrms Control PGB

Vrms > Brown In
Vrms then PGB Pull Low
4 + PFC Brown Out
.
1.78V - Vrms < 1.0V Brown out

.
Vrms > 1.78V Brown In

1.0V Blanking
VFB PFC OVP
IAC AC Detect
+
VCC
2.75V .
-
2.6V -
24 Ohm ON
Adjustable Sagging Delay
PFC Tri-Fault
S Q PFC OUT
10
0.4V +
R Q
VFB -
17V
SS Discharge current 3uA PFC ILIMIT 12 Ohm OFF ZENER
-1.25V +
-
ISENSE
S Q
Green PFC
0.4V + R Q
Dynamic Soft VEAO -
VFB 380V-OK
PFC VFB -
PFC .
RTCT
PFCCLK=1 2.3V +
RTCT
.
Frequency
RAMP1 RTCT
7
VEAO SUPPORT
11.0V
IAC VCC
2 10.25V UVLO
Vrms
Rmul GND
Gain Modulator 8
ISENSE
3 PFC CMP
Imul
- GMi - SS
VCC Discharge 3uA
.
+
Adjustable 10uA Sagging Delay 5V

+
380V OK VCC Sagging Delay
Rmul
Charge 380V OK Discharge by 70K
Current
10uA VREF ok SW OFF T
PGB low SW OFF VCC-5V
5 Adjustable Sagging Delay = X Css
3uA(Typ)
SS 70K
REFOKB PGB
IEAO
1

ORDERING INFORMATION
Part Number Temperature Range Package
CM6502UHHXIS* -40℃ to 125℃ 14-Pin SOP (S14)
CM6502UHHXISTR* -40℃ to 125℃ 14-Pin SOP (S14)
CM6502UHHXIP* -40℃ to 125℃ 14-Pin DIP (P14)
*Note: X : Suffix for Halogen Free and PB Free Product

TR : Package is Tape & Reel
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum ratings are those values beyond which the device could be permanently damaged.
Parameter Min. Max. Units

VCC 21 V
VREF GND – 0.3 8 V
VREF (transient/load regulation) overshoot (period less than 1ms) 8.5 V
VREF (transient/load regulation) overshoot (period less than 300us) 10 V
IEAO/VEAO/Vrms/RTCT/PGTHL GND – 0.3 VREF+0.3 V
IAC/PGB/SS GND – 0.3 VCC+0.7 V
VFB GND – 0.3 5 V
ISENSE Voltage -5 0.7 V
ISENSE Voltage (period less than 1ms) -10 0.7 V
PFC OUT GND – 0.3 VCC + 0.3 V

PFC Out Driver (period less than 50ns) GND – 3.0 VCC + 0.3 V
PFC Out Driver (period less than 25ns) GND – 5.0 VCC + 0.3 V
Peak PFC OUT Current, Source or Sink 0.5 A
Peak PFC OUT Current, Source or Sink (period less than 5us) 1 A
PFC OUT, Energy Per Cycle 1.5 μJ
IREF 3.5 mA
IAC Input Current 1 mA
Junction Temperature 150 ℃
Storage Temperature Range -65 150 ℃
Operating Temperature Range -40 125 ℃
Lead Temperature (Soldering, 10 sec) 260 ℃
Thermal Resistance (θJA)

Plastic DIP 80 ℃/W
Plastic SOIC 105 ℃/W

ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply Vcc=+14V, PGTHL=+2.0V, RT = 27kΩ, CT = 1000pF, TA=Operating
Temperature Range (Note 1)
Symbol Parameter Test Conditions CM6502UHH

Unit
Min. Typ. Max.
Clean Digital PFC Brown in/Out
VRMS Threshold High Room Temperature=25℃ 1.71 1.78 1.80 V
VRMS Threshold Low Room Temperature=25℃ 0.98 1.02 1.06 V
Hysteresis 750 760 790 mV
AC high line and low line
Vrms AC High/Low line Threshold Sweep Vrms pin Vrms>3.5~3.7 high line 3.525 3.58 3.65 V
Vrms AC High line Threshold Sweep Vrms pin Vrms high line 2.9 3 3.1 V
Vrms AC Low line Threshold Sweep Vrms pin Vrms low line 1.9 2 2.1 V
Voltage Error Amplifier (GMv) VEAO
Input Voltage Range 0 6 V
Transconductance VNONINV = VINV, VEAO = 2.25V @ T=25℃ 30 40 50 μ mho
VFB(high) Feedback Reference Voltage Vrms > AC High Line Threshold
Full load (High) Veao > 2.5V and Vrms < AC high Line 2.49 2.515 2.54 V
Threshold
VFB(low) Feedback Reference Voltage Veao < 2.0V and Vrms < AC high Line
2.32 2.35 2.38 V
Light load (Low) Threshold
Light/Full Load determine (Veao Threshold)

Room Temperature=25℃ VFB=Feedback
Veao Full Load Threshold 2.4 2.5 2.6 V
Reference Voltage (High)
Room Temperature=25℃ VFB=Feedback
Veao Light Load Threshold 1.9 2 2.1 V
Reference Voltage (Low)
Hysteresis 400 500 600 mV
Output High Voltage 5.8 6.0 V
Output Low Voltage 0.1 0.4 V
Source Current Overdrive Voltage = 100mV @ T=25℃ 1 3 5 μA
Sink Current Overdrive Voltage = 100mV @ T=25℃ -45 -25 μA
Open Loop Gain DC gain 30 40 dB
Power Supply Rejection Ratio 11V < VCC < 16.5V 60 75 dB
Current Error Amplifier (GMi) IEAO
Transconductance VNONINV = VINV, IEAO = 1.5V @ T=25℃ 60 70 80 μ mho
Input Offset Voltage VEAO=0V, IAC is open -12 12 mV
Output High Voltage 6.8 7.3 7.8 V
Output Low Voltage 0.1 0.4 V

(Unless otherwise stated, these specifications apply Vcc=+14V, PGTHL=+2.0V, RT = 27kΩ, CT = 1000pF, TA=Operating
CM6502UHH
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
Sink Current ISENSE = -0.5V, IEAO = 1.5V -45 -35 -25 μA
Source Current ISENSE = +0.5V, IEAO = 4.0V 25 35 45 μA
Open Loop Gain DC Gain 30 40 dB
Power Supply Rejection Ratio 11V < VCC < 16.5V 60 75 dB
PFC OVP Comparator
Threshold Voltage 2.65 2.75 2.85 V
Hysteresis 140 240 mV
PFC Green Power Detect Comparator
Veao Threshold Voltage 0.3 0.4 0.5 V
Tri-Fault Detect
Fault Detect HIGH 2.65 2.75 2.85 V
Time to Fault Detect HIGH VFB=VFAULT DETECT LOW to

2 4 ms
VFB=OPEN, 470pF from VFB to GND
Fault Detect LOW 0.3 0.4 0.5 V
PFC ILIMIT Comparator(PFC current limit)
Threshold Voltage -1.375 -1.25 -1.125 V
(PFCILIMIT– Gain Modulator

300 450 mV
Output)
Delay to Output (Note 4) 700 ns
PGTHL(set up PGB pull high;turn off point)
PGB_CMP_LOW Sweep VFB than check PGB CMP pull low 2.1 2.3 V
Setup Vref 分壓, PGTHL=2V, VEAO=3V

PGB_CMP_HIGH Sweep VFB Voltage Check PGB CMP 1.949 2.035 V
Pull-High
Remember (Full Load) – (Light

130 150 170 mV
Load) Hysteresis

CM6502UHH
Min. Typ. Max.
GAIN Modulator
IAC = 20 μ A, VRMS =1.125, VFB = 2.375V @

Gain1 (Note 3) 5 6 7.2
T=25℃
IAC = 20 μ A, VRMS = 1.45588V, VFB =
Gain2 (Note 3 ) 4 5 6
2.375V @ T=25℃
IAC = 20 μ A, VRMS =2.91V, VFB = 2.375V @
Gain3 (Note 3) 1.2 1.4 1.6
T=25℃
IAC = 20 μ A, VRMS = 3.44V, VFB = 2.375V
Gain4 (Note 3) 0.8 1 1.2
@ T=25℃
Bandwidth (Note 4) IAC = 40 μ A 1 MHz
IAC = 50 μ A, VRMS = 1.125V, VFB = 2.375V

Output Voltage = Rmul *
0.7 0.8 0.9 V
(ISENSE-IOFFSET) VEAO=6V
I(V)mul Threshold (low) VEAO=2V 0.3 0.365 V
Oscillator (Measuring fpfc)
RT = 27 kΩ, CT = 1000pF, TA = 25℃

Initial fpfc Accuracy 1 60 66 72 kHz
IAC=0uA
Voltage Stability 11V < VCC < 16.5V 2 %
Temperature Stability 2 %
Ramp Valley to Peak Voltage VEAO=6V and IAC=20uA 2.5 V
PFC Dead Time (Note 4) 600 1000 ns
CT Discharge Current VRAMP2 = 0V, VRAMP1 = 2.5V 9 10 11 mA

CM6502UHH
Min. Typ. Max.
Reference
Output Voltage TA = 25℃, I(VREF) = 0mA 7.48 7.52 7.56 V
Line Regulation 11V < VCC < 16.5V@ T=25℃ 3 8 mV
VCC=10.5V,0mA < I(VREF) < 2.0mA;

25 50 mV
@ T=25℃
Load Regulation
VCC=14V,0mA < I(VREF) < 3.5mA;
25 50 mV
TA = -40℃~85℃
Temperature Stability 0.4 %
Total Variation Line, Load, Temp 7.3 7.7 V
Long Term Stability TJ = 125℃, 1000HRs 5 25 mV
PFC
Minimum Duty Cycle VIEAO > 4.5V 0 %
Maximum Duty Cycle VIEAO < 1.2V 93 95 %

IOUT = -20mA @ T=25℃ 12 18 ohm
Output Low Rdson IOUT = -100mA @ T=25℃ 18 ohm

IOUT = 10mA, VCC = 9V @ T=25℃ 0.5 1 V
IOUT = 20mA @ T=25℃ 24 40 ohm
Output High Rdson
IOUT = 100mA @ T=25℃ 40 ohm
Rise/Fall Time (Note 4) CL = 100pF @ T=25℃ 50 ns
Soft Start
Soft Start Current Room Temperature=25℃ 7 10 12 μA

Soft Start Discharge Current Vrms=brown out, Soft Start=VCC to 5V 1 3 5 μA
Supply
Start-Up Current VCC = 12V, CL = 0 @ T=25℃ 50 75 uA
Operating Current 14V, CL = 0 2.5 3.5 mA
Turn-On Under voltage Lockout Threshold CM6502UHH 10.5 11 11.5 V
Turn-Off Under voltage Lockout Hysteresis CM6502UHH 0.75 1.1 V
Shunt Regulator (VCC zener)
Zener Threshold Voltage Apply VCC with Iop=20mA 16.5 17 17.5 V
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the VFB pin.
-1
Note 3: Gain ~ K x 5.3V; K = (ISENSE – IOFFSET) x [IAC (VEAO – 0.7)] ; VEAOMAX = 6V
Note 4: Guaranteed by design, not 100% production test.

Getting Start Power Factor Correction
To start evaluating CM6502UHH from the exiting CM6502 , Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current drawn
need to be taken care before doing the fine tune: from the line is in phase with and proportional to the line
voltage, so the power factor is unity (one). A common class of
1.) Change RTCT pin (pin 7) from the existing value to nonlinear load is the input of most power supplies, which use a
RT=27K ohm and CT=1000pF to have fpfc = fRTCT = bridge rectifier and capacitive input filter fed from the line. The
68Khz for CM6502UHH. peak-charging effect, which occurs on the input filter capacitor
in these supplies, causes brief high-amplitude pulses of current
2.) Adjust all high voltage resistor around 5 mega ohm or
to flow from the power line, rather than a sinusoidal current in
higher first. phase with the line voltage. Such supplies present a power
3.) VRMS pin (pin 4) needs to be 1.1V at VIN=80Vac right factor to the line of less than one (i.e. they cause significant
before PFC brown out and to be 1.78V at VIN=85VAC current harmonics of the power line frequency to appear at
right before PFC brown in for universal input application their input). If the input current drawn by such a supply (or any
for line input from 85VAC to 270VAC. other nonlinear load) can be made to follow the input voltage in
instantaneous amplitude, it will appear resistive to the AC line
5.) At full load, the average Veao needs to be around 4.2V and and a unity power factor will be achieved.
the ripple on the Veao needs to be less than 300mV when To hold the input current draw of a device drawing power
the light load comparator are triggered. from the AC line in phase with and proportional to the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous line
Functional Description voltage. The PFC section of the CM6502UHH uses a
CM6502UHH is designed for high efficient power supply for boost-mode DC-DC converter to accomplish this. The input to
the converter is the full wave rectified AC line voltage. No bulk
both full load and light load. It is a ZVS-Like PFC supply
filtering is applied following the bridge rectifier, so the input
controller. voltage to the boost converter ranges (at twice line frequency)
The CM6502UHH is an average current controlled, from zero volts to the peak value of the AC input and back to
zero. By forcing the boost converter to meet two simultaneous
continuous/discontinuous boost Power Factor Correction conditions, it is possible to ensure that the current drawn from
(PFC) which uses leading edge modulation. the power line is proportional to the input line voltage. One of
these conditions is that the output voltage of the boost
In addition to power factor correction, a number of protection converter must be set higher than the peak value of the line
features have been built into the CM6502UHH. These include voltage. A commonly used value is 385VDC, to allow for a high
line of 270VACrms. The other condition is that the current drawn
soft-start, PFC over-voltage protection, peak current limiting,
from the line at any given instant must be proportional to the
brownout protection, duty cycle limiting, and under-voltage line voltage. Establishing a suitable voltage control loop for the
lockout. converter, which in turn drives a current error amplifier and
switching output driver satisfies the first of these requirements.
The second requirement is met by using the rectified AC line
voltage to modulate the output of the voltage control loop. Such
modulation causes the current error amplifier to command a
power stage current that varies directly with the input voltage.
In order to prevent ripple, which will necessarily appear at the
output of boost circuit (typically about 10VAC on a 385V DC
level); from introducing distortion back through the voltage
error amplifier, the bandwidth of the voltage loop is deliberately
kept low. A final refinement is to adjust the overall gain of the
PFC such to be proportional to 1/(Vin x Vin), which linearizes
the transfer function of the system as the AC input to voltage
varies.
Since the boost converter topology in the CM6502UHH PFC
is of the current-averaging type, no slope compensation is
required.
More exactly, the output current of the gain modulator is given

by:

Dynamic Soft PFC (patent pending)

Dynamic Soft PFC is the main feature of CM6502UHH.
Dynamic Soft PFC is to improve the efficiency, to reduce Gain=Imul/Iac
power device stress, to ease EMI, and to ease the monotonic
output design while it has the more protection such as the
K=Gain/(VEAO-0.7V)
short circuit with power-fold-back protection. Its unique
sequential control maximizes the performance and the
protections among steady state, transient and the power on/off Imul = K x (VEAO – 0.7V) x IAC
conditions. -1
Where K is in units of [V ]
PFC Section: Note that the output current of the gain modulator is limited
around 140 μ A and the maximum output voltage of the gain
Gain Modulator
modulator is limited to 140uA x 5.7K=0.8V. This 0.8V also will
Figure 1 shows a block diagram of the PFC section of the determine the maximum input power.
CM6502UHH. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the current However, IGAINMOD cannot be measured directly from ISENSE.
loop to line voltage waveform and frequency, rms line voltage, ISENSE = IGAINMOD-IOFFSET and IOFFSET can only be measured
and PFC output voltages. There are three inputs to the gain when VEAO is less than 0.5V and IGAINMOD is 0A. Typical
modulator. These are: IOFFSET is around 25uA.
1. A current representing the instantaneous input voltage
(amplitude and wave-shape) to the PFC. The rectified AC IAC=20uA, VEAO=6V
input sine wave is converted to a proportional current via a
resistor and is then fed into the gain modulator at IAC.
Sampling current in this way minimizes ground noise, as is
required in high power switching power conversion
environments. The gain modulator responds linearly to this
current.
2. A voltage proportional to the long-term RMS AC line voltage,
derived from the rectified line voltage after scaling and
filtering. This signal is presented to the gain modulator at
VRMS. The gain modulator’s output is inversely proportional
2
to VRMS . The relationship between VRMS and gain is
illustrated in the Typical Performance Characteristics of this
page.
3. The output of the voltage error amplifier, VEAO. The gain
modulator responds linearly to variations in this voltage.
The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line Gain vs. VRMS (pin4)
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way the When VRMS below 1V, the PFC is shut off. Designer needs
gain modulator forms the reference for the current error loop, to design 80VAC with VRMS average voltage= 1.14V.
and ultimately controls the instantaneous current draw of the
PFC from the power line. The general formula of the output of I SENSE − I OFFSET I MUL
the gain modulator is:
Gain = =
I AC I AC
IAC × ( VEAO - 0.7V)
Imul = x constant (1)
VRMS2 Selecting RAC for IAC pin
IAC pin is the input of the gain modulator. IAC also is a
current mirror input and it requires current input. By selecting a
proper resistor RAC, it will provide a good sine wave current
derived from the line voltage and it also helps program the
maximum input power and minimum input line voltage.
RAC=Vin min peak x 50K. For example, if the minimum line
voltage is 85VAC, the RAC=85 x 1.414 x 50K = 6.0 Mega ohm.

VRMS Description Clean Digital PFC Brown Out

Clean Digital PFC Brown Out provides a clean cut off when
VRMS pin is designed for the following functions:
AC input is much lower than regular AC input voltage such as
1. VRMS is used to detect the AC Brown Out (Also, we can 67Vac.
call it Clean Digital PFC brown out.). When VRMS is less Inside of Clean Digital PFC Brown Out, there is a comparator
than 1.03 V +/-5%, PFCOUT will be turned off and VEAO monitors the VRMS (pin 4) voltage. Clean Digital PFC Brown
will be softly discharged. When VRMS is greater than Out inhibits the PFC and VEAO (PFC error amplifier output) is
1.78V +/-5%, PFCOUT is enabled and VEAO is released. pulled down when the VRMS is lower than off threshold, 1.04V
(The off Vin voltage usually corresponds to 70Vac). When the
2. At High Line and Light Load, 380V to 355V (Vfb threshold
VRMS voltage reaches 1.75V (The On Vin voltage usually
moves from 2.515V to 2.35V) is enable for CM6502UHH.
corresponds to 86.62V and when Vin = 80Vac, VRMS =
At Low Line and Light Load, 380V to 355V (Vfb threshold
moves from 2.515V to 2.35V) is enable for CM6502UHH. 1.14V), PFC is on.
It provides ZVS-Like performance. Before PFC is turned on, VRMS (pin 4) represents the peak
voltage of the AC input. Before PFC is turned off, VRMS (pin 4)
represents the VRMS voltage of the AC input.
Current Error Amplifier, IEAO

The current error amplifier’s output controls the PFC duty
Cycle-By-Cycle Current Limiter and
cycle to keep the average current through the boost inductor a Selecting RSENSE
linear function of the line voltage. At the inverting input to the
The ISENSE pin, as well as being a part of the current
current error amplifier, the output current of the gain modulator feedback loop, is a direct input to the cycle-by-cycle current
is summed with a current which results from a negative voltage limiter for the PFC section. Should the input voltage at this pin
being impressed upon the ISENSE pin. The negative voltage on ever be more negative than –1.3V, the output of the PFC will
ISENSE represents the sum of all currents flowing in the PFC be disabled until the protection flip-flop is reset by the clock
circuit, and is typically derived from a current sense resistor in pulse at the start of the next PFC power cycle.
RS is the sensing resistor of the PFC boost converter. During
series with the negative terminal of the input bridge rectifier.
the steady state, line input current x RSENSE = Imul x 5.7K. Since
the maximum output voltage of the gain modulator is Imul max x
In higher power applications, two current transformers are
5.7K= 0.8V during the steady state, RSENSE x line input current
sometimes used, one to monitor the IF of the boost diode. As will be limited below 0.8V as well. When VEAO reaches
stated above, the inverting input of the current error amplifier is maximum VEAO which is 6V, Isense can reach -0.8V. At 100%
a virtual ground. Given this fact, and the arrangement of the load, VEAO should be around 4.5V and ISENSE average peak
duty cycle modulator polarities internal to the PFC, an increase is -0.6V. It will provide the optimal dynamic response +
tolerance of the components.
in positive current from the gain modulator will cause the
output stage to increase its duty cycle until the voltage on Therefore, to choose RSENSE, we use the following equation:
ISENSE is adequately negative to cancel this increased current.
RSENSE + RParasitic =0.6V x Vinpeak / (2 x Line Input power)
Similarly, if the gain modulator’s output decreases, the output
duty cycle will decrease, to achieve a less negative voltage on For example, if the minimum input voltage is 80VAC, and the
the ISENSE pin. maximum input rms power is 200Watt, RSENSE + RParasitic =
(0.6V x 80V x 1.414) / (2 x 200) = 0.169 ohm. The designer
needs to consider the parasitic resistance and the margin of
Error Amplifier Compensation
the power supply and dynamic response. Assume RParasitic = 30
The PWM loading of the PFC can be modeled as a negative mOhm, RSENSE = 139 mOhm.
resistor; an increase in input voltage to the PWM causes a
decrease in the input current. This response dictates the
PFC OVP
proper compensation of the two transconductance error
amplifiers. Figure 2 shows the types of compensation networks In the CM6502UHH, PFC OVP comparator serves to protect
most commonly used for the voltage and current error the power circuit from being subjected to excessive voltages if
amplifiers, along with their respective return points. The current the load should suddenly change. A resistor divider from the
loop compensation is returned to VREF to produce a soft-start high voltage DC output of the PFC is fed to VFB. When the
characteristic on the PFC: as the reference voltage comes up voltage on VFB exceeds 2.79V, the PFC output driver is shut
from zero volts, it creates a differentiated voltage on IEAO which down. The PWM section will continue to operate. The OVP
prevents the PFC from immediately demanding a full duty comparator has 250mV of hysteresis, and the PFC will not
cycle on its boost converter. restart until the voltage at VFB drops below 2.54V. The VFB
power components and the CM6502UHH are within their safe
operating voltages, but not so low as to interfere with the boost
voltage regulation loop.

PFC Voltage Loop

There are two major concerns when compensating the The Current Loop Gain (S)
voltage loop error amplifier, VEAO; stability and transient
ΔVISENSE ΔD OFF ΔIEAO
response. Optimizing interaction between transient response = * *
and stability requires that the error amplifier’s open-loop ΔDOFF ΔIEAO ΔISENSE
crossover frequency should be 1/2 that of the line frequency,
VOUTDC * R S
or 23Hz for a 47Hz line (lowest anticipated international power ≈ * GMI * ZCI
frequency). S * L * 2.5V
deviate from its 2.5V (nominal) value. If this happens, the
transconductance of the voltage error amplifier, GMv will ZCI: Compensation Net Work for the Current Loop
increase significantly, as shown in the Typical Performance GMI: Transconductance of IEAO
Characteristics. This raises the gain-bandwidth product of the VOUTDC: PFC Boost Output Voltage; typical designed value is
voltage loop, resulting in a much more rapid voltage loop 380V and we use the worst condition to calculate the ZCI
response to such perturbations than would occur with a
RSENSE: The Sensing Resistor of the Boost Converter
conventional linear gain characteristics.
2.5V: The Amplitude of the PFC Leading Edge Modulation
The Voltage Loop Gain (S) Ramp(typical)
ΔVOUT ΔVFB ΔVEAO L: The Boost Inductor
= * *
ΔVEAO ΔVOUT ΔVFB The gain vs. input voltage of the CM6502UHH’s voltage error
PIN * 2.5V amplifier, VEAO has a specially shaped non-linearity such that
≈ 2
* GMV * ZCV
VOUTDC * ΔVEAO * S * CDC under steady-state operating conditions the transconductance
of the error amplifier, GMv is at a local minimum. Rapid
ZCV: Compensation Net Work for the Voltage Loop perturbation in line or load conditions will cause the input to the
GMv: Transconductance of VEAO voltage error amplifier (VFB) to
PIN: Average PFC Input Power
ISENSE Filter, the RC filter between RSENSE and ISENSE :
VOUTDC: PFC Boost Output Voltage; typical designed value is
380V. There are 2 purposes to add a filter at ISENSE pin:
CDC: PFC Boost Output Capacitor
1.) Protection: During start up or inrush current conditions, it
PFC Current Loop will have a large voltage cross Rs which is the sensing
resistor of the PFC boost converter. It requires the ISENSE
The current transcondutance amplifier, GMi, IEAO
Filter to attenuate the energy.
compensation is similar to that of the voltage error amplifier,
VEAO with exception of the choice of crossover frequency.
The crossover frequency of the 2.) To reduce L, the Boost Inductor: The ISENSE Filter To
current amplifier should be at least 10 times that of reduce L, the Boost Inductor: The ISENSE Filter also can
the voltage amplifier, to prevent interaction with the voltage
reduce the Boost Inductor value since the ISENSE Filter
loop. It should also be limited to less than 1/6th that of the
switching frequency, e.g. 8.33kHz for a 50kHz switching behaves like an integrator before going ISENSE which is the
frequency. input of the current error amplifier, IEAO.
The ISENSE Filter is a RC filter. The resistor value of the ISENSE
Filter is 50 ohm because IOFFSET x the resistor can generate an
offset voltage of IEAO. By selecting RFILTER equal to 50ohm will
keep the offset of the IEAO less than 10mV. Usually, we
design the pole of ISENSE Filter at fpfc/6~fpfc=8.33Khz, one
sixth of the PFC switching frequency. Therefore, the boost
inductor can be reduced 6 times without disturbing the stability.
Therefore, the capacitor of the ISENSE Filter, CFILTER, will be
around 382.1nF.

Bulk+ VREF
13 12 6 11 9
VFB VREF PGTHL (PGB turn off set point) VCC
PGB
GMv
VEAO -
7.52V 17.0V
14 .
REFERENCE VCC Shunt
+ PGTHL
- 3Kohm
+
2.515V RV1 (Voltage1)

2.35V RV2 (Voltage2) PGTHL-150mV
+
-
.
2.5V -
VFB +
.
2V When Veao > 2.5V (RV1)(full load)

When Veao < 2.0V(RV2)(light load)
2.5V + VFB +
-
. 2.3V
-
Vrms
AC High Line +
Vrms > AC High Line
. SS +
Vrms - CM6502 Family Only 2.5V -

PGB PULL LOW
Vrms Control PGB

Vrms > Brown In
Vrms then PGB Pull Low
4 + PFC Brown Out
.
1.78V - Vrms < 1.0V Brown out

.
Vrms > 1.78V Brown In

1.0V Blanking
VFB PFC OVP
IAC AC Detect
+
VCC
2.75V .
-
2.6V -
24 Ohm ON
Adjustable Sagging Delay
PFC Tri-Fault
S Q PFC OUT
10
0.4V +
R Q
VFB -
17V
SS Discharge current 3uA PFC ILIMIT 12 Ohm OFF ZENER
-1.25V +
-
ISENSE
S Q
Green PFC
0.4V + R Q
Dynami c Soft VEAO -
VFB 380V-OK
PFC VFB -
PFC
RTCT .
PFCCLK=1 2.3V +
RTCT
.
Frequency
RAMP1 RTCT
7
VEAO SUPPORT
11.0V
IAC VCC
2 10.25V UVLO
Vrms
Rmul GND
Gain Modulator 8
ISENSE
3 PFC CMP
Imul
- GMi - SS
VCC Discharge 3uA
.
+
Adjustable 10uA Sagging Delay 5V

+
380V OK VCC Sagging Delay
Rmul
Charge 380V OK Discharge by 70K
Current
10uA VREF ok SW OFF T
PGB low SW OFF VCC-5V
5 Adjustable Sagging Delay = X Css
3uA(Typ)
SS 70K
REFOKB PGB
IEAO
1
Figure 1. PFC Section Block Diagram

Oscillator (RAMP1, or called RTCT) Soft Start (ISS)
In CM6502UHH, fRTCT = fpfc fRTCT =68Khz, when There is a ~ 10uA to charge ISS pin. The PFC-soft-start function
VEAO=0V, it provides the best performance in the PC is implemented with ISS pin.
application.
The oscillator frequency, fRTCT is the similar formula in
CM6800: After PFC Brown Out condition is removed (Vrms is greater than
1.75V.), ISS potential will be raised by the 10uA charge current.
fRTCT = 1 ISS potential also determines the VFB threshold until ISS is
tRAMP + tDEADTIME
greater than 2.5V. Therefore, before ISS reaching 2.5V, PFC bulk
The dead time of the oscillator is derived from the output voltage is determined by ISS potential until ISS reaching
following equation:
2.5V.
tRAMP = CT x RT x In VREF − 0.78
VREF − 3.7
at VREF = 7.52V:
tRAMP = CT x RT x 0.5678
The dead time of the oscillator may be determined using:
tDEADTIME = 2.92V x CT = 292 x CT
10.0mA
The dead time is so small (tRAMP >> tDEADTIME ) that the

operating frequency can typically be approximately by:
1
fRTCT =
tRAMP
Ct should be greater than 470pF.
Let us use 1000PF Solving for RT yields 27K. Selecting

standard components values, CT = 1000pF, and RT = 27kΩ
The dead time of the oscillator determined PFC minimum

off time which is the dead time.

Generating VCC
A filter network is recommended between VCC (pin 11) and
After turning on CM6502UHH at 11V, the operating voltage bootstrap winding. The resistor of the filter can be set as
can vary from 10V to 21V. That’s the two ways to generate following.
VCC. One way is to use auxiliary power supply around 15V, RFILTER x IVCC ~ 2V, IVCC = IOP + (QPFCFET + QPWMFET ) x fsw
and the other way is to use bootstrap winding to self-bias IOP = 2.1mA (typ.)
CM6502UHH system. The bootstrap winding can be either
taped from PFC boost choke or from the transformer of the If anything goes wrong, and VCC goes beyond 19.4V, the
DC to DC stage. The ratio of winding transformer for the PFC gate (pin 10) drive goes low remains function. The
bootstrap should be set between 18V and 15V. resistor’s value must be chosen to meet the operating current
requirement of the CM6502UHH itself (5mA, max.) plus the
current required by the two gate driver outputs.
EXAMPLE:
With a wanting voltage called, VBIAS ,of 18V, a VCC of 15V
and the CM6502UHH driving a total gate charge of 90nC at
100kHz (e.g. 1 IRF840 MOSFET and 2 IRF820 MOSFET),
the gate driver current required is:
IGATEDRIVE = 100kHz x 90nC = 9mA
RBIAS =
VBIAS − VCC
ICC + IG
RBIAS = 18V − 15V
5mA + 9mA
In case of leading edge modulation, the switch is turned Choose RBIAS = 214Ω
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier The CM6502UHH should be locally bypassed with a 1.0 μ F
output voltage, the switch will be turned ON. The effective ceramic capacitor. In most applications, an electrolytic
duty-cycle of the leading edge modulation is determined capacitor of between 47 μ F and 220 μ F is also required
during OFF time of the switch. across the part, both for filtering and as part of the start-up
bootstrap circuitry.
Figure 5 shows a leading edge control scheme.
One of the advantages of this control technique is that it Leading/Trailing Modulation
required only one system clock. Switch 1(SW1) turns off and
switch 2 (SW2) turns on at the same instant to minimize the Conventional Pulse Width Modulation (PWM) techniques
momentary “no-load” period, thus lowering ripple voltage employ trailing edge modulation in which the switch will turn
generated by the switching action. With such synchronized on right after the trailing edge of the system clock. The error
switching, the ripple voltage of the first stage is reduced. amplifier output is then compared with the modulating ramp
Calculation and evaluation have shown that the 120Hz up. The effective duty cycle of the trailing edge modulation is
component of the PFC’s output ripple voltage can be determined during the ON time of the switch. Figure 4 shows
reduced by as much as 30% using this method. a typical trailing edge control scheme.

TYPICAL APPLCATION CIRCUIT

PFC F1
T2 T1
250V 6.3A HSB TR18*10*10 BD1
L TR18*10*10
1 D10XB60
H15 (10A/600V)
3
C5
FR1 (High inrush current resister)
1
4
220pF/2KV C3 1
+ - 4
910K 1/2W C2
0.22uF 275V 0.22uF 275V
C6 BC1
2
3
1uF/450V R2
2
220pF/2KV
N 0.1
t
1
H14 RT1
2.5Ω/5A
Q26 VCCP
2 1
RL1 NC
835NL-1A-B-C 9V 4 3 2 3
C69 D23
1
NC NC
R92
ZD6 NC
NC
380VDC
D6
L4 1N5406 (3A/600V)
CS-270026
R6 7 5
2.2M
R26 380VDC 9
D7
47 HFA08TB60
R1 (8A/600V)
R15
1M 1%
2M R17
150K
Vref/1 U1 R100
D28
C11 VCCP
2
R25 CM6500/02 Family C12 10K
10K 33n 0.47uF Q1
R24 1N4148 1
IEAO VEAO
14 1
20N60C3
C20 C19 Q3
1M 1000pF 100pF R3 (20A/600V) C9
3
2N2222
3
D29 1M 1% 1
+
220uF/450V
R39
R23 1N4148 2
IAC VFB
13
10
1M
2
R34
D30 VCCP 13K 1%
2
3 12
R23-1 1N4148 C22
ISENSE VREF Vref/1 C10 1
D4
C16 102pF
0.47uF 243K 0.047UF Q2 SCS140P R20
C71 C70
2N2907 22K
3
4 11 +
Vrms VCC 0.1uF 22uF/25V
R23-2 C17
36.5K 0.47uF 5
SS PFC OUT
10
C21 R11
1000pF PGB R33
10
6 9 0
Vref/1 PGTHL PGB PGIB/1
R12 C25 R13 R38 R9 C77
27K 0.1uF 69.8K 1% 27K NC 4700P
7 8
RAMP1 GND
C18
1000pF
12VS
Standby D11
EFM103 (1A/150V)
Q8
2N2222
3 1
R44 R95
4.7KΩ 4.7KΩ
380VDC C29
2
+
R43 ZD9 47uF/25V
1 1W(S) Q27
C28
+
2N7002 ZMM(11V)
ZD1 R45 100uF/25V ZD2 +12V
C76 3M ZMM(15V) R96 C75
+
P6KE150A
100uF/400V 5% C30 47KΩ 0.47uF
NC T3
EE-19
R46 1.4mH
1M 6 11.5TS
8TS
L1 ON/OFF
D12 1 PC2A
BYV-26E 8
DR6*8.3 LTV817
85TS 7
2
8TS 12VSB
C33 R47 C31
470UF/25V
+ 2A
4 1000pF/50V 20
5 C32 +
ZD3
D13 11TS 1200UF/16V
+ C34 SF14
1 NC
100uF/35V 3
D14
SB10100
2 3
VCC
R48 C35
+
5 4
GND D 15K 10uF/25V
6
GND .
3 D15 R49
7 2
1N4007 100 VDD
GND BP (1A/1000V)
8 1
GND EN
U2 TNY277P C36
4
PC3A R52
R54 ZD5
30 NC 1K
C37 HZ15-2 817C
0.1UF/50V
3
14.50~15.10V
C38 +
10uF/50V R93
R55 3 1 22
R56 10K 1% VCC VCCP
Q9
150 C40 R58 PC2B 2N2222
0.1UF/25V 10K
2
R50
LTV817
CN2 7.5K
3
C68 CON2
C41 1
222M/250V Y1 NC
1
+12V 12VSB IC1 ZD4

R59 1N4745A
2
KA431AZ1 2.54K 1% 15.2~16.8V

R94
D10 ON/OFF 5.6K
NC

DC-DC 380VDC
D16
1N4148
DRVH C42
R60 Q12
NC 12VSYNDRVL
10Ω FCP11N60
R61 R62
47KΩ Lp(1.7mH) 47KΩ
PQ3230 Q13
L2
C43
+12VIS +12V
9
160uh/PQ512
6 2
T4 IR F2804PBF L3
DRVHGND 8 130nH/20A
5 10
82nF/800V 2TS
D17
1N4148 27TS C45
12VSYNDRVH C47 C48
3300 uF/16V
2 200uF/16 V
9
470u F/1 6V
1
10 + +
C46 + +
Q14 C49
DRVL FCP11N60 2TS Q15 2200uF/25V C50 C51
R63 IR F2804PBF R64 0.1uF 0.1uF 0.1uF
10Ω C52 11 47KΩ
NC JP11
OUT
R65 7 R91
0 NC
47KΩ 2TS R98
D18 C54 C53 +
EFM204 0.1uF 10KΩ 680uF/25V IPLIMIT

12
-12V
(2A/200V)
IPLIMIT
R66
D19 5.6
BAV99
C56 C55 R67
1uF/50V 105pF 470
D20
BAV99
SLS Controller
12VS SD
+12V 12VS
R40
5.1K 12VS
Vref/1
1
Q18 D22
PC1A
817B 2N7002 SCS140P Q16
2N2222 C58
2
REMOTEOFF/FPOB 1uF/50V T5
PGB R41 C57 +
ZD5 EE-19
20K 1N4148 47uF/25V
5
R102 DRVH
100K Q17
2N2907
6
PGB From R101 3 DRVHGND
8.2K
CM6500/02 Family
PGI 12VS
+12V R42 C79 C27 C59 2 7

1.8K 1nF 334 333 Q20
DRVL
2N2222
8
R73
R72 316K 1%
12K
Q21
U3 CM6901 Family 12VS 2N2907
R74
750 1 16
2
Rset VREF
15
VREF 12VS
VFB VCC
3 14
Q22
FEAO PRIDRV 2N2222
4
D_IN- PRIDRVB
13
R76
VREF 22Ω
C60 5
D_IN+ SRDRV
12
4700pF R75 6 11
12VSYNDRVH
DEAO SRDRVB
36.5KΩ
R78 7 10 R79 12VS D26
C62 R77 SD CSS GND
56KΩ SCS140P
3.3K 220KΩ 8 9
NC Ilim RT/CT
VREF Q23
R84 C63 R88 2N2907
R80 R deao1 R deao2 R87 1KΩ
51K 1uF/16V R85 C64 C66
6KΩ
33KΩ 1M 3M
27KΩ
C65
C67 12VS
47pF 1uF/25V 1000pF Q24
IPLIMIT 0.1uF/25V 2N2222
R89
22Ω
12VSYNDRVL
VREF
D27
Q25 SCS140P
2N2907

PACKAGE DIMENSION
14-PIN SOP (S14)
14-PIN DIP (P14)

IMPORTANT NOTICE
Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to
discontinue any integrated circuit product or service without notice, and advises its customers to obtain
the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
A few applications using integrated circuit products may involve potential risks of death, personal injury,
or severe property or environmental damage. CMC integrated circuit products are not designed,
intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems
or other critical applications. Use of CMC products in such applications is understood to be fully at the
risk of the customer. In order to minimize risks associated with the customer’s applications, the
customer should provide adequate design and operating safeguards.
HsinChu Headquarter Sales & Marketing
5F, No. 11, Park Avenue II, 21F., No. 96, Sec. 1, Sintai 5th Rd., Sijhih City,
Science-Based Industrial Park, Taipei County 22102,
HsinChu City, Taiwan Taiwan, R.O.C.
T E L : +886-3-567 9979 T E L : +886-2-2696 3558
F A X : +886-3-567 9909 F A X : +886-2-2696 3559
http://www.champion-micro.com

Cm6502 Apfc Chip (Epa90+ Zvs Type)

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CM6502UHH (1MHz PFC)

http://www.championmicro.com.tw EPA/90+ ZVS-Like PFC CONTROLLER

GENERAL DESCRIPTION FEATURES

2014/11/11 Rev. 1.0 Champion Microelectronic Corporation 1

APPLICATIONS PIN CONFIGURATION

 Internet Server Power Supply

 LCD Power Supply 1 IEAO VEAO 14

 IPC Power Supply 3 ISENSE VREF 12

PFC transconductance current error amplifier output

IAC has 2 functions:

PFC Current Sense: for both Gain Modulator and PFC

1)PFC Soft Start pin: It supplies ~ 10uA to SS pin. It provides a

Soft Start function can adjust by a simple capacitor to ground and

it can be around 1uF.

PGTHL(PGB comparator), SS pin is discharged through an

internal ~ 70K Ohm resistor.

2014/11/11 Rev. 1.0 Champion Microelectronic Corporation 2

PGTHL is an input I/O. The user can program the Low

7 RTCT Oscillator timing node; timing set by RT and CT 0.8 4 V

PGB is the PG comparator output. The input of PG

10 PFC OUT PFC driver output 0 VCC V

11 VCC Positive supply for CM6502UHH 10 15 20 V

Maximum 3.5mA buffered output for the internal 7.5V

13 VFB PFC transconductance voltage error amplifier input 0 2.5 3 V

PFC transconductance voltage error amplifier output

2014/11/11 Rev. 1.0 Champion Microelectronic Corporation 3

SIMPLIFIED BLOCK DIAGRAM (CM6502UHH)

2.515V RV1 (Voltage1)

When Veao > 2.5V (RV1)(full load)

Vrms - CM6502 Family Only 2.5V -

Vrms Control PGB

1.78V - Vrms < 1.0V Brown out

Vrms > 1.78V Brown In

Dynamic Soft VEAO -

Adjustable 10uA Sagging Delay 5V

2014/11/11 Rev. 1.0 Champion Microelectronic Corporation 4

Part Number Temperature Range Package

CM6502UHHXIS* -40℃ to 125℃ 14-Pin SOP (S14)

CM6502UHHXISTR* -40℃ to 125℃ 14-Pin SOP (S14)

CM6502UHHXIP* -40℃ to 125℃ 14-Pin DIP (P14)

*Note: X : Suffix for Halogen Free and PB Free Product

ABSOLUTE MAXIMUM RATINGS

Parameter Min. Max. Units

ISENSE Voltage (period less than 1ms) -10 0.7 V

PFC OUT GND – 0.3 VCC + 0.3 V

Storage Temperature Range -65 150 ℃

Operating Temperature Range -40 125 ℃

Lead Temperature (Soldering, 10 sec) 260 ℃

Thermal Resistance (θJA)

Plastic SOIC 105 ℃/W

2014/11/11 Rev. 1.0 Champion Microelectronic Corporation 5

Symbol Parameter Test Conditions CM6502UHH

Light/Full Load determine (Veao Threshold)

2014/11/11 Rev. 1.0 Champion Microelectronic Corporation 6

Sink Current ISENSE = -0.5V, IEAO = 1.5V -45 -35 -25 μA

Source Current ISENSE = +0.5V, IEAO = 4.0V 25 35 45 μA

Open Loop Gain DC Gain 30 40 dB

Power Supply Rejection Ratio 11V < VCC < 16.5V 60 75 dB

PFC OVP Comparator

Threshold Voltage 2.65 2.75 2.85 V

Internet Server Power Supply

LCD Power Supply 1 IEAO VEAO 14

IPC Power Supply 3 ISENSE VREF 12