UL

®
LSI/CSI LS7166
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
A3800

August 2006
24-BIT QUADRATURE COUNTER
FEATURES: PIN ASSIGNMENTS - Top View
• Programmable modes are: Up/Down, 20-PIN
Binary, BCD, 24 Hour Clock, Divide-by-N, DIP and SOIC

x1 or x2 or x4 Quadrature and Single-Cycle. WR 1 20 VSS ( -V )

LSI
• DC to 25MHz Count Frequency.
CS 2 19 RD
• 8-Bit I/O Bus for uP Communication and Control.
• 24-Bit comparator for pre-set count comparison. LCTR/LLTC 3 18 C/D
• Readable status register.
• Input/Output TTL and CMOS compatible. ABGT/RCTR 4 17 BW

• 3V to 5.5V operation (VDD - VSS).

LS7166
VDD ( +V) 5 16 CY
• LS7166 (DIP); LS7166-S (SOIC);
LS7166-TS24 (24-Pin TSSOP) - See Figure 1 - A 6 15 D7

B 7 14 D6
GENERAL DESCRIPTION:
The LS7166 is a CMOS, 24-bit counter that can be pro- D0 8 13 D5
grammed to operate in several different modes. The oper-
D1 9 12 D4
ating mode is set up by writing control words into internal
control registers (see Figure 8). There are three 6-bit and D2 10 11 D3
one 2-bit control registers for setting up the circuit functional
characteristics. In addition to the control registers, there is a 24-PIN
5-bit output status register (OSR) that indicates the current TSSOP
counter status. The IC communicates with external circuits
through an 8-bit three state I/O bus. Control and data words WR 1 24 VSS ( - V )
LSI

are written into the LS7166 through the bus. In addition to 2 23 RD

CS
the I/O bus, there are a number of discrete inputs and out-
puts to facilitate instantaneous hardware based control func- LCTR/LLTC 3 22 C/D
tions and instantaneous status indication.
ABGT/RCTR 4 21 VDD ( +V)

REGISTER DESCRIPTION: NC 5 20 BW
Internal hardware registers are accessible through the I/O
LS7166

NC 6 19 CY
bus (D0 - D7) for READ or WRITE when CS = 0. The C/D in-
put selects between the control registers (C/D = 1) and the NC 7 18 NC
data registers (C/D = 0) during a READ or WRITE operation.
A 8 17 D7
(See Table 1)
B 9 16 D6

D0 10 15 D5

D1 11 14 D4
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems, D2 12 13 D3
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
FIGURE 1

7166-082906-1
 PR (Preset register). The PR is the input port for the CNTR. The CNTR is loaded with a 24 bit data via the PR. The
data is first written into the PR in 3 WRITE cycle sequence of Byte 0 (PR0), Byte 1 (PR1) and Byte 2 (PR2).
The address pointer for PR0/PR1/PR2 is automatically incremented with each write cycle.
Accessed by: WRITE when C/D = 0, CS = 0.

Bit # 7----------0 7---------- 0 7----------0

PR2 PR1 PR0

(BYTE 2) (BYTE 1) (BYTE 0)

Standard Sequence for Loading PR and Reading CNTR:

1 MCR ; Reset PR address pointer
WRITE PR ; Load Byte 0 and into PR0 increment address
WRITE PR ; Load Byte 1 and into PR1 increment address
WRITE PR ; Load Byte 2 and into PR3 increment address
8 MCR ; Transfer PR to CNTR

MCR (Master Control Register). Performs register reset and load operations. Writing a "non-zero” word to MCR does
not require a follow-up write of an “all-zero” word to terminate a designated operation.
Accessed by: WRITE when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0
0 0

1: Reset PR/OL address pointer

1: Transfer CNTR to OL (24 bits)
1: Reset CNTR, BWT and CYT. Set SIGN bit.
(CNTR = 0, BWT = 0, CYT = 0, SIGN = 1)
1: Transfer PR to CNTR (24 bits)
1: Reset COMPT (COMPT = 0)
1: Master reset. Reset CNTR, ICR, OCCR, QR, BWT, CYT, OL
COMPT, and PR/OL address pointer. Set PR (PR = FFFFFF) and SIGN.
0: Select MCR
0:
NOTE: Control functions may be combined.

ICR (Input Control Register). Initializes counter input operating modes.

Accessed by: WRITE when C/D = 1, CS = 0.
Bit # 7 6 5 4 3 2 1 0
0 1
0: Input A = Up count input, Input B = Down count input
1: Input A = Count input, Input B = Count direction input (overridden in
quadrature mode) where B = 0 selects up count mode and B = 1
selects Down count mode.
(NOTE: During counting operation B may switch only when A = 1.)
0: NOP
1: Increment CNTR once (A/B = 1, if enabled)
0: NOP
1: Decrement CNTR once (A/B = 1, if enabled)
0: Disable inputs A/B
1: Enable inputs A/B
0: Initialize Pin 4 as CNTR Reset input (Pin 4 = RCTR)
1: Initialize Pin 4 as Enable/Disable gate for A/B inputs (Pin 4 = ABGT)
0: Initialize Pin 3 as CNTR load input (Pin 3 = LCTR)
1: Initialize Pin 3 as OL load input (Pin 3 = LLTC)
1: Select ICR
0:

NOTE: Control functions may be combined.

7166-110103-2
 TABLE 1 - Register Addressing Modes

D7 D6 C/D RD WR CS COMMENT
X X X X X 1 Disable Chip for READ/WRITE
0 0 1 1 0 Write to Master Control Register (MCR)

0 1 1 1 0 Write to input control register (ICR)

1 0 1 1 0 Write to output/counter control register (OCCR)

1 1 1 1 0 Write to quadrature register (QR)

X X 0 1 0 Write to preset register (PR) and increment register
address counter.

X X 0 1 0 Read output latch (OL) and increment register

address counter

X X 1 1 0 Read output status register (OSR).

X = Don't Care

OSR (Output Status Register). Indicates CNTR status: Accessed by: READ when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0
U U U 0/1 0/1 0/1 0/1 0/1

BWT. Borrow Toggle Flip-Flop. Toggles everytime CNTR underflows

generating a borrow.
CYT. Carry Toggle Flip-Flop. Toggles everytime CNTR overflows
generating a carry.
COMPT. Compare Toggle Flip-Flop. Toggles everytime CNTR equals PR
SIGN. Sign bit. Reset ( = 0) when CNTR underflows
Set ( = 1) when CNTR overflows
UP/DOWN. Count direction indicatior in quadrature mode.
Reset ( = 0) when counting down
Set ( = 1) when counting up
U = Undefined
(Forced to 1 in non-quadrature mode)

OL(Output latch). The OL is the output port for the CNTR. The 24 bit CNTR Value at any instant can be accessed
by performing a CNTR to OL transfer and then reading the OL in 3 READ cycle sequence of Byte 0 (OL0), Byte 1 (OL1)
and Byte 2 (OL2). The address pointer for OL0/OL1/OL2 is automatically incremented with each READ cycle.
Accessed by: READ when C/D = 0, CS = 0.

Bit # 7 0 7 0 7 0

OL2 OL1 OL0

(BYTE 2) (BYTE 1) (BYTE 0)

Standard Sequence for Loading and Reading OL:

3 MCR ; Reset OL address pointer and Transfer CNTR to OL
READ OL ; Read Byte 0 and increment address
READ OL ; Read Byte 1 and increment address
READ OL ; Read Byte 2 and increment address

7166-110103-3
 OCCR (Output Control Register) Initializes CNTR and output operating modes.
Accessed by : WRITE when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0
1 0
0: Binary count mode (Overridden by D3 = 1).
1: BCD count mode (Overridden by D3 = 1)
0: Normal count mode
1: Non-Recycle count mode. (CNTR enabled with a Load or Reset
CNTR and disabled with generation of Carry or Borrow.
In this mode no external CY or BW is generated. Instead
CYT or BWT should be used as cycle completion indicator.)
0: Normal count mode

1: Divide by N count mode (CNTR is reloaded with PR data upon

Carry or Borrow).
0: Binary or BCD count mode (see D0)
1: 24 Hour Clock mode with Byte 0 = Sec, Byte 1 = Min and Byte 2 = Hr.
(Overrides BCD/Binary Modes)
0 Pin 16 = CY, Pin 17 = BW. (Active Low)
0
1 Pin 16 = CYT, Pin 17 = BWT
0
0 Pin 16 = CY, Pin 17 = BW. (Active high)
1
1 Pin 16 = COMP, Pin 17 = COMPT
1
0 Select OCCR
1

QR (Quadrature Register). Selects quadrature count mode (See Fig. 7)

Accessed by: WRITE when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0
1 1 X X X X
0
Disable quadrature mode
0

1
Enable x1 quadrature mode
0

0 Enable x2 quadrature mode

1

1 Enable x4 quadrature mode

1

1
Select QR
1
X = Don’t Care
7166-110103-4
 I/O DESCRIPTION:
(See REGISTER DESCRIPTION for I/O Prgramming.) ABGT/RCTR (Pin 4). This input can be programmed to function
as either inputs A and B enable gate or as external counter reset
Data-Bus (D0 - D7) (Pin 8 - Pin 15). The 8-line data bus is a input. A logical "0" is the active level on this input. In non-
three-state I/O bus for interfacing with the system bus. quadrature mode, if Pin 4 is programmed as A and B enable gate
input, it may switch state only when A is high (if A is clock and B
CS (Chip Select Input) (Pin 2). A logical "0" at this input enables is direction) or when both A and B are high (if A and B are
the chip for Read and Write. clocks). In quadrature mode, if Pin 4 is programmed as A and B
enable gate, it may switch state only when either A or B switches.
RD (Read Input) (Pin 19). A logical "0" at this input enables the
OSR and the OL to be read on the data bus. LCTR/LLTC (Pin 3 ) This input can be programmed to function
as the external load command input for either the CNTR or the
WR (Write Input) (Pin 1). A logical "0" at this input enables the OL. When programmed as counter load input, the counter is
data bus to be written into the control and data registers. loaded with the data contained in the PR. When programmed as
the OL load input, the OL is loaded with data contained in the
C/D (Control/Data Input) (Pin 18). A logical "1" at this input en- CNTR. A logical "0" is the active level on this input.
ables a control word to be written into one of the four control reg-
isters or the OSR to be read on the I/O bus. A logical "0" enables CY (Pin 16) This output can be programmed to serve as one of
a data word to be written into the PR, or the OL to be read on the the following:
I/O bus. A. CY. Complemented Carry out (active "0").
B. CY. True Carry out (active "1").
A (Pin 6). Input A is a programmable count input capable of C. CYT. Carry Toggle flip-flop out.
functioning in three different modes, such as up count input, down D. COMP. Comparator out (active "0")
count input and quadrature input. In non-quadrature mode, the
counter advances on the rising edge of Input A. BW (Pin 17) This output can be programmed to serve as one of
the following:
B (Pin 7). Input B is also a programmable count input that can be A. BW. Complemented Borrow out (active "0").
programmed to function either as down count input, or count B. BW. True Borrow out (active "1").
direction control gate for input A, or quadrature input. In non- quad- C. BWT. Borrow Toggle flip-flop out.
rature mode, and when programmed as the Down Count input, the D. COMPT. Comparator Toggle output.
counter advances on the rising edge of Input B. When B is pro-
grammed as the count direction control gate, B = 0 enables A as VDD (Pin 5) Supply voltage positive terminal.
the Up Count input and B = 1 enables A as the Down Count input.
When programmed as the direction input, B can switch state only VSS (Pin 20) Supply voltage negative terminal.
when A is high.

Absolute Maximum Ratings:

Parameter Symbol Values Unit
Voltage at any input VIN VSS - 0.3 to VDD + 0.3 V
Operating Temperature TA -40 to +125 oC
Storage Temperature TSTG -65 to +150 oC
Supply Voltage VDD - VSS +7.0 V

DC Electrical Characteristics. (All voltages referenced to VSS.

TA = 0˚ to 85˚C, VDD = 3V to 5.5V, fc = 0, unless otherwise specified)

Parameter Symbol Min. Value Max.Value Unit Remarks

Supply Voltage VDD 3.0 5.5 V -
Supply Current IDD - 350 µA Outputs open
Input Low Voltage VIL 0 0.8 V -
Input High Voltage VIH 2.0 VDD V -
Output Low Voltage VOL - 0.4 V 4mA Sink, VDD = 5V
Output High Voltage VOH 2.5 - V 200µA Source, VDD = 5V
Input Current - - 15 nA Leakage
Current
Output Source Current ISRC 200 - µA VOH = 2.5V, VDD = 5V
Output Sink Current ISINK 4 - mA VOL = 0.4V, VDD = 5V
Data Bus Off-State
Leakage Current - - 15 nA -

7166-082906-5
 TRANSIENT CHARACTERISTICS (See Timing Diagrams in Fig. 2 thru Fig. 7,
VDD = 3V to 5.5V, TA = 0˚ to 85˚C, unless otherwise specified)

Parameter Symbol Min.Value Max.Value Unit

Clock A/B "Low” TCL 18 No Limit ns
Clock A/B "High" TCH 22 No Limit ns
Clock A/B Frequency fc 0 25 MHz
(See NOTE 1)
Clock UP/DN Reversal TUDD 100 - ns
Delay
LCTR Positive edge to TLC 100 - ns
the next A/B positive or
negative edge delay
Clock A/B to TCBL - 65 ns
CY/BW/COMP "low"
propagation delay
Clock A/B to TCBH - 85 ns
CY/BW/COMP "high"
propagation delay
LCTR and LLTC pulse TLCW 60 - ns
width
Clock A/B to CYT, BWT TTFH - 100 ns
and COMPT "high"
propagation delay
Clock A/B to CYT, BWT TTFL - 100 ns
and COMPT "low"
progagation delay
WR pulse width TWR 60 - ns
RD to data out delay TR - 110 ns
(CL=20pF)
CS, RD Terminate to TRT - 30 ns
Data-Bus Tri-State
Data-Bus set-up TDS 30 - ns
time for WR
Data-Bus hold time for WR TDH 30 - ns

CS set-up time for RD TSRS 0 - ns

CS hold time for RD TSRH 0 - ns
Back to Back RD delay TRR 60 - ns
RD to WR delay - 60 - ns
C/D set-up time for RD TCRS 0
C/D hold time for RD TCRH 30
C/D set-up time for WR TCWS 30 - ns
C/D hold time for WR TCWH 30 - ns
CS set-up time for WR TSWS 60 - ns
CS hold time for WR TSWH 0 - ns
Back to Back WR delay Tww 60 - ns
WR to RD delay - 60 - ns

Quadrature Mode:
Clock A/B Validation delay TCQV - 160 ns
(See NOTE 1)
A and B phase delay TPH 208 - ns
Clock A/B frequency fCQ - 1.2 MHz
CY, BW, COMP pulse width TCBW 85 200 ns

NOTE 1: In quadrature mode A/B inputs are filtered and required to be stable
for at least TCQV length to be valid.

7166-011705-6
 TLCW
LTCR

TLC
TCL
UP CLK (A)
TCH TUDD
TCH
DN CLK (B)
TCL

Q0
(Internal)

Q1
(Internal)
Q2-Q23
(Internal)
CNTR=FFFFFD CNTR=FFFFFE CNTR=FFFFFF CNTR=000000 CNTR=0000001 CNTR=000000 CNTR=FFFFFF CNTR=FFFFFE CNTR=FFFFFD
(PR=CNTR) (PR=CNTR)

COMP NOTE 2

CY

BW

FIGURE 2 . LOAD COUNTER, UP CLOCK, DOWN CLOCK, COMPARE OUT, CARRY, BORROW

NOTE 1: The counter in this example is assumed to be operating in the binary mode.
NOTE 2: No COMP output is generated here, although PR = CNTR. COMP output is disabled with a counter load command and
enabled with the rising edge of the next clock, thus eliminating invalid COMP outputs whenever the CNTR is loaded from the PR.
NOTE 3: When UP Clock is active, the DN Clock should be held "HIGH" and vice versa.

UP CLK
OR DN CLK

TCBH
TCBL
CY

TTFH TTFL

CYT

TCBL
TCBH
BW

TTFL
TTFH

BWT
TCBL
TCBH
COMP

TTFH TTFL

COMPT

SIGN
(INTERNAL)

FIGURE 3. CLOCK TO CY/BW OUTPUT PROPAGATION DELAYS

7166-110103-7
 TSRS
TSRH
CS

C/D

TCRS TCRH
RD

TRR

TRD TRT
DATA BUS
VALID OUTPUT

CS TSWS TSWH

C/D
TCWS

TCWH

WR TWR
TWW

TDS TDH
VALID DATA
DATA BUS

FIGURE 4. READ/WRITE CYCLES

LCTR

DN CLK

Q0
(INTERNAL)

Q1
(INTERNAL)

Q2-Q23
(INTERNAL)

CNTR=3 =2 =1 =0 =3 =2 =1 =0 =3

CNTR LD
(INTERNAL)

BW

NOTE: EXAMPLE OF DIVIDE BY 4 IN DOWN COUNT MODE

FIGURE 5. DIVIDE BY N MODE

CNTR LOAD
(LCTR or MCR BASED)

UP CLK OR
DN CLK

CY or BW

CNTR DISABLED
CNTR DISABLED CNTR ENABLED

FIGURE 6 . CYCLE ONCE MODE

7166-110103-8
 FORWARD REVERSE

A
T PH T PH

UPCLK (x1) T CQV

(Internal)

DNCLK (x1)
(Internal)

UPCLK (x2)
(Internal)

DNCLK (x2)
(Internal)
T CQV
UPCLK (x4)
(Internal)

DNCLK (x4)
(Internal)

UP/DN (OSR Bit 4)

T CBW
CY

T CBW
BW

FIGURE 7.
QUADRATURE MODE INTERNAL CLOCKS

7166-110503-9
 I/O
(DATA-BUS) 8-15 D0 - D7
BUFFER
D0 -D4
OSR

D0, D6,D7
QR
(CHIP SELECT INPUT) CS 2

(READ INPUT) RD 19
D0 - D7
OCCR CONTROL
(WRITE INPUT) WR 1
INPUT LOGIC

INTERNAL DATA BUS

BUFFER
(CONTROL /DATA INPUT) C/D 18
AND
DECODE
(COUNT INPUT) A 6 D0 - D7 ICR
LOGIC

(COUNT INPUT) B 7 16 CY (CARRY OUT)

STATUS
LOGIC
(AB GATE/LOAD LATCH) ABGT/RCTR 4 17 BW (BORROW OUT)
D0 - D7 MCR
(LOAD CTR/LOAD LATCH) LCTR/LLTC 3

COMPARATOR

N1=N2
N1 N2

PR/OL
ADDRESS
PR0
B0 - B23
B0 - B7
(+5V) VDD 5 OL0
PR1
CNTR
(GND) VSS D0 -D7 B8 - B15
20
Q0 -Q23 OL1
PR2
B16 - B23
OL2

PR/OL ADDRESS
D0 - D7
FIGURE 8.
LS7166 BLOCK DIAGRAM UP CLOCK

DN CLOCK

7166-110103-10
 FIGURE 9. 80C31/8051 TO LS7166 INTERFACE IN EXTERNAL ADDRESS MODE

8051
80C31 74HC573
19
P0.0 AD0 2
D1 Q1
P0.1 AD1 3
4 D2
P0.2 AD2
5 D3
P0.3 AD3
6 D4
P0.4 AD4
D5
P0.5 AD5 7
D6 7166
P0.6 AD6 8
AD7 D7
P0.7 9 D8 18
ALE 11 C/D
C
1 0C 12 2 CS/
Q8

AD0 8 D0
AD1 9 D1
AD2 10 D2
AD3 11 D3
AD4 12 D4
AD5 13 D5
AD6 14 D6
AD7 15 D7

WR/ 1 WR/
RD/ 19 RD/

NOTE: Port_0 is open drain output. Add pull-up resistors to all Port_0 i/0 lines.

7166-110503-11
 VCC

FIGURE 10. 8751 INTERFACE TO LS7166 IN I/O MODE

UR
31 39 5
VCC ER/VP P0.0
38 6 R V DD 16
P0.1 CY
P0.2 37
19 36 7 8
X1 P0.3
35 BW 17
P0.4
18 P0.5 34 3 LCTR/LLTC
X2
P0.6 33
32 4 RBGT/RCTR
9 RESET P0.7

P2.0 21 /7166C/D P1.0 8 D0

12 22 /7166CS 9 LS7166
INT0 P2.1 P1.1 D1
13 8051 P2.2 23 P1.2 10 D2
INT1
15 T0 P2.3 24 P1.3 11 D3
14 P2.4 25 P1.4 12 D4 WR 1 /7166WR
T1
P2.5 26 P1.5 13 D5 RD 19 /7166RD
P1.0 1 P1.0 P2.6 27 P1.6 14 D6 C/D 18 /7166C/D
P1.1 2 P1.1 P2.7 28 P1.7 15 D7 CS 2 /7166CS
P1.2 3 P1.2 Vss
P1.3 4 P1.3 17 /7166RD 20
RD
P1.4 5 P1.4 16 /7166WR
WR
P1.5 6 P1.5 29
PSEN
P1.6 7 P1.6 30
ALE/P
P1.7 8 P1.7 11
TXO
RXO 10

7166-092304-12
 +5V
FIGURE 11. LS7166 TO 68HC11 INTERFACE

U1
PC0 8 16
D0 V DD CY
30 XTAL PA3 5 PC1 9
29 EXTAL PA4 PC2 10 D1
4 17
PA5 PC3 D2 BW
3 11
39 RESET PA6 2 PC4 12 D3
LCTR/LLTC 3
41 IRQ PA7 1 PC5 13 D4
40 XIRD PC6 14 D5 4
PC7 15 D6 RBGT/RCTR
8 PA0 D7 LS7166
PB0 16 18 6
7 PA1 A0 A COUNT IN
PB1 15 C/D
6 PA2 CS/ 2
PB2 14 CS
7
17 PE0 PB3 13 B COUNT IN
18 PE1 PB4 12 WR/ 1
19 PE2 PB5 11 WR
RD/ 19
20 PE3 PB6 10 RD GND
PB7 9 U3
22 YRH 20
21 YRL
PC0 31 PC0 PC0 3 D0 Q0 2
PC1 32 PC1 PC1 4 D1 Q1 5
PC2 33 PC2 PC2 7 D2 Q2 6
PC3 34 PC3 PC3 8 D3 Q3 9
PC4 35 PC4 PC4 13 D4 Q4 12 ADDRESS
PC5 36 PC5 PC5 14 D5 Q5 15 DECODE
PC6 37 PC6 PC6 17 D6 Q6 16
PC7 38 PC7 PC7 18 D7 Q7 19
1 OC
PD0 42
11 G
PD1 43
PD2 44 74HC373 +5V
PD3 45
PD4 46
PD5 47
4
2
MODA 25 PR 5
D
MODB 24 Q
CLK
E 27 6
26 Q
AS CL
28
RW 1
U5 A U6 A 74HC74
68HC11A1 1 2 1
3
74HC04 2
74HC08

U6 B U5 B
4
6 3 4
5
74HC08 74HC04

7166-110103-13
 FIGURE 12. LS7166 INTERFACE EXAMPLE

ISA BUS

D7
D6
D5 LS7166
D4
D3
D2
D1 D0 8 D0
D0 D1 9 D1
D2 10 D2
D3 11 D3
D4 12 D4 1 IOW/
WR
D5 13 D5 RD 19 IOR/
D6 14 D6 18 A0
AEN C/D
D7 15 D7 2
CS

A8
A7
A6
A5
ADDRESS
A4
DECODER
A3
A2
A1

A0
IOR/
IOW/

7166-110503-14
 FIGURE 13. 68000 INTERFACE TO LS7166

DATA BUS
D0 - D7
ADDRESS
D Q A0

LS373 C/D

CK DECODE
CS

R/W RD
+V
LDS/UDS 7166
S
68000 D
68008 S74
68010 CK WR
Q
R +V

AS
S D Q S D
S74 S74
Q CK CK
DTACK R R
CLK
CLOCK

7166-062306-15