Proc. IEEE 1sOO Int. Conference on Microelectronic Test Stmcturea, Vol.9, March 1990. 109.

On-chip Quasi-static Floating-gate Capacitance

Measurement Method

C. Kortekaas
Device and Process Characterization Group
PHILIPS Research Laboratories
P O Box 80.000, 5600 JA Eindhoven,
The Netherlands

Vf gnd
Abstract

A n accurate interconnect capacitance parameter

measurement technique is described. The tech-
nique is based on measurement of a capacitively
divided D C voltage b y means of a source follower
stage integrated in the teststructure. Determina-
tion of dielectric thickness as well as intercon-
nect capacitance parameters using this technique
in combination with special test patterns, is de- sld Vt
scribed. The method shows good agreement with
%dimensional computer simulations. The t u h - Figure 1: Equivalent circuit of the Boating-gate structure
nique has been proven to be practical and reliable
and is suited for use with manual and automatic 2 Principles of the method
parametric test equipment.
The equivalent circuit of the floating-gate teststructure is
1 Introduction shown in Fig. 1. The structure is composed of two capacitors
and a MOSFET. The elements share a common node, being
the floating gate of the MOSFET. For nwell CMOS processes
As lateral feature sizes are scaled down and device density a p-channel device is used to implement a source follower
is increased on integrated circuits, while vertical dimensions stage. The drain of the sense transistor and the free node of
remain more or less constant, edge effects are becoming more the reference capacitor C, are grounded. The gate potential
and more important. In order to deal with the non-linear is then controlled by the driving voltage V, on the free node
effects of device dimensions, accurate measurement and sim- of the unknown capacitor Cm.
ulation techniques have to be used to evaluate the device
A constant current I d 8 is forced through the sense tran-
characteristics. Most of the results reported so far have been
sistor, causing a fixed gate-source potential which depends
obtained by computer simulation [1,2,3]. However this is
on the applied current level. A typical capacitance measure-
not very practical in a factory environment, where MOS-IC
ment consists in setting a fixed voltage on the input terminal
process monitoring is taking place. Even in research and
of the structure and measuring the resulting output voltage
development, especially in process characterisation, evalu-
V, on the source node of the transistor. Because of the source
ation of interconnect capacitances is very time consuming
follower operation of the sense transistor, changes in the gate
because of the many possible layer configurations and the
potential will result in equal changes in the source potential.
complicated test equipment. Conversely, a simple and ac-
curate method for the evaluation of layer thicknesses and
-
Therefore the slope S in a V f V, plot is determined by C,
and C, and we can write
associated capacitance parameters by means of automated
capacitance measurements has been shown to be very effec-
tive [4,5]. Therefore a new measurement technique of small v, = s .v,+ VO(1)
capacitances between internal wiring in VLSI stuctures is
introduced. The relatively small area of the quasi DC mea-
surement structure makes it suitable for use with high vol-
ume parametric process control test systems [SI.

90CH2797-9
 110.

3 Isolation thickness monitor

(4)

where V o ( l )is the source potential at a 0 Volt bias on the Dielectric thickness monitoring can be performed using a
driving node. This constant is dependent on the characteris- well controlled reference capacitor, i.e. a gate-oxide device.
tics of the sense transistor and on the forced current level as Fig. 3 shows the layout of such a thickness monitor. This
shown in Fig.2. In this plot the forced current ranges from design is used as a monitor of the thickness of the isolation
10 nA to 10 pA for a 10 x 10pmZp-channel MOSFET. between the first and the second polysilicon layers.
In the teststructure the backgate of the transistor is con- The test structure is included in a scribeline Process Con-
nected to the source in order to prevent threshold shifts be- trol Monitor and is fabricated in a 1.6 pm switched capacitor
cause of backbias effects when operating in a source follower CMOS process. In this example both capacitors have equal
mode. Threshold shifts induced by the drain voltage are capacitance under nominal process conditions. Edge effects
minimised by using relatively wide and long sense devices.
In order to guarantee that the transistor is operating in the
saturation region, limits must be set to the forced voltage on
the free terminal of the C, capacitor. From the p-channel
+
saturation condition -Vd, > -V#, V, and the practical re-
striction of using positive input voltages we can derive that

vs
Figure 3: An example of a isolation thickness monitor
[Vl

10.00 600.0
E-03

1.000 60.00
/div /div

Figure 2: Typical floating-gate output voltage characteris-

tics

the device always operates in either the saturation region or,

.0000
.0000
.0000
IO. 00
VF 1.00Wdiv ( V)
depending on the current level, in the subthreshold region.
Accurate measurements are only possible when the charge
Figure 4: Boating-gate outputvoltage characteristic for a
on the floating-gate node is, within pratical limits, conserved
gate-oxide reference capacitor
during the measurements. The sense transistor will cause
deviations from this ideal situation because of the chang-
ing gate- and source potentials. But forcing a constant cur- are negligable in this design because of the relative large area
rent through a transistor, which is connected as described, and the thin dielectrics used. The output characteristic of
will result in a constant V,, and in a changing Vd8. There- this teststructure is shown in Fig. 4, where source voltage
fore the only parasitic effect is dominated by the associated V, and S are plotted as function of the input voltage V f .
gate-drain capacitance. In the saturation region this (over- In this plot the voltage dependence of the gate-oxide ref-
1ap)capacitance value is very small (< 1%)compared to C, erence capacitor is reflected in the slope S of the curve. At
and C,, but it sets a limit to the applicability of the method. sufficiently high drive level voltages the reference capacitor
As can be seen in Fig. 2, the slope S is not only independant will be in the inversion mode with a practically constant
of the applied current level but also, in case of voltage inde- capacitance value, which results in a constant slope of the
pendent capacitors, practically independant of the applied curve. In this region the ratio of both capacitors can be de-
voltage. termined. Data obtained using this structure are listed in
 111.

table 1. 4 Capacitance parameters

I Layers 1 Ratio I inline I measured 1 For interconnect capacitance parameter extraction both ca-
I I I I I
1 1
nm nm pacitors are of the same type, i.e. metal-to-metal, metal-to-
poly or other combinations of conductors, but with different
gate-oxide 26.8 area-to-periphery ratio’s. With the model from [3], the ca-
I Poly2 isolation ~ 1.02 I 1 52.2 52.5 I pacitance of an arbitrary interconnect capacitance can be
written as

of a Poly2 to Polyl isolation.

where C B ,C E B and C E C are the specific capacitances
The measured layer thickness is derived from inline gate- per unit area and unit length respectively, Ab is the area
oxide data in column 2. Comparable results can be obtained of the capacitor and Lb, Ll are the lengths of the edges to
from the nominal gate-oxide value and the observed capaci- ground plate and adjacent tracks. To determine the C E B
tor ratio which is corrected with the ratio of measured and parameter it is advantageous to use a relatively large square
nominal MOS transistor gain constants according to plate capacitor as reference device where the total edge con-
tributions are negligable compared to the paral!el plate com-
(5) ponent. A comb structure with a relatively large periphery
length can then be used as unknown C , (Fig. 6).
where: Tisol Poly2 to Polyl isolation thickness In the determination of the C E B parameter, the effective
To, nominal gate-oxide thickness (process target) trackwidth of the fingers in the comb is required, therefore
A , area of unkown capacitor C , a separate measurement must be performed to obtain the
A, area of reference capacitor C, actual linewidth of the C, capacitor.
R observed capacitor ratio (%)
Pm measured transistor gain constant ( p . Co2) One of the major problems in the determination of the
Pn nominal gain constant. track-to-track capacitance is the separation of the various
contributions which play a role in practical test structures.
In Fig. 5 wafermaps of Poly2-Poly1 thickness data result-
Parasitic capacitances of the test equipment or - structure
ins from direct measurements and from &corrected floating-
itself complicates the measurement of small lateral capac-
gate data are shown.

*its :
Max - nm
53.0
nin - 49.0
b)

Figure 5: Wafermajm of PolyZPolyl isolation thickness. a) direct measurement, b) floating-gate data.

 112.

os3' p
[I

Figure 6: Used layout in the fringe capacitance module Figure 7: Used layout of the track-to-track capacitance mod-
ule

itances. These problems can be overcome when interdigi- debigned for large volume testing in R&D and production
tated comb structures are used. With two identical comb- environments [6].
like structures two capacitors can be made with different The teststructures have a 10*lOpmzp-channel MOSFET
characteristics. The capacitance of both combs connected as sense transistor which is biased with 10pA source current.
together is determined by track-to-groundplate ( C B ,C E B ) The ratio is determined from measurements done at biases
contributions only, while connecting one of the combs to of 2.0 and 3.0 Volt .
the groundplate will result in a capacitance which not only In table 2 and 3 the results from the measurements are
includes a track-to-track component but also has a track- compared with the results obtained from 2D capacitance
to-groundplate capacitance which is half of that of the first simulations using actual thickness data in cme of M2 n+ -
structure (Fig. 7). Both capacitors used in the floating gate and M2 - Poly capacitors and nominal process data for the
structure will make the determination of the lateral capaci- M2 - M1 cases.
tance parameter CEC more accurate because of the reduc- For both C E B and C E C determination the floating-gate
tion of the number of unknowns. In this case only for the method compares well with the simulated results. The rel-
determination of the actual track-to-track spacing knowledge
of the effective trackwidth is required.
Both floating-gate teststructures are included in a pro-
cess evaluation die that is fabricated in a Philips 1.Opm Layers spacing Ratio C E B [aF/pm]
CMOS double metal process. Several layer combinations, [pm] meas. 1 sim. meas. I sim.'
all with metal2 tracks, are available. The same testdie also
contains modules for the determination of the trackwidths. M2 - n+ 1.5 1.05 1.03 17.2 f 0.4 18.0
The fingers in the used capacitors all have the minimum
width of the process (1.5pm). In most cases the minimum M2 - Poly 1.5 1.04 1.03 17.6 * 0.4 18.0
pitch (3.Opm) is used in the interdigitated structures, in one
case the spacing of the fingers is made larger, with a pitch -
M2 M1 1.5 1.11 1.14 32.4 f 1.5 30.0
of 5.5pm, in order to verify the spacing dependency of the 4.0 1.43 1.50 58.1 f 1.5 53.0
edge parameters.
The ratio of the capacitances is designed to range from
-
1.0 to 1.5 with capacitors of 0.7 1.5 pF. Typical area of the Table 2: Capacitance ratio's and fringe capacitance
capacitor structures is 250*150 pm'. The measurements are parameters measured and calculated for several
currently implemented on a Keithley S350 parametric tester layer combinations. M2 linewidth = 1.5pm.
 113.

Acknowledgement

The author would like to express his appreciation to H.P.

-
M2 M1 Tuinhout for the valuable discussions, to W. Huinink and
P. Peys for maskdesign, to S. Swaving, J.J.M. Joosten and
M.J.M. van Someren for software- and to T. Smit for mea-
surement support.
Table 3: Capacitance ratio’s and track-to-track capacitance
parameters measured and calculated for several
spacings. M2 linewidth = 1.5pm.
References

ative deviations in the fringe capacitance parameters C E B 1 - J.H. Quint, F.M. Klaassen and R. Petterson,
seem to be larger than in the track-to-track parameters. This ”2D and 3D capacitance effects in MOS VLSI“,
is probably caused by the accuracy of the effective track- Proc. ESSDERC 87 Bologna Italy, pp. 417-420.
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accuracy. Furthermore, the resulis of simulations of fringe ”Capacitance Coefficients for VLSI Multilevel
effects in stacked isolation layers are dependent on the exact Metallization Lines”, IEEE J. Electron Devices,
layer formation. In this example an approximation of the pp. 644-649, Mar. 1987.
actual layer composition is used [3]. 3 - C. Kortekaas,
” Interconnect capacitance characterisation for
MOS-IC process and circuit design”,
5 Conclusions Proc. ICMTS 88 Long Beach California, pp. 39-44.
4 - H. Iway and S. Kohyama,
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included.
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use of complicated test equipment. Interconnect capacitance
parameter extraction requires a relatively small area and
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can therefore be incorporated in drop-in PCM’s.