64Mb Synchronous DRAM Specification: A3V64S40GTP
64Mb Synchronous DRAM Specification: A3V64S40GTP
64Mb Synchronous DRAM Specification: A3V64S40GTP
A3V64S40GTP
General Description
A3V64S40GTP is organized as 4-bank x 1,048,576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. A3V64S40GTP achieve very high speed data rates up to 166MHz, and are
suitable for main memories or graphic memories in computer systems.
Features
- Single 3.3V ±0.3V power supply
- Maximum clock frequency:
-60:166MHz<3-3-3>/-70:143MHz<3-3-3>/-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0, BA1 (Bank Address)
- CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- LDQM and UDQM (A3V64S40GTP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Support concurrent auto-precharge
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
Pb-free package is available
Ordering Information
54Pin TSOPII (400mil x 875mil)
Part No. Max. Frequency Supply Voltage
A3V64S40GTP-60 166MHz (CL=3) 3.3V
A3V64S40GTP-70 143MHz (CL=3) 3.3V
A3V64S40GTP-75 133MHz (CL=3) 3.3V
Zentel Electronics reserves the right to change products or specification without notice.
PIN CONFIGURATION
(TOP VIEW)
Vdd 1 54 Vss
DQ0 2 53 DQ15
VddQ 3 52 VssQ
DQ1 4 51 DQ14
DQ2 5 50 DQ13
VssQ 6 49 VddQ
DQ3 7 48 DQ12
DQ4 8 47 DQ11
VddQ 9 46 VssQ
DQ5 10 45 DQ10
DQ6 11 44 DQ9
VssQ 12 43 VddQ
DQ7 13 42 DQ8
Vdd 14 41 Vss
LDQM 15 40 NC
/WE 16 39 UDQM
/CAS 17 38 CLK
/RAS 18 37 CKE
/CS 19 36 NC
BA0 20 35 A11
BA1 21 34 A9
A10(AP) 22 33 A8
A0 23 32 A7
A1 24 31 A6
A2 25 30 A5
A3 26 29 A4
Vdd 27 28 Vss
BLOCK DIAGRAM
DQ0-15
A0-11 U,LDQM
Interface V: LVTTL
Zentel Memory
Pin Descriptions
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
CLK Input edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank), or CLOCK SUSPEND operation (burst /
CKE Input access in progress). CKE is synchronous except after the device enters self refresh mode, where
CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK,
are disabled during self refresh mode, providing low standby power. CKE may be tied HIGH.
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external
/CS Input bank selection on systems with multiple banks. /CS is considered part of the command code.
/CAS, Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.
/RAS, Input
/WE
Input / Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output disable signal for read accesses. Input data is masked during a WRITE cycle. The
LDQM, output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM
Input
UDQM, corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or
BA0, BA1 Input PRECHARGE command is being applied.
A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is
specified by A0-11. The Column Address is specified by A0-7. A10 is also used to indicate
A0–A11 Input precharge option. When A10 is high at a read / write command, an auto precharge is performed.
When A10 is high at a precharge command, all banks are precharged.
Internally Not Connected: These could be left unconnected, but it is recommended they be
NC – connected or VSS.
Data Output Power: Provide isolated power to output buffers for improved noise immunity.
VddQ Supply
Data Output Ground: Provide isolated ground to output buffers for improved noise immunity.
VssQ Supply
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Note:
1. VIH(max) = 4.6V AC for pulse width ≤ 10ns acceptable.
2. VIL(min) = -1.5V AC for pulse width ≤ 10ns acceptable.
3. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled , 0V ≤ VOUT ≤ VDD.
CAPACITANCE ( Vdd = VddQ = 3.3V, TA = 25°C, f = 1MHz, pin under test biased at 1.4V.)
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted, TA = 0 to 70°C)
Version
Parameter Symbol Test Condition Unit Note
-60 -70 -75
Burst length = 2
Operating Current
ICC1 tRC = tRC(min) 80 75 70 mA 1
(One Bank Active)
IO = 0 mA
IO = 0 mA
Operating Current Page burst
ICC4 100 90 85 mA 1
(Burst Mode) 4Banks Activated
tCCD = 2CLKs
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter Symbol Unit Note
-60 -70 -75
tRAS(min) 42 45 45 ns 1
Row active time
tRAS(max) 100 100 100 us
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
TRUTH TABLE
Current state /CS /RAS /CAS /WE /Address Command Action Notes
Precharging H X X X X DESL NOP, idle after tRP
L H H H X NOP NOP, idle after tRP
L H H L X BST ILLEGAL 2
L H L H BA,CA,A10 RD/RDA ILLEGAL 2
L H L L BA,CA,A10 WR/WRA ILLEGAL 2
L L H H BA,RA ACT Bank active / ILLEGAL 2
L L H L BA,A10 PRE/PALL Nop, idle after tRP 4
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Row activating H X X X X DESL NOP, row active after tRCD
L H H H X NOP NOP, row active after tRCD
L H H L X BST ILLEGAL 2
L H L H BA,CA,A10 RD/RDA ILLEGAL 2
L H L L BA,CA,A10 WR/WRA ILLEGAL 2
L L H H BA,RA ACT ILLEGAL 2
L L H L BA,A10 PRE/PALL ILLEGAL 2
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Write H X X X X DESL NOP
recovering L H H H X NOP NOP
L H H L X BST ILLEGAL 2
L H L H BA,CA,A10 RD/RDA Begin read, determine AP
L H L L BA,CA,A10 WR/WRA Begin write, determine AP
L L H H BA,RA ACT ILLEGAL 2
L L H L BA,A10 PRE/PALL ILLEGAL 2
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Refreshing H X X X X DESL NOP, idle after tARFC
L H H H X NOP NOP, idle after tARFC
L H H L X BST ILLEGAL
L H L H BA,CA,A10 RD/RDA ILLEGAL
L H L L BA,CA,A10 WR/WRA ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PALL ILLEGAL
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Mode register H X X X X DESL NOP, idle after tMRD
accessing L H H H X NOP NOP, idle after tMRD
L H H L X BST ILLEGAL
L H L H BA,CA,A10 RD/RDA ILLEGAL
L H L L BA,CA,A10 WR/WRA ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PALL ILLEGAL
L L L H X REF ILLEGAL
L L L L OC MRS ILLEGAL
Notes: 1. All entries assumes that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to the bank in specified state; function may be legal in the bank indicated by BA, depending on the state
of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL: Device operation and/or data-integrity are not guaranteed.
MRS Mode
CAS Latency Burst Type Burst Length Write Burst Mode
A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1 A9 Type
0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 Programmed Burst Length
0 0 1 Reserved 1 Interleave 0 0 1 2 2 1 Single Location Access
0 1 0 2 0 1 0 4 4
0 1 1 3 0 1 1 8 8
1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved
1 1 0 Reserved 1 1 0 Reserved Reserved
1 1 1 Reserved 1 1 1 Full Page Reserved
BURST SEQUENCE
STARTING COLUMN ORDER OF ACCESSES WITHIN A BURST
BURST LENGTH
ADDRESS
TYPE=SEQUENTIAL TYPE=INTERLEAVED
A0
2 0 0-1 0-1
1 1-0 1-0
A1 A0
0 0 0-1-2-3 0-1-2-3
4 0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
N=A0 – A7 Cn, Cn+1, Cn+2, Cn+3,
Full Page (y) Not Supported
(location 0 – y) Cn+4..., …Cn-1, Cn…
NOTE:
1. For full-page accesses: y = 256.
2. For a burst length of two, A1–A7 select the block-of-two burst; A0 selects the starting column within the block.
3. For a burst length of four, A2–A7 select the block-of-four burst; A0–A1 select the starting column within the block.
4. For a burst length of eight, A3–A7 select the block-of-eight burst; A0–A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0–A7 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
7. For a burst length of one, A0–A7 select the unique column to be accessed, and mode register bit A3 is ignored.
Power-up sequence
Power-up sequence
1. Apply VDD and VDDQ at the same time. Keep CKE low during power up.
2. Wait for stable power.
3. Start clock and drive CKE high.
Note: Voltage on any input pin must not exceed VDD+0.3V during power up.
Initialization sequence
4. After stable power and stable clock, wait 200us.
5. Issue precharge all command (PALL).
6. After tRP delay, set 2 or more auto refresh commands (REF).
7. Set the mode register set command (MRS) to initialize the mode register.
Note: We recommend that you keep DQM and CKE high during initialization sequence to prevent data contention on the DQ
bus.
CKE
Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank
active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write
command input.
Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency - 1) cycle after
read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the
bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks
specified by the CAS Latency. The CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive
burst-length data has been output.
The CAS latency and burst length must be specified at the mode register.
Write operation
1. Burst write: A burst write operation is enabled by setting OPCODE A9 to 0. A burst write starts in the same clock as a write
command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4 and 8, like burst read operations.
The write start address is specified by the column address and the bank select address at the write command set cycle.
.
2. Single write: A single write operation is enabled by setting OPCODE A9 to 1. In a single write operation, data is only
written to the column address and the bank select address specified by the write command set cycle without regard to the
burst length setting. (The latency of data input is 0 clock).
Auto Precharge
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to
High-Z at the same clock with the burst stop command.
Command Intervals
Read command to Read command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank
as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock.
Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands
cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 clock,
provided that the other bank is in the bank active state. Even when the first command is a burst read that is not yet finished,
the data read by the second command will be valid.
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed;
it is necessary to separate the two write commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock,
provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority.
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed;
it is necessary to separate the two commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle,
provided that the other bank is in the bank active state. However, UDQM and LDQM must be set High so that the output
buffer becomes High-Z before data input.
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed;
it is necessary to separate the two commands with a precharge command and a bank active command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock,
provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be
written until one clock before the read command is executed (as in the case of the same bank and the same address).
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even
when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is
valid. The internal auto-precharge of one bank starts at the clock of the second command.
2. Same bank: The consecutive read command (the same bank) is illegal.
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. In the
case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts at the next
clock of the second command.
2. Same bank: The consecutive write command (the same bank) is illegal.
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to
separate the two commands with a bank active command.
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to
separate the two commands with a bank active command.
tRDL
tRDL
tMRD
RDL
DQM Control
The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM and LDQM is
different during reading and writing.
Reading
When data is read, the output buffer can be controlled by UDQM and LDQM. By setting UDQM and LDQM to Low, the output
buffer becomes Low-Z, enabling data output. By setting UDQM and LDQM to High, the output buffer becomes High-Z, and
the corresponding data is not output. However, internal reading operations continue. The latency of UDQM and LDQM
during reading is 2 clocks.
Writing
Input data can be masked by UDQM and LDQM. By setting DQM to Low, data can be written. In addition, when UDQM and
LDQM are set to High, the corresponding data is not written, and the previous data is held. The latency of UDQM and LDQM
during writing is 0 clock.
Refresh
Auto-refresh
All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the
internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external
address specification is not required. The refresh cycles are required to refresh all the ROW addresses within tREF (max.).
The output buffer becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal
operation after the auto-refresh, an additional precharge operation by the precharge command is not required.
Self-refresh
After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh
operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit
command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF(max.) period
on the condition 1 and 2 below.
1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh
addresses are completed.
2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below* after exiting from
self-refresh mode.
Others
Power-down mode
The SDRAM enters power-down mode when CKE goes Low. For cases of all banks in the IDLE state, it is referred to as
precharge power-down mode. For cases of any bank in the ACTIVE state, it is referred to as active power-down mode. In
power down mode, power consumption is suppressed by deactivating the input buffers excluding CLK and CKE. Power
down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the power down
mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed.
Timing Waveforms
Read Cycle
tCC
tSAC
C
Write Cycle
tCC
tRDL
tARFC tARFC
tARFC tARFC
Initialization Sequence
PACKAGE DRAWING
Important Notice:
Zentel DRAM products are not intended for medical implementation, airplane and transportation
instrument, safety equipments, or any other applications for life support or where Zentel products
failure could result in life loss, personal injury, or environment damage. Zentel customers who
purchase Zentel products for use in such applications do so in their own risk and fully agree Zentel
accepts no liability for any damage from this improper use.