Laboratory Manual: Department of Electronics & Telecommunication Engineering

SANT DNYANESHWAR SHIKSHAN SANSTHA’S
ANNASAHEB DANGE COLLEGE OF ENGINEERING & TECHNOLOGY, ASHTA
DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION

ENGINEERING
LABORATORY MANUAL
COMMUNICATION LABORATORY - II
T. Y. B. Tech
2020-2021
ANNASAHEB DANGE COLLEGE OF ENGINEERING & TECHNOLOGY, ASHTA
DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION ENGINEERING
COMMUNICATION LABORATORY - II
INDEX
SR. TITLE OF THE EXPERIMENT DATE DATE PAGE SIGN
NO. PERFORMED SUBMITTED NO.
1 Introduction
Perform and analyze
2 i. Sampling
ii. PCM technique and interpret modulated
and demodulated waveform.
Perform and analyze
i. Delta
3 ii. Adaptive Modulation technique and
interpret modulated & demodulated
waveform.
Conduct and observe waveforms of
4 i. Amplitude Shift Keying
ii. Frequency Shift Keying.
Observe and analyze
5 i. Binary Phase Shift Keying
ii. QPSK modulated and demodulated
waveform.
Develop a program for digital modulation scheme
6
using MATLAB (ASK, FSK, PSK, QPSK).
7 Revision
8 Perform error correction and detection cyclic
codes.
9 Develop a block diagram for digital modulation
scheme using Multisim/Simulink.
10 Performance comparison of simple dipole
antenna, log periodic antenna, Yagi-Uda antenna.
Determination of velocity of object moving in
11 RADAR range and also time & frequency of
RADAR using moving Pendulum.
12 Measurement of characteristic/Input Impedance
/Attenuation of transmission line.
13 Write a program to find radiation pattern of
Broadside array antenna using MATLAB.
14 Submission
15 Internal oral
This is to certify that Mr. /Ms. ____________________________________________________

Roll No._____________ of _____________ Class has completed satisfactorily _____________
experiments in Communication Laboratory - II during the academic year ________________.
Date:
Department of Electronics & Telecommunication Engineering Communication Laboratory - II
Experiment No 1
INTRODUCTION TO LABORATORY
Prepared By : Mrs. M. M. Raste Page 3

Experiment No 2
SAMPLING & PULSE CODE MODULATION & DEMODULATION (PCM)
Aim: To Conduct and Observe the waveform of

i. Sampling
ii. Pulse code Modulation and Demodulation.
Equipment’s: Sampling kit, PCM Modem kit, Patch Cods, DSO or CRO, CRO probes.
Theory:
By Nyquist theorem, if signal contains no frequency components for F > B. W., it is

completely described by instantaneous sample values uniformly spaced in time with period
Ts < ½ BW. If a signal has been sampled at the Nyquist rate or greater (Fs > 2.BW) & the
sample values are represented as weighted impulses, the signal can be exactly reconstructed from
it’s samples by an ideal LPF of bandwidth B.W.
Pulse code Modulation is a digital transmission of samples of analog signal. In PCM
Generator we have sampler, Analog to digital converter & parallel to serial data converter &
serial transmission. In PCM Receiver there is serial reception of data, this serially Received data
is then converted to parallel from & then fed to digital to analog converter. The output of DAC
is fed to low pass filter & we get transmitted analog signal. PCM performance as an analog
communication system depends primarily on the quantization noise introduced by ADC.
In our kit for PCM transmitter we have used ADC0809, Multiplexer IC74151, Latch
IC74373, Counter IC4040, IC7404, IC7432 & IC7408 for required Logic implementation.
The conversion time of ADC limits maximum sampling rate & therefore Bandwidth of
transmitter. All control signals are derived from basic clock. To derive control signals IC7408,
7432, 4017, are used. After analog to digital conversion signals fed to Multiplexer IC. Control
for IC 74151 is from IC4040. Every time IC4040 counter gives 8 combination & transmits 8 bit
data corresponding to every sample.
In Receiver section we have used shift register IC 74198 in serial in & parallel out form. For
synchronization clock at Receiver must be same to clock at transmitter. After serial reception of
data output of shift register is latched using 74373 & fed to DAC (R-2R Ladder).Output of DAC
is fed to filter.
To observe stable waveform on CRO the sampling frequency must be exactly integer
multiple of signal frequency. In our kit signal frequency is obtain by frequency divider & filter
circuit.
PROCEDURE :
NOTE : Pot provided at top left side corner is for varying de bias at the I/p of A/D. We can
measure DC bias voltage at the test pt. 8 bit dip switch is provided for varying bit resolution of
A/D. If Sw is ‘ON’ that means that bit is going to latch connected after A/D. If it is ‘OFF’ it
means gnd is connected to respective pin of latch. If LSB bit is off (no. 1 of DIP switch) least
count of A/D is now 38mv instead of ‘19mv’ when all bits are connected.
1. Switch on ‘Power on’ switch , red LED should glow.

2. Observe 1MHz clock O/p signal on panel.

3. Connect this 1MHz clock to ADC 0809 clock I/p.

4. Observe point ‘A’ O/p from -:- 2 Network & connect it to point ‘B’ i.e. I/p to -:- 8
Network .
5. Observe O/p of both -:- 8 network & calculate their frequencies.
6. Connect O/p of 2nd -:- 8 network to start conversion I/p of ADC 0809 i.e. ‘SC’ point on
panel.
7. Observe ‘SC’ point & ‘EOC’ point on panel simultaneously on dual trace oscilloscope &
find out conversion period of A/D. Conversion period Time between falling edge of
‘SC’ & rising edge of ‘EOC’.
8. Observe ‘EOC’ point & ‘OE’ point i.e. O/p enable pin of 74373 latch simultaneously on
dual trace scope. Also observe ‘RST’ point &’Clk’ point of IC 4040 along with ‘OE’.
9. Observe ‘PCM OUTPUT’ point & connect it to I/p to receiver. i e. serial I/p to shift
register 74198
10. Observe ‘CLK’ of 74198 along with ‘Clk’ of 4040 dual trace scope.
11. Observe ‘LE’ i. e. latch enable pin of 74373 latch next to shift register, with ‘CLK’ of
74198.
12. Now you can draw timing diagram of the system.
13. Ensure that all 8 bits are connected to latch i.e. that all DIP SWs. are to on position.
14. Adjust biasing dc voltage to 2.5v with the pot.
15. By using pot provided above ‘DAC’ adjust 2.5v at the O/p of DAC.
16. Now vary I/p biasing pot slightly & observe that accordingly DAC voltage varies
linearly, on CRO.
17. Now keep 3 LSB bits SWs to ‘Off ’ position & vary I/p biasing voltage, you will find
DAC voltage varies in steps.
18. By measuring I/p voltage & DAC voltage we can find out quantization noise.
19. Now keep DC bias to 2.5v using nearby pot. & all DIP SWs to on position.
20. Two generators are provided on panel rightmost is fixed frequency Sine wave & the other
is variable frequency. (Sine, square & triangular wave generator) To vary its frequency
pot is provided on panel.
21. First Connect fixed frequency sine wave to I/p of ADC 0809.
22. Observe DAC O/p. Calculate its frequency & peak to peak amplitude. Observe this with
I/p fixed frequency sine wave.
23. Connect DAC O/p to I/p of filter & observe O/p of filter.
24. Repeat step 22-23 variable frequency sine, triangular & square wave a I/p to ADC.
25. First keep frequency of sine wave minimum. Observe DAC O/p along with I/p sine wave.
Now slowly increase freq. of sine wave to verify Nyquist criteria & to observe alaising
effect.

Connection Diagram:
CONNECTION DIAGRAM
PCM MODEM POINTS TO OBSERVE ONLY
RST CLOCK CONTROL

MONO CLOCK LE CCT
IC 4040
O/P
LE I/P
IC 74198
IC 74373
DC
PCM
IC 74373
IC 74151
ADC 0809 DAC
O/P
O/P
I/P
SC
FREQ ADJ LPF
EOC O/P
I/P CLOCK
1MHz POWER ON
GND 1KHz
A FUNCTION
GEN SINE
B
GEN.
CLOCK -:- 2 N/W -:-8 N/W -:- 8 N/W
Conclusion:
PCM WAVEFORMS:
CLK 500 KHz
8 KHz
4017 (Q 0)
4017 (Q 2)
4017 (Q 4)
4017 (Q 6)
TRANS. &RECE
CLK
ADC
START CONV.
EOC
Conversion Period
TRANS.
LATCH OE
RECEIVER
LATCH LE
PCM MODEM

Experiment No 3
DELTA MODULATION & DEMODULATION (DM) & ADAPTIVE DELTA

MODULATION

i. Delta Modulation and Demodulation
ii. Adaptive Delta Modulation and Demodulation
Equipment’s: DM Kit, ADM Kit Patch Cods, DSO or CRO, CRO probes.
Theory:
i. Delta Modulation
Sample values of analog waveform derived from physical Process often exhibit
predictability in the sense that the average change from Sample to sample is small. Hence you
can make a reasonable guess of the next sample value based on previous values. The predicted
values has some error off course, but the range of the error should be much, less than the Peak -
to peak signal Range Predictive coded modulation scheme exploit this property by transmitting
just the prediction errors. An identical prediction circuit at the destination combines the incoming
errors with its own predicted values to reconstruct the waveform.
Delta modulation employee’s prediction to simplify hardware in exchange for increased
signaling rate compared to Pulse code modulation.
At DM transmitter, every sample of message waveform is compared with previous sample.
To have previous sample available, dummy receiver is required at transmitter. If sample at any
instant is larger in magnitude than previous one, then one is transmitted. if sample at any instant
is smaller than previous value ‘O’ is transmitted. Thus DM one bit per sample is transmitted.
In our kit we have provided IC8038 based function generator Sine triangular & Square
wave is provided. A fixed sampling (8 KHz) frequency is provided. By varying I/p signal
frequency different sampling rates & its effect on reconstructed message signal can be observed.
Also variable step-size is provided. For square wave slope-overload prominently occurs, it can
reduce by increasing step-size or increasing sampling rate.
At DM Receiver our aim is to reconstruct transmitted message signal from train of ‘1’ &
‘0’. In our kit Receiver is built with complete hardware. flip-flops ( IC4013 ), Decade counter (
IC4017 ), Binary Adders ( IC 7483 ),Latches ( 74373 ), OR Gate ( IC7432 ), Not Gate ( IC7404
), Digital to analog converter (OP-AMP based R-2R Ladder) are used for this purpose.
At receiver timing is very critical. We have to perform different operation such as addition,
subtraction, latching. Therefore different control signals for sequential operation are derived by
dividing Basic Clock using (IC4017). Before taking new I/p pulse, previous sample value is
latched using (IC74373) & transfer to binary adder & subtractor .
Subtraction is carried out using binary adder (IC7483) using 2’s complement method. If
received signal is ‘One’ then ‘1’ is added to previous value, else it is subtracted form previous
value. The result of addition/ subtraction is again latched & transfer to adder/ subtrator. So it can
used as previous sample for next sample. Result is fed to DAC. O/p of DAC is reconstructed
message signal.

ii. Adaptive Delta Modulation

In case of Delta modulation we transmit ‘1’ when instantaneous value of message
waveform is larger than previous sample & ‘0’ when it is smaller than previous sample. But
the stepsize is fixed. If I/p (i. e. message waveform) is changing rapidly, it is not possible for
DM to track the message waveform. For example for square wave I/p ,O/p of DM receiver is
not square wave. This is called as slope overload. To avoid this problem adaptive delta
modulation technique is used. Adaptive delta modulation (ADM) involves additional
hardware designed to provide variable step size, thereby reducing slope-overload effects
without increasing the granular noise. In DM we observe that slope-overload appears as a
sequence of pulses having the same polarity. This sequence information can be utilized to
adopt the step size in accordance with the signals characteristics.
If instantaneous value of message waveform is larger than previous sampled then ‘1’ is
transmitted and if smaller then ‘0’ is transmitted. But the difference is that if ‘1’ is
transmitted two or more times successively then stepsize is not same. If for first ‘1’ it is 1D
for second ‘1’ it 2D, for 3rd 3D and so on. Similarly if ‘0’ is transmitted two or more times
then stepsize is –D for 1st ‘0’, -2D for second zero and so on.
From figure we observe that slope overload is decreases. Another ADM scheme is called
continuously variable slope delta modulation (CVSDM))) provides a continuous range of
stepsize adjustment instead of a set of discrete value.
The signal to noise ratio of is typically 8 to 14 dB better than ordinary DM. In our ADM
kit we have provided sine & square wave as a message waveform. The logic which explained
earlier is build using complete hardware . Up-Down counters, Latches, Binary adders, Digital
to analog converters, Comparators are used. Complete circuit diagram is as shown in figure.
Timing sequence is similar to that of DM kit. Only difference is that one CLK is fed
during each sampling to UP or DOWN counter depending on whether ‘1’ is transmitted
or ‘0’ is transmitted. Also up counter is reset if ‘0’ is transmit & down counter is reset if ‘1’
is transmit.
Procedure:
i. Delta Modulation:
1. Switch on ‘Power on’ switch. Red led should glow.
2. Two signal generators are provided on panel. One is fixed frequency sine wave & the
other is variable frequency square, sine, triangular wave generator. First Connect O/p of
fixed frequency generator to non-inverting terminal of comparator.
3. O/p of 4013 i.e. point ‘A’ on panel should be connected to point ‘B’ on panel.
4. DAC O/p should be connected to inverting terminal of comparator & to input of LPF.
5. Observe O/p of ‘CLOCK’ Measure its frequency.
6. Observe clock O/p terminal connected to 4013 IC. It is nothing but the sampling
frequency. Measure it.
7. Observe DM O/p for given fixed frequency sine wave. Measure frequency of this sine
wave.
8. Observe fixed frequency sine wave & DAC O/p i. e. reconstructed signal simultaneously
on CRO & find out DM algorithm.
9. Observe point ‘A’ of 4013 & DAC O/p simultaneously on dual trace CRO.
10. Observe ‘OE’s of 74373’s in subtractor branch i. e. in which 7404 is connected & adder
branch simultaneously on dual trace CRO. They are complementally to each other.

11. Observe effect of pot on step size. This pot is situated on top of DAC.
a. To find out bit resolution in DM algorithm procedure is as follows
b. Keep non-inverting terminal of comparator open.
c. Connect inverting terminal of comparator to ground other & Connections as it is.
c.. Observe DAC O/p. stair case waveform is seen on CRO. Measure no. of step in that
waveform from this now calculates Bit resolution.
d. For this configuration rising stair case waveform is observed Reason for this is that
non-inverting terminal is internally dc biased for 2.5V, & we kept inverting terminal grounded.
So comparator O/p is permanently high ,so increment command to DM receiver ,so it goes on
Incrementing & due to overflow again starts from zero level. i.e. if inverting terminal is
connected to VCC i. e. 5V, falling stair-case waveform is observed.
12. To draw timing diagram of system, make connection as said earlier & instead of
connecting any signal to non-inverting terminal keep it open, internally 2.5V biasing is
given. For this DAC O/p wave form is sq. wave. For each sample either increment or
decrement by one Step size. Now observe sampling clock of IC 4013 with ‘LE’ signal of
previous data latch 74373 simultaneously on dual trace. Then observe any ‘OE’ signal
with ‘LE’ signal, simultaneously. Now draw timing diagram.
13. Now by connecting variable frequency sine wave & sq. wave to non-inverting terminal
observe DAC O/p. also see the effect of step size & sampling frequency when frequency
is varied.
14. Low pass filter is provided on panel. By giving variable sine wave to its I/p observe its
O/p & from that find out its cut off frequency. Also for fixed frequency sine wave
connect DAC O/p to I/p of LPF & observe its O/p.
iii.Adaptive Delta Modulation

1. Switch on ‘Power on’ switch. Red LED should glow.
2. Observe O/p from clock & measure its frequency.
3. Two signal generators are provided on panel. One is fixed frequency sine wave generator.
Observe its O/p on CRO. Measure its frequency & peak to peak amplitude. The other is
variable frequency sine & square wave generator. Pot is given to very its frequency.
measure its frequency span.
4. Connect non inverting terminal of comparator to fixed sine wave.
5. Connect inverting terminal of comparator to DAC O/p.
6. O/p’s from 4013 IC are shown as point ‘A’ & ‘C’ on panel. They are used for further
control. Connect point ‘A’ to point ‘B’ & connect point ’C’ to point ‘D’ on panel.
7. Now observe DAC O/p along with I/p sine wave & by nearing hearby pot see variable
step size. Also observe that slope overload is less in ADM.
8. Observe ADM O/p with sine wave & then with digitally reconstructed DAC O/p. what is
your conclusion ?
9. Also for particular step size if we observe ADM O/p & DAC O/p simultaneously on dual
trace CRO then we find 1 sample delay in decision making but if point ‘A’ & DAC O/p is
observed simultaneously, no such delay is observed why ?
10. Observe sampling clock of IC 4013. Measure its frequency.
11. Connect DAC O/p to I/p of low pass filter & observe its O/p & measure its frequency
observe effects of step size variation on the filter O/p.

12. Observe point ‘A’ & one by one, two ‘RST’ pins of 74193 on dual trace. What is your
observation.?
13. Measure ‘Clock’ frequency given to both 74193 ICs.
14. Observe point ‘A’ & two ‘OE’s on dual trace scope one by one.
15. Observe ‘LE’ point of previous latch 74373 situated at the bottom. Measure its
frequency.
16. To draw timing diagram, keep non inverting terminal of comparator open, then in this
case DC is given due to internal DC biasing. Observe DAC O/p. adjust pot so that only
one step hunting is observed. Also see that here if step size is varied hunting is more than
in DM.
17. Now when only one step size hunting is there, for every sample we get increment or
decrement.
18. Then observe sampling clock & ‘LE’ of latch simultaneously. Then observe ‘RST’ &
sampling clock.
19. Observe ‘Clk’ to 74193 & ‘LE’ of previous latch.
20. Observe ‘Clk’ to 74193 & OE’s of two latches i. e. 74373. From these observations draw
timing diagram.
21. Now connect non inverting terminal of coparator to variable frequency sine wave & sq.
wave.
22. Observe slope overload effect. For low frequency observe hunting.
23. Low pass filter is provided on panel. We have variable frequency signal generator.
Measure LPF’s cut-off frequency.
Connection Diagram:
I. DELTA MODULATION
DM O/P S. CLOCK
+12
A CONNECTION DIAGRAM TO STUDY DM
+
POINTS FOR OBSERVATION ONLY
IC 4013 I/P
_ O/P
-12 LPF SINE
OE GEN.
+5
B IC 7404 IC 7483 IC 74373
CONTROL
OE
+5
DAC
IC 7483
IC 74373
O/P
LE
CLOCK SINE
O/P
CLOCK
IC 74373 FUNCTION
GEN.
POWER ON
FREQ.
GND
ADJ.

II. ADAPTIVE DELTA MODULATION
ADM O/P S. CLOCK

+12
CONNECTION DIAGRAM TO STUDY ADM
+ A
POINTS FOR OBSERVATION ONLY
IC 4013 I/P
- -12 LPF
B D SINE
C
OE O/P GEN.
CONTROL
IC74193 IC 7404 IC 7483 IC 74373
RST OE
DAC
IC74193 IC 7483 IC 74373
RST
O/P
LE
SINE
CLOCK
CLOCK
O/P IC 74373 FUNCTION
GEN.
POWER ON
GND FREQ.
ADJ.
Conclusion:
DELTA MODULATION WAVEFORMS
TRIANGUULAR
WAVE I/P
SAMPLING PERIOD
TS
DM O/P
SQUARE
WAVE I/P
SQ. WAVE
I/P
DM O/P
WAVEFORMS FOR DM

ADAPTIVE DELTA MODULATION WAVEFORMS
ADM
CLK
62.5KHz
. 8 G CLK TO 4 013
.
Q0
N LE [FINAL LATCH]
Q2
H CLK TO 74193
Q4
J I.e. LE
ADDER, SUBTRACTOR
Q6 LATCH.
B ‘4 013 ‘ PIN (1)

TO 74193 RESET (SUBTRACTOR)
P
TO 74193 RESET (ADDER)
‘4 013 ‘ PIN (13) I. e. C

TO OE SUBTRACTOR BRANCH.
OE ADDER BRANCH.
NON - INVERTING INPUT OF COMPARATOR IS OPEN FOR THIS DIAGRAM.
TRIONGUULAR
WAVE I/P
TS
DAC O/P
ADM O/P
SQ. WAVE
I/P
DAC O/P
ADM O/P

Experiment No 4
AMPLITUDE SHIFT KEYING (ASK ) & FREQUENCY SHIFT KEYING (FSK)

I. Amplitude Shift Keying Modulation and Demodulation.
II. Frequency Shift Keying Modulation and Demodulation.
Equipments: ASK kit, FSK Kit, Patch Cods, DSO or CRO, CRO probes.
Theory :
i. AMPLITUDE SHIFT KEYING:
In binary ASK System the transmitted signal is a sinusoid of two different amplitudes.
When data is logic high ,amplitude of sinusoid is twice as compared to amplitude when data is
at logic low. In our kit we have derived a sinusoid from a crystal clock , frequency divider & 2 nd
order butterworth filter. Also two different bit patterns are derived from a basic clock. For
transmitter section we have used IC4052 as a analog switch. A sinusoid is given to I/p of analog
S/w & ½ sinusoid to other I/p. of analog switch. Bit pattern is used as switching I/p.
At receiver we have used comparator using OPAMP. O/p of comparator is given to
transistor switch. Output of switch is given to monoshot. Monoshot is used for waveshaping.
Time period of monoshot is adjustable externally. At the O/p of monoshot we get required data.
ii. FREQUENCY SHIFT KEYING:

In computer peripheral & radio (wireless) communications, the binary data or code is
transmitted by means of a carrier frequency that is shifted between tow preset frequencies. Since
a carrier frequency is shifted between two preset frequencies, the data transmission is said to use
a frequency shift keying technique. The frequency shift is usually accomplished by driving a
VCO with the binary data signal so that the two resulting frequencies correspond to the logic “0”
& logic “1” states of the binary data signal. The frequencies corresponding to logic “1” & logic
“0” states are commonly called as the mark & space frequencies. Several standards are used to
set the mark & space frequencies. For example, when transmitting teletypewriter information
using MODEM system a 1070HZ –1270HZ (mark -space) pair represents the originate signal,
while 2025HZ-2225HZ (mark -space) pair represents the answer signal. In our kit we have used
XR2206 IC for FSK Generation. Mark & space frequencies can be independently adjusted by the
choice of timing resistors. In our kit mark frequency is fixed & space frequency can be adjusted
using pot provided on panel. Detail cct diagram is also provided. Baud rate of our system is
330HZ. At receiver our aim is to distinguish two frequencies. For this purpose XR2211, a
monolithic phase-locked Loop IC is used. The circuit consists of a basic PLL for tracking an I/p
signal within the pass-band, a quadrature phase detector which provides carrier detection & a
FSK Voltage comparator which provides FSK demodulation.

Procedure:-
i. AMPLITUDE SHIFT KEYING:
1. Switch on the power supply.
2. Observe SINE & ½ x sine on dual scope CRO.
3. Observe O/Ps of pattern Gen & connect any one pattern to pattern I/p of analog switch.
4. Observe ASK O/p together with pattern I/p.
5. Connect ASK O/p to ASK I/p of COM Block.
6. Observe O/p of ‘COM’ Block .Adjust nearby pot to get O/P of comparator.
7. Observe O/p of ‘MONO’ Block & adjust it properly using pot provided near mono
Block.
i. FREQUNECY SHIFT KEYING:

1. Switch on the Power supply.
2. Connect pattern “P1” or “P2” as I/p to FSK Generator i.e. XR2206 I/p.
3. Adjust pot of XR2206 such that two frequencies can be easily distinguished & a neat
FSK wave form is observed on dual scope CRO.
Now to study FSK receivers follow the following procedure.
4. Connect I/p of FSK Generator to 5v i.e. (Vcc), logic “1” state & measure FSK O/p
frequency, say “F1”.
5. Now connect I/p of FSK Generator to GND i. e. logic “0” & observe FSK O/p, frequency
say F2. Now using pot of XR 2206 adjust F2 such that (f2= f1+200).
6. Now calculate PLL center frequency fo,
fo = f1 + f2
2
7. Now connect “A” pt. of XR2211 to “B” pt, so that we can observe free running frequency
of PLL at “D” point.
8. Now by using ‘VCO FREQ ADJ’ pot adjust free running frequency to fo.
9. Now disconnect pt “A” from pt “B” & connect pt “A” to pt “C”.
10. Connect FSK O/p to I/p of capacitor near “C” pt & observe detected O/p of XR-2211
which is required O/p.
Connection Diagram:
i. Amplitude Shift Keying

ii. Frequency Shift Keying
FSK MODEM Vcc

D
FSK O/P C
A
XR - 2211
XR - 2206 O/P
B I/P
Vcc
I/P
P1
PATTERN
VCO FREQ. ADJ.
GEN.
P2
GND.
POWER ON
Conclusion:
ASK WAVEFORMS:
Carrier
5
Amplitude
-5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time
Square Pulses
4
Amplitude
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time
ASK Signal
10
Amplitude
-10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time

FSK WAVEFORM
1 0 1 0 0 1
DATA
FSK
O/P
REC.
DATA

Experiment No 5
BINARY PHASE SHIFT KEYING & QUADRATURE PHASE SHIFT KEYING

I. Binary Phase Shift Keying Modulation and Demodulation.
II. Quadrature Phase Shift Keying Modulation and Demodulation.
Equipment’s: BPSK Kit, QPSK Kit, Patch Cods, DSO or CRO, CRO probes.
Theory:-
i. Binary Phase Shift Keying
In binary PSK the transmitted signal is a sinusoid of fixed amplitude. It has one fixed phase
when the data is at one level & when the data is at the other level the phase is the different by 180. In
our kit we have derived a sinusoid from a crystal clock using IC 4017’s & frequency divider & 2 nd
order butter worth filter & for phase shifted wave form we have used OPAMP Inverter.
Also two different bit patterns are also derived from a basis clock. For transmitter section
we have used IC 4052 [Analog Switch]. A sinusoid & phase shifted sinusoid are two I/p’s to
analog switch & bit pattern is connected to control I/p of 4052. O/p of 4052 is required BPSK
O/p.
At receiver we have to derive carrier frequency from BPSK wave form. So this
waveform is given to squaring circuit (IC 1496 multiplier). At the o/p of 1496 we have 2fc
frequency. By using Band pass filter with center frequency 2fc we get neat sinewave & it is
given to freq divider IC 4017. Output of divider is our recovered carrier.
For detection of data from BPSK signal, phase comparator section of PLL (IC 565) is
used. One I/p to PLL is BPSK Signal & Other I/p recovered carrier. O/p of PLL is then given to
filter.
BPSK system is having one inherent disadvantage or drawback i.e. at receiver O/P we may
get inverted data. This is because at carrier recovery section we get either in phase or out of
phase carrier since there are only two possible phases. If we recovered 180 deg.out of phase
carrier then we get inverted data at receiver O/P. To remove this drawback normally DPSK or
DEPSK systems are used. In our kit we have given one method to get always in phase data. If we
do all necessary connections as mentioned in the procedure & make power supply switch on,
then we get always in phase data. Here one power on mono.is ‘OR’ed with bit pattern. Receiver
knows that after power on logic ‘1’should be the 1st bit if it is zero then receiver comes to know
that carrier recovered is out of phase. Then other bits coming later on also will be inverted. So by
using analog sw. invert of whatever is recovered is given out as receiver O/P, so that we get
correct data. If at power on logic 1 is received then the same is given out as receiver O/P. so we
get always in phase data.
To observe BPSK signal on CRO there are two ways to do so. First connect bit pattern &
BPSK signal to two channels on CRO & trigger it properly i.e. when bit is going to zero from
logic 1 position or going to logic 1 from logic 0 position we get 180 deg. Phase shift in carrier.
The other way is to connect sine wave & BPSK signal to two channels of CRO & then
by pressing ‘XY’ mode switch we get lissageous fig. i.e. two cross lines on screen.

180
ii. Quadrature Phase Shift Keying:

To transmit digital data on analog lines (Viz. telephone) or even into space, modulation of analog
signal is required. Simplest way is BPSK Where one phase of carrier is transmitted for ‘1’ and
inverted carrier is transmitted for digital ‘0’. Here if bit rate is “Tb’ then bandwidth required Is
‘2Tb’. To reduce this bandwidth requirement QPSK can be used. For QPSK bandwidth required
is ‘Tb’ i. e. half that of BPSK.
‘QPSK’ technique comes under ‘carrier modulation’ type. Here I/P to the transmitter is
digital data, in between processing is in analog form & finally O/P of receiver is again digital
data same as fed to transmitter. ‘Q’ in ‘QPSK’ means quadrature i. e. 4, four phases of carrier are
transmitted depending upon bit pattern. e.g. we know that incoming bit pattern is divided into
‘odd’ & ‘even’ bit patterns. Odd pattern is multiplied by sine wave, & even pattern is multiplied
by cos wave. Sine & cos waves are 90 degree phase shifted. Now resulting two PSK’s are added
& we get vector addition O/P i. e. if both odd & even pattern bits are ‘1’ we get 45 degree phase
shifted carrier. If odd bit is 1 & even bit is 0 we get 135 degree phase carrier. If odd bit is 0 &
even also 0 we get 225 degree. If odd bit is 0 & even bit is 1 we get 315 degree.
In QPSK , two consecutive bits are stored & for resulting four combinations (4) different
phases of carrier are transmitted. By using ‘D’ flip-flop type arrangement incoming bit pattern is
divided into two bit patterns Viz. odd pattern & even pattern, for obtaining this, basic clock
whose frequency is ‘fb’ is divided by two, resulting odd & even clock frequencies are ‘fb/2 ‘&
they are complementary. Each bit is stored for 2Tb. time period. Odd pattern will have bit no.
1,3,5,7, etc. each stored for ‘2Tb’ & even bit pattern will have bit no.2,4,6, etc. stored for ‘2 Tb’.
Here active edges of, odd & even clocks are seperated by time ‘Tb’. So out of two bits only
one bit is changing (either odd or even ) after each ‘Tb’period but every bit is there for 2 Tb
time ; so in this offset QPSK system every time phase changes by 90 degree only.
Then QPSK signal is multiplied by ‘SINE & COS’ carrier waves. As A result we get odd &
even patterns after filtering & intergrating multiplier Outputs. Now by combining these two
patterns we can get original bit Patterns. This is done by using switch (analog switch).
To observe QPSK, we have given two bit patterns (i. e. repeated after 5 bits.) so
that on analog CRO we can observe the wave forms. Here carrier phase changes every after time
‘tb’ ( bit period ) depending upon odd & even bit combination. It is difficult to observe this on
analog CRO. Details of these phase changes are shown in diagram attached. To observe QPSK
we can use lissageous patterns. i. e. If we connect ‘SINE’ wave to one channel & ‘COS’ wave
to the other channel & press ‘XY’ button of CRO we get circle on screen. ( this is lissageous
pattern for 90 degree phase shifted waves)
Now if we connect ‘SINE’ & its associated PSK signal to two channels & press ‘XY’
mode button we get two crossed lines.( One of 0 degree & the other for 180 degree phase )
180

If ‘SINE’ & ‘QPSK’ signals are connected to two channels, on ‘XY’ mode we get two crossed
ellipses. This is because for 45, 135, 225 & 315 degree we get ellipse as lissagous figure.
135,315 45,225
Also at transmitter observe that ‘SINE’, ‘COS’ wave amplitudes are lesser than resulting ‘QPSK’
wave because of vector addition.
We are doing this complex processing to save on bandwidth requirement of the system.
This can be observed on CRO also. Observe bit pattern on CRO along with odd or even bit
pattern, you will come to know that odd or even bit pattern frequency is lesser than original bit
pattern frequency.
PROCEDURE:-
i. Binary Phase Shift Keying:
1. Connect O/p of pattern Gen (Either Pattern1 or Pattern2) to I/p of ‘OR’Gate.
2. Connect O/p of OR gate to I/p of PSK GEN. Block.
3. Observe o/p of PSK GEN on CRO as above procedure.
4. Connect O/p of PSK GEN Block i.e. BPSK O/p to I/p of 1496 Sq. cct & I/p2 of
PHASE COMP Block.
5. Observe o/p of 1496 Squ. Cct & Connect O/p of 1496 Sq. cct to I/p of B. P. Filter.
6. Observe o/p of BP filter & adjust it using ‘POT’ provided on pannel such that we get
maximum o/p & neat sinewave of freq. 2Fc. Connect O/p of BP filter to I/p of %2
N/W.
7. Observe o/p of %2 N/W. It is a square wave of freq ‘F’ which is our recoverd carrier.
Connect This O/p to I/p1 of phase comparator.
8. Observe filter O/p & COMP. Block O/p. The O/p of COMP. Block is required detected
O/p.
9. Observe COMP o/p with i/p pattern on CRO simultaneously. If it is inverted switch
off the power supply & make it on again. We will get correct data.
ii. Quadrature Phase Shift Keying

1. Observe ‘CLK’O/p, measure its frequency. This is nothing but ‘Fb’
2. Connect ‘CLK’O/p to I/p of ‘Odd & Even CLK Gen’ observe ‘O’ CLK ( i. e. odd CLK)
& ‘E CLK’ Frequency is ‘fb/2’.
3. Observe two patterns of pattern gen. & connect first pattern to I/p of O & E Data
generator.
4. Observe ‘O Data’ (i. e.. Odd Data) & ‘E’ Data along with I/p pattern on dual trace CRO.
5. Connect ‘O’ Data to ‘O’ Data pt. Pf 1496 Mul’. [I.e. 1496 Multiplier].
6. Connect ‘E. Data’ to ‘Edata’ pt. of 1496 ‘Mul’.
7. Observe ‘SINE & COS waves & measure their frequencies. & also observe on ‘XY’
mode of CRO
8. Observe pt. A with ‘O. Data’ on dual trace CRO. This is PSK signal of ‘O’ Data.

9. Observe pt. A with sinewave on CRO.( ‘XY’ mode)

10. Observe pt. ‘B’ with ‘E’ Data’, this is PSK signal of ‘E. Data’.
11. Observe pt. B with coswave on CRO.( ‘XY’ mode)
12. Observe QPSK O/p with bit pattern. & then with Sine wave. Press ‘XY’ mode & observe
two ellipse .
13. Connect QPSK O/p to common I/p pt . of 2, 1496 Mul blocks.
14. Connect SINE wave from transmitter section to SINE of 1496 MUL block.
15. Connect COS wave from transmitter section to COS of 1496 MUL block.
16. Observe final O/p with the original I/p bit pattern.There is delay between i/p & o/p .
17. Observe pt. ‘C’ & ‘D’.These are odd & even bit patterns received at receiver.
Connection Diagram:
i. Binary Phase Shift Keying
PSK MODEM O/P I/P
CARRIER I/P 1496 BP

SQU. FILTER %2 N/W
MULT. CCT. 2F
PSK GEN. PSK O/P
I/P O/P
I/P O/P
OR
O/P
GND.
START
SIGNAL
PHASE FILTER
COMP. COMP.
DATA
I/P1 O/P
PATTERN P!
GEN. I/P2
POWER ON
P2
Points to observe only

ii. Quadrature Phase Shift Keying

a. Connection Diagram for Carrier Recovery
Connection Diagram for Carrier Recovery
CARRIER
QPSK MODEM RECOVERY
SECTION
BP. POT
I/P
I/P I/P
TRANSMITTER
I/P
ODD 1496 1496 BP
CLOCK EVEN O. CLOCK SQ. SQ. FILTER %4 N/W
CLOCK 1 2 4F
GEN.
SINE
I/P E. CLOCK
O/P O/P O/P
O/P
SINE W.
COS
QPSK I/P
1496 O/P C
O. DATA MUL. 1496
ADDER RECEIVER
A MUL.
1496
MUL.
E. DATA SINE
COS W. B
O. DATA SWITCH
SINE O/P
1496
O&E PATTERN MUL.
I/P GEN.
DATA
GEN.
E. DATA COS D CLOCK
COS GND.
E. CLOCK
Pts. To Observe Only O. CLOCK POWER ON
b. Connection Diagram for QPSK Transmitter & Receiver

Connection Diagram for QPSK Tr & Re.
CARRIER
QPSK MODEM RECOVERY
SECTION
BP. POT
I/P
I/P I/P
TRANSMITTER
I/P
ODD 1496 1496 BP
CLOCK EVEN O. CLOCK SQ. SQ. FILTER %4 N/W
CLOCK 1 2 4F
GEN.
SINE
I/P E. CLOCK
O/P O/P O/P
O/P
SINE W.
COS
QPSK I/P
1496 O/P C
O. DATA MUL. 1496
ADDER RECEIVER
A MUL.
1496
MUL.
E. DATA SINE
COS W. B
O. DATA SWITCH
SINE O/P
1496
O&E PATTERN MUL.
I/P GEN.
DATA
GEN.
E. DATA COS D CLOCK
COS GND.
E. CLOCK
Pts. To Observe Only O. CLOCK POWER ON

Conclusion:
i. PSK WAVEFORMS:
CARRIER
PATTERN
PSK O/P
BPF
RECOVERED
CARRIER
PHASE
COMPARATOR
O/p
FINAL O/P
ii. QPSK Waveforms
CLK QPSK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
PAT.N
O.CLK
E.CLK
O.D
E.D
QPSK 135 315 135 315

225 225 225

CLK QPSK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PAT.N
O.CLK
E.CLK
O.D
E.D
QPSK 45 315 45 135 45 315

135

Experiment No 6
DIGITAL MODULATION SCHEME USING MATLAB
AIM: Study of any digital modulation scheme using Matlab communication tool
EQUIPMENTS: Personal Computer, MATLAB software
THEORY:
The digital modulation techniques are classified into two categories as
1. Coherent Techniques: In the coherent digital modulation techniques, we have to use a phase
synchronized carrier to be generated at the receiver to recover the information signal. Coherent
techniques are complex but yield better performance.
2. Non – coherent Techniques: In the noncoherent techniques, no phase synchronized local
carrier is needed at the receiver. These are less complex, but the performance is inferior to that of
coherent techniques.
When it is necessary to transmit digital data over a bandpass channel, it is necessary to
modulate the digital data onto a carrier wave which is usually sinusoidal. The digital signals are
in the form of train of pulses. When these pulses are transmitted over a communication medium
without its shape, the communication medium must have a large bandwidth. Practically, we use
the telephone lines as a communication medium for sending digital data from one place to other.
The well known example of such communication is computer – to – computer communication.
This communication is through a local area network or wide area network or internet. The
telephone lines used for such application do not have sufficient bandwidth to transfer the digital
data without distortion. Therefore, we cannot put the digital data directly on the telephone lines.
Instead of putting the digital data as it is on the telephone lines, it is converted into a suitable
form which is compatible to the telephone lines. For this conversion, we need to use a modulator
on the sending end and demodulator on the receiving end. A special communication box called
MODEM does the modulation and demodulation process. MODEM is a combination of a
modulator and demodulator. A modulator converts the digital data coming from a DTE into an
analog signal which needs lower bandwidth. Thus modulation process is used for conversion of
digital data into its equivalent analog signal. The demodulator at the receiving end will reconvert
this signal and applies it to DTE at the receiving end which is nothing but a computer. Thus it is
necessary to convert the digital data into some kind of analog signal so that the bandwidth
requirement is reduced. For this conversion we have to use certain modulation techniques.
The basic continuous wave modulation techniques used by a modem to convert digital data to
analog signals are:
1) Amplitude Shift Keying: The amplitude shift keying (ASK) operates on the principle of
transmitting two different levels of a sinusoidal carriers corresponding to the logic states of “0”
and “1” in the digital data
2) Frequency Shift Keying: In the binary frequency shift keying (FSK), sine waves of two
different frequencies are transmitted corresponding to the “0” and “1” states of the digital data.

3) Phase Shift Keying: In the binary phase shift keying (PSK), the phase shift of a sinusoidal
carrier is switched from one value to the other corresponding to the changeovers from “0” to “1”
in the digital data.
Thus for all these techniques, we are using a sinusoidal carrier which is a continuous
signal. Therefore, these techniques are known as continuous wave modulation (CW) techniques.
PROCEDURE:
1. Open MATLAB software. Open a new “.m” file in it.
2. Type the program for ASK and phase shift keying.
3. Save and run the program.
4. Print the figure output.
CONCLUSION:
ASK Code
clear all;
clc;
close all;
F1=input('Enter the frequency of carrier=');
F2=input('Enter the frequency of pulse=');
A=3;%Amplitude
t=0:0.001:1;
x=A.*sin(2*pi*F1*t);%Carrier Sine wave
u=A/2.*square(2*pi*F2*t)+(A/2);%Square wave message
v=x.*u;
subplot(3,1,1);
plot(t,x);
xlabel('Time');
ylabel('Amplitude');
title('Carrier');
grid on;
subplot(3,1,2);
plot(t,u);
xlabel('Time');
title('Square Pulses');
grid on;subplot(3,1,3);
plot(t,v);
xlabel('Time');

title('ASK Signal');
grid on;
Enter the frequency of carrier=30
Enter the frequency of pulse=5
PSK Code
clear all;
clc;
close all;
set(0,'defaultlinelinewidth',2);
A=5;
t=0:.001:1;
f1=input('Carrier Sine wave frequency =');
f2=input('Message frequency =');
x=A.*sin(2*pi*f1*t);%Carrier Sine
subplot(3,1,1);
plot(t,x);
xlabel('time');
title('Carrier');
grid on;
u=square(2*pi*f2*t);%Message signal
subplot(3,1,2);
plot(t,u);
xlabel('time');
title('Message Signal');
grid on;
v=x.*u;%Sine wave multiplied with square wave
subplot(3,1,3);
plot(t,v);
axis([0 1 -6 6]);
xlabel('t');
ylabel('y');
title('PSK');
grid on;
Generated PSK Signal
Carrier Sine wave frequency =10

Message frequency =2

Experiment No 8
ERROR DETECTING & CORRECTING CODES
Aim: To perform error correction and detection of code logic
Equipments: Error correction and detection kit, Patch Cods, CRO, CRO probes.
Theory:
Normally we transmit the data in digital format. In the transmission due to the noise
some bits get corrupted & error is introduced. So need arises to detect such error & correct it.
There are several codes for such purpose.
Hamming Code [7, 4]:
In this we can correct one error. Four un-coded bits are given to generate 3 code bits. So
ultimately we have 7 bits, in total. If a1, a2, a3, a4 are un-coded 4 bits, corresponding 3 code bits
are as follows-
C1 = a1 + a2 + a3
C2 = a1 + a2 + a4
C3 = a1 + a3 + a4
So by using Ex-or gate we generate 3 code bits. Then we transmit these 7 bits serially by
multiplexer and received parallel by using shift register. At receiver we get code word we can
introduce single error anywhere to see its effect. From received 7 bits i. e. R1 to R7 we find out
syndrome matrix by formula.
S1 = R1 + R2 + R3 + R5
S2 = R1 + R2 + R4 + R6
S3 = R1 + R3 + R4 + R7
By using 3 to 8 multiplexer we find out error pattern. For zero syndrome matrix error pattern is
all 7 zeros. Then by ex-oring error pattern with received code word we get actual transmitted
code word. Thus by using this type of code we not only detect error but also correct it.
Procedure :
1) Switch on ‘Power ON’ switch on panel. Red LED should glow.
2) On panel 2 columns of 5V and Gnd with 4 points each are given. We use these points as a bit
pattern.
3) For hamming code, again connect any 4 bit pattern to its I/p. observe its 7 O/ps. Verify this
for all bits patterns.
4) Internally connected 7 O/ps from Hamming code generator to 7 I/ps of multiplexer. Leftmost
point of Hamming code generator should be connected to leftmost point of 74151
multiplexer.
5) Observe multiplexer O/ps.
6) Connect multiplexer O/p to I/p of shift register & observe shift register O/ps. All toggle
switches to upward position.

7) Connect these 7 O/ps to 7 I/ps of syndrome generator sequentially i.e. leftmost point to
leftmost point.
8) Observe syndrome matrix on 3 points provided on panel.
9) 7 LEDS at “CORRECTOR BLOCK” give actual code word.
10) Now introducing single error at different position observe O/ps of “CORRECTOR
BLOCK”.
11) Observe error pattern LEDs E1to E7 each time.
NOTE
1. Block Diagram is enclosed.
2. Detail circuit diagram gives all Hardware Details inside the Kit.
3. Kit is fitted in brief case, so kindly avoid the scratches on the printed acrylic board.
Connection Diagram:
Connection Diagram for Hamming Code

Points For Observation Only
I/N
HAMMING CODE SYNDROM ERROR PAT. CORR.BLACK

GEN. GEN. GEN.
LSB ERROR PAT.

E1 TO E7
GND
74151 MUX GND SHIFT REG I/p
5V
O/P
EVEN
PARTY GEN.
REC O/P
GEN. 74138
I/P POWER ON
PARTY CHECKER
Observation Table:
Data bits Code words Error Patterns Received Codes Syndrome
CONCLUSION:

Experiment No 9
BLOCK DIAGRAM DEVELOPMENT FOR DIGITAL MODULATION USING
MATLAB/SIMULINK
Aim: To develop a block diagram for digital modulation using modulation using
MATLAB/Simulink.
Equipment’s: Error correction and detection kit, Patch Cods, CRO, CRO probes.
Theory:
Simulink is a program for simulation of dynamic systems that provides a graphical
interface. Within the MATLAB environment it is a toolbox. Dynamical systems are often
represented using block diagrams. The graphical interface allows us to use such a block diagram
directly for programming Simulink. The dynamical system in our case is the digital modulation
scheme with time-varying data.
Simulink is started by the command
Simulink
From MATLAB workspace. The Block Library Browser will open and provide the
blocks available in the Simulink library.
The library is subdivided according to the functions of the blocks, such as Sources or
Sinks. You can open a library by double-clicking on the respective button.
Procedure:
1. Open MATLAB software. Open a new “.m” file in it.
2. Type the program for ASK and phase shift keying.
3. Save and run the program.
4. Print the figure output.
Conclusion:

Experiment No 10
PERFORMANCE COMPARISON OF DIFFERENT TYPES OF ANTENNAS
Aim: Performance comparison of Simple Dipole antenna, Log Periodic antenna, Yagi-Uda
antenna.
Equipment’s: Main unit, power cord, coaxial antenna mast (At Tx), detector unit, transmitting
and receiving antenna, Receiving antenna mast.
Theory:-
Simple Dipole:
A simple Dipole is the simplest form of antenna having 2 poles each of length (/2). The
nominal impedance of this antenna is 73. The actual value departs from this due to construction
constraints, such on non-zero diameter rods, presence of BNC connector body and the antenna
mast. The effect of all this are partially corrected by a "Y match" arrangement connection. See
Figure 1.
The radiation pattern of simple Dipole (/2) is uniform in forward & reverse direction.
The polarisation is horizontal. The typical radiation pattern of this antenna is given in Figure 2
Figure 1. λ/2 Dipole Antenna structure

Log Periodic Antenna:

The main feature of this antenna is frequency independence for both radiation resistance and
pattern. The radiation pattern may be unidirectional or bidirectional. Bandwidth of 10:1 is easily
achievable.
The array consists of number of dipoles of different lengths and spacing, and fed from a two wire
line which is transposed between each adjacent pair of dipoles. The array is fed from narrow end
and maximum radiation is in this direction. See Figure 1.
If a graph is drawn of antenna input impedance v/s frequency, a repetitive variation will be
noticed. If plotted against log of frequency instead of frequency, then variation is periodic
consisting of identical cycles. All other properties of antenna undergo similar variation especially
radiation pattern. It is this behaviour of antenna, which has given, log periodic name.
This is a horizontally polarised antenna. Typical radiation pattern is shown in Figure 2
Procedure:
1. Simple Dipole Antenna
2. Mount simple dipole (/2) on the top of the transmitting mast
3. Arrange the Set up as per Procedure I and draw the polar graph.
Figure 2 Radiation pattern of λ/2 dipole antenna

2. Log Periodic Antenna

1. Mount the Log Periodic antenna on the transmitting mast.
2. Arrange the Set up as per procedure given in Experiment 1 and draw the polar graph.
Figure 7. Log-periodic structure
Figure 8. Radiation Patterns of Log periodic antenna

3. Yagi-uda Antennas:
1. Arrange the set up as given in Procedure I of Experiment No. 1
2. First mount Yagi-uda 3 element folded dipole on the transmitting mast. After
performing following procedure and calculations and plotting polar graph for Yagi-
uda 3 element folded dipole, mount Yagi-uda 5 element folded dipole, Yagi-UDA 5
element simple dipole, and then Yagi-UDA 7 element simple dipole one after
another.
3. Bring the detector assembly near to main unit and adjust height of both transmitting
and receiving antenna same.
4. Keep detector assembly away from main unit approximately 1.5m and align both of
them. Ensure that there is no reflector sort things in the vicinity of the experiment
such as steel structures, pipes, cables, etc.
5. Keep the RF level and FS adjust to minimum and directional coupler switch to FWD.
6. Keep detector level control in the center approximately.
7. Increase RF level gradually and see that there is deflection in detector meter.
8. Adjust RF level and detector level so that there is deflection in detector meter
approximately 30-35 µA.
9. Align arrow mark on the disk with zero of the goniometer scale.
10. Start taking readings at the interval of 10 deg. Note the deflection on detector
assembly.
11. Convert the µA readings of detector assembly into dB’s, with the help of conversion
chart or by 20Log( ___ µA).
12. Calculate Gain with the help of formula G=kD (where k=antenna efficiency factor
and D=Pmax/Pav) by assuming k as value between 0 to 1 (for eg: 0.75 for 75%
efficiency).
13. Plot the polar graph in degrees of rotation of antenna against level in detector in dB’s.
14. Calculate the following with the help of this graph
a)Beam width b)Front/back ratio
15. To calculate the above from graph, proceed as follows:
Beam width:
Look for main lobe. Draw boresight maxima line OA
Mark -3dB from maximum on the boresight line point B
Draw an arc of radius OB
This arc will intersect main lobe at C & D.
Measure angle COD. This angle is -3dB beamwidth.
Similarly calculate -10dB beamwidth.
Front to back ratio:
Look for the main lobe.
Draw boresight maxima line OA
Look for back lobe if any (At 180 deg.)
If no back, then front to back ratio = OA dB
If there is back lobe, then measure OE where E is maximum of back lobe.
Then, front to back ratio= OA/OE (in dB)
Conclusion:

Experiment No.11
VELOCITY, TIME & FREQUENCY OF RADAR USING MOVING PENDULUM
AIM: Determination of velocity of object moving in RADAR range and also time & frequency
of RADAR using moving Pendulum.
EQUIPMENTS: Radar Trainer system, PC with RFbeam signal viewer Software, Experimental
manual, Oscilloscope, Pendulum, USB Cable
THEORY:
Experimental Setup
PROCEDURE:
1. Do the Experimental setup as shown in Fig 1. Connect radar trainer System to the computer
with USB to USB cable provided.
2. Radar Trainer System does not require external power supply. It gets powered from Computer
3. The computer will treat radar training system hardware as “USB Sound System” & thus does
not require any driver.
4. When pendulum moves to and fro in front of transceiver antenna it will reflect the incoming
microwave Signal.
5. The reflections can be observed on RFbeam Signal Viewer software or on DSO at Amplified
Radar signal Post.
6. Open the Rfbeam Signal Viewer software and Record the signal for sufficient time and then
playback the recorded file. Playback signal can be observed on DSO at Playback Signal Post on
front plate.
7. Measure the time period between two reflected signals. Measured time is the time required by
pendulum to complete one oscillation.
8. Take the inverse of the measured time; it will give the frequency of oscillation of pendulum at
that length.

9. In another case move the pendulum in a direction perpendicular to the axis of the radar.
Analyze the difference in their reflected signals.
10. Move the pendulum at different angles to radar and see if the time Measurement remains
same.
11. Vary length of pendulum, and find out the different Time periods using Radar.
12. Theoretically Time Period of pendulum is given by:
T = 2π. √(l/g) where l is length of pendulum and g is constant 9.8 m/s2.
13. Compare the Practical results to the theoretical time periods.
OBSERVATIONS:
• Time Domain Display of Signal Viewer software
• Amplified Radar Signal on Front panel of System
• Playback Signal on Front panel of System
Result: Snap of software window shows reflections due to movement of pendulum.
CONCLUSION:

Experiment No.12
MEASUREMENT OF CHARACTERISTIC/INPUT IMPEDANCE /ATTENUATION OF
TRANSMISSION LINE
AIM: Measurement of characteristic/Input Impedance /Attenuation of transmission line.
EQUIPMENTS: Transmission line trainer kit, patch cords, DSO
THEORY:
A line that has not been terminated with the load equal to its characteristics impedance is
subjected to a reflection phenomenon of the power from the remote end. The amount of the
reflected power depends on the amount of mismatch between the characteristics impedance of
the line and the load impedance. In the extreme case of short circuited line (Rl = 0) and open
circuit (Rl = ∞) a situation of load reflection occurs for either the current wave or the voltage
wave. The purpose of this test is to study the establishment of the stationary wave within the line.
PROCEDURE:
1. Adjust Ri and rl for 18Ω and 68Ω respectively with the help of DMM.
2. Make connections as shown in figure 1.
3. Set oscilloscope to 0.1V/div for both channels.
4. Adjust the sine generator for an output of 0.2V P-P (2 div deflection on ch1) and at
frequency 100 KHz.
5. Observe the peak to peak voltage on ch2 at 100m and at the intermediate sockets at
75m, 50m, 25m, and 0m.
6. Tabulate the results as under
OBSERVATIONS:
DISTANCE VOLTAGE (P-P)
0m
25m
50m
75m
100m
7. Calculate the stationary wave ratio by using the formula
S = Vmax / Vmin for 100KHz is approximately 1.25.
8. The reflection coefficient ‘r’ of the line shows how much of the energy is supplied at
the input and being reflected as the consequence of the load decoupling. The
reflection coefficient is normally expressed in percentage and can be determined from
the stationary wave ration by the formula
R = (S-1)/(s-2)
At 100KHz is approximately 11%.
9. Repeat the same procedure for open and short circuit lines.
10. Try the same experiment with other frequencies to see the effect of frequency on ‘s’
CONCLUSION:

Experiment No.13
FIND RADIATION PATTERN OF BROADSIDE ARRAY ANTENNA USING MATLAB.
AIM: Write a program to find radiation pattern of Broadside array antenna using MATLAB.
EQUIPMENTS: MATLAB SOFTWARE, PC
THEORY:
An array is said to be broad side if phase angle is such that it makes maximum
radiation perpendicular to the line of array i.e. 900 and 2700.
PROGRAM:
clc;
close all;
clear all;
phi = 0:0.1:2*pi;
c = 3 * (10^8);
f = input(‘enter frequency of signal’);
lambda = c/f;
beta = 2*pi/lambda;
dr = beta * d;
delta = input(‘give value of delta’);
n = input(‘enter number of points v/s’);
si = abs(dr * cos(phi) + delta);
E = abs ((sin(n * si/2)) ./ sin(si/2));
Polar(phi,e)
OUTPUT:
Enter frequency of signal: 1e9
Beta = 20.9440
Dr = 3.1416
Give value of delta0
Enter number of point sources n = 4
CONCLUSION:

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SANT DNYANESHWAR SHIKSHAN SANSTHA’S

ANNASAHEB DANGE COLLEGE OF ENGINEERING & TECHNOLOGY, ASHTA

DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION

This is to certify that Mr. /Ms. ____________________________________________________

Prepared By : Mrs. M. M. Raste Page 3

SAMPLING & PULSE CODE MODULATION & DEMODULATION (PCM)

Aim: To Conduct and Observe the waveform of

By Nyquist theorem, if signal contains no frequency components for F > B. W., it is

1. Switch on ‘Power on’ switch , red LED should glow.

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3. Connect this 1MHz clock to ADC 0809 clock I/p.

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PCM MODEM POINTS TO OBSERVE ONLY

RST CLOCK CONTROL

CLK 500 KHz

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DELTA MODULATION & DEMODULATION (DM) & ADAPTIVE DELTA

Aim: To Conduct and Observe the waveform of

Prepared By : Mrs. M. M. Raste Page 7

ii. Adaptive Delta Modulation

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iii.Adaptive Delta Modulation

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B IC 7404 IC 7483 IC 74373

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II. ADAPTIVE DELTA MODULATION

ADM O/P S. CLOCK

IC74193 IC 7404 IC 7483 IC 74373

DELTA MODULATION WAVEFORMS

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ADAPTIVE DELTA MODULATION WAVEFORMS

B ‘4 013 ‘ PIN (1)

‘4 013 ‘ PIN (13) I. e. C

NON - INVERTING INPUT OF COMPARATOR IS OPEN FOR THIS DIAGRAM.

Prepared By : Mrs. M. M. Raste Page 12

AMPLITUDE SHIFT KEYING (ASK ) & FREQUENCY SHIFT KEYING (FSK)

Aim: To Conduct and Observe the waveform of

ii. FREQUENCY SHIFT KEYING:

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i. FREQUNECY SHIFT KEYING:

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ii. Frequency Shift Keying

FSK MODEM Vcc

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BINARY PHASE SHIFT KEYING & QUADRATURE PHASE SHIFT KEYING

Aim: To Conduct and Observe the waveform of

Prepared By : Mrs. M. M. Raste Page 17

ii. Quadrature Phase Shift Keying:

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ii. Quadrature Phase Shift Keying

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9. Observe pt. A with sinewave on CRO.( ‘XY’ mode)

i. Binary Phase Shift Keying

PSK MODEM O/P I/P

CARRIER I/P 1496 BP

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ii. Quadrature Phase Shift Keying

Pts. To Observe Only O. CLOCK POWER ON