Makerere University Introduction to Digital Electronics Start: March 16, 2020

Group Assignment Dr. Edwin Mugume Due: March 27, 2020

Instructions:
To implement this lab, you will use Multism. Do not give theoretical background on any question – just
get on with it. Keep your reports brief and neat. You will submit a hard copy – make sure that your
printed work is clear, and the diagrams are large enough to ensure clarity. Document formatting is a big
thing for me – I will reward you for good formatting.

HARDWARE DESCRIPTION LANGUAGES

Recent trends in the field of digital systems are favoring text-based language description of digital
circuits. For example, see Figure 3-42 in our course reference book to see the four different ways that a
digital scenario could be represented. From this assignment forward, we will begin to learn some of the
more advanced tools that professionals in the digital field use to describe the circuits that implement
their ideas. These tools are referred to as hardware description languages (HDLs). Even with the
powerful computers we have today, it is not possible to describe a logic circuit in English prose and
expect the computer to understand what you mean. Computers need a more rigidly defined language.
Our reference book uses two languages in this text: Altera hardware description language (AHDL)
and very high-speed integrated circuit (VHSIC) hardware description language (VHDL).
However, there are other description languages such as Verilog. In our assignments, we will concentrate
on AHDL, which is a simplified version of VHDL and is more appropriate at this stage. However,
professionals tend to use VHDL but with knowledge of AHDL, migrating to VHDL is easy.

Brief AHDL Tutorial

In the following paragraphs, I will attempt to give a few ideas of how to describe digital systems using
AHDL. I will also give an example of a typical simple circuit. However, you are encouraged to read on
your own (for example, Sections 3-17, 3-19 and 3-20, concentrating only on AHDL for now). In practice,
the code is written in software to perform a given digital logic function. Once it has been tested to work,
it is fed/inserted into a hardware digital board which can then be used in real circuits.
1. In AHDL, the following symbols are used for gates: AND = &, NOT = !, OR = #, and XOR =
$. For example, !A is the inverse of A, $! is XNOR, etc. The words “and”, “or”, “xor” and
“xnor” also work. I am sure you can work out the other gates such as NOR and NAND.
2. Typically, we have 𝑚 inputs and 𝑛 outputs in every digital system. As in any computer program,
we have to initialize our inputs and outputs. The syntax is as follows:
a. The inputs can be separated by commas on the same line, after which you add
“:INPUT”. The line is ended by “;”.
b. The outputs can also be separated by commas on the same line, after which you add
“:OUTPUT”. The line is ended by “;”. As an example of the syntax:
A, B, C : INPUT;
X, Y : OUTPUT;
This initialization part of the program is put under the SUBDESIGN keyword as follows:
SUBDESIGN program
(
A, B, C : INPUT;
X, Y : OUTPUT;
)

1
 The word program is the name of the program, and the code file should be saved under the
same name to avoid confusion.

3. Usually, in digital circuits, we have what are called intermediate nodes or buried nodes (see
Fig. 3-49). These are nodes between inputs and outputs. Outputs may consider buried nodes as
their inputs, and as in Boolean Algebra, we need to carefully develop the output expressions by
considering these intermediate nodes. In AHDL, you can define as many buried nodes as you
want. Considering a buried node labeled m, the syntax is defined under VARIABLE as:
VARIABLE
m : NODE;

4. The logic part of the program is put under the “BEGIN ---- END;” construction. This is also
the last part of the program. For example, imagine that our digital system has one out X that is
defined as follows: X = AB + C; then, we can an AND gate and an OR gate at the end. We can
define the output of the and gate as the buried node 𝑚. Our full program is then:
SUBDESIGN program
(
A, B, C : INPUT;
X : OUTPUT;
)
VARIABLE
m : NODE;
BEGIN
m = A & B;
X = m # C;
END;

5. I encourage you to read the reference sections I have given you, as well as watch YouTube
videos to learn more. I particularly encourage the three videos below. Although Verilog is used,
the software is the same and you can follow through while writing in AHDL.
a. https://www.youtube.com/watch?v=sV60DDYJD7E&t=86s
b. https://www.youtube.com/watch?v=l2JB6-a9JC8
c. https://www.youtube.com/watch?v=zwNbXQ8E3ng

Tutorial Example:
I will attempt to run the above program whose code I have already created. We run the Quartus software
– I will provide a copy to your class representative. However, note that there is a version of the software
(Quartus Lite) that is free to download from the Intel website and includes all the functionalities we
need to simulate our simple circuits. If you want, you can download your own copy.
1. YouTube video (a) will show you how to open the software and create a new project. On the
type of hardware to use, it really does not matter. If we had hardware in the lab to insert our
program, then we would choose the appropriate hardware for our project. However, I tend to
use Cyclone IV GX (for no major reason). I recommend that for each question you attempt,
you create a new project.
2. In video (b), you will see how to display the circuit you have created in the RTL viewer. It
should look exactly similar to what you created on paper.
3. In video (c), we create some timing diagrams for the different inputs and track how the output
is changing. In creating these timing diagrams for the inputs, make sure that there is enough
variability within the inputs to give as many different combinations as possible. An example
timing diagram is shown in Fig. 3-42 (d).

2
Assignment Questions:
Institutions:
For each question, show the code, the RTL viewer schematic, and the timing diagrams for me to track
how the circuit performs.

Question 1
Design the circuit in 3-53(a) using the concept of buried nodes.

Question 2
Design a two-output circuit that operates as follows:

• When inputs A = C, output Y will follow input B while output X will be 0.

• When inputs A ≠ C, output Y will be 0 while output X will follow input B.

Question 3
Implement a logic circuit that controls an elevator door in a three-story building. The circuit shown
below has four inputs. M is a logic signal that indicates when the elevator is moving (M=1) or stopped
(M=0). F1, F2, and F3 are floor indicator signals that are normally LOW, and they go HIGH only when
the elevator is positioned at the level of that particular floor. For example, when the elevator is lined up
level with the second floor, F2=1 and F1=F3=0. The circuit output is the OPEN signal, which is
normally LOW and will go HIGH when the elevator door is to be opened. Show all your working.