PART -A

Answer ALL questions (30 x 1= 30 marks)

1. Free running multivibrator is also called as

a) Stable muluyibrator
b) Voltage control ospillasor
c) Square wave oscillator
d) Pulse stretcher

Answer: b

2. Voltage to frequency conversion factor for VCO 1s

a) Ke=4Ve Af
b) By= 4fe'aV,
c) Ke=4h~™ AVe
d) Ke=1MafxaVe)
Answer: b

3. How to obtain a desired amount of multiplication in frequency multiplier?

a) By decreasing the multiplication factor

b) By increasing the input frequency

¢) By selecting proper divide by N-network

d) None of the mentioned
Answer: c

4. In VCOIC 566, the value of charging & discharging is dependent on the voltage applied at ;

a) Triangular
wave output
b) Square wave output

c) Modulating input |
d) All of the above
Answer:¢
 5. Which characteristic of PLL is defined as the range of frequencies over which PLL can acquire lock
with the input signal?

a) Free-running state
b) Pull-in ume
c) Lock-in range
d) Capture range
Answer: d

6. Express the output voltage equation of divider a

a) Vo= -(Vnee2)*(V2V3)
b) Vo= -(2*Veed)(Wa/Vs)
©) Vo= -(Vred)*(Va'Vx)
d) Vo= -Vier WV)
Answer: ¢

7. Find the condition at which the output will not saturate?

a) Vx> 10v
; Vy > 10v
b) Ux< 10v; Vy > 10v
c) Vx< 10v;
Vy < 10v
d) Nx> 10v ; Vy < 10v
Answer:c

8. For perfect lock, what should be the phase relation between the incoming signal and VCO output
signal?

a) 90 degrees I
b) 180 degrees
¢) In phase with each other
d) 270 degrees
Answer: a

9. Find
the equation for change
m frequency of VCO?

a) Af. = (2x AV) (RrsC7xVis)

b) Af,= AVP(4*Rr*CrVer)
ec) A= AVg(2RrCr<Vec)
d) Af, = (4eAV(RreCp
Voc)
Answer: a
 10. Find out the incorrect statement.
Monolithic phase detector 1s preferred for critical applications as it is;
1. Independent of variation in amplitude
2. Independent of variation in duty cycle of the input waveform
3. Independent of variation in response time
a)1&2
b)1&3
o)2&3
4)1,2&3
Answer: a
11. The output voltage ofanalog phase detector 1s given by
a) K fo - 2/4)
b) K .(@ - x)
c) K &@- 2/2)

4) K (9 + 7/2)
Answer: c

12. The maximum de output voltage in digital phase detector occurs

a) When the phase difference is 1/2

c) When the phase difference is 32/4

d) When the phase difference is 2a
Answer: b

13. What is the advantage of using filter in phase locked loop?

a) High noise immunity
b) Reduce the bandwidth of PLL
c) Provides dynamic range of frequencies

d) Provides stability
Answer a I

14. Which device is used for diagnostic purposes and for recording?
a) Low pass filter
b) Monolithic PLL
°) —

15. When does a digital phase detector can be used. where fo->output frequency, fs->input frequency.
a) Both fo& fs signals should be square wave
b) fo should be square wave & fs can be any non-sinusoidal wave
c) fs should be square wave & fp can be any non-sinusoidal wave
d) Both fo & fs can be any non-sinusoidal wave
Answer: a I
16, Express the output voltage of digital to analog converter?

a) Vo=KVex(di2"+d22*+....d,2*)
b) Ve =Vesik(di2-'+dy2*+....d,2*)
©) Ve=Vrs(di2-!+d227+....de2*)
d) Vo =K(d)2"+d227+___.d.2*)
Answer a
17. The polarity of reference voltage used during DAC depends on
a) Operating mode of Op-amp used
b) Type of converter used
c) Type of switch used
d) Type of filter used
Answer: c

18. The number of comparator required for flash type A/D converter
a) Triples for cach added
bit
b) Reduce by half for each added bit
c) Double
for each added bit
d) Doubles ex[ponentialty
for each added bit
Answer:c

19. In integrating
type ADCs, the

a) Input voltage is proportional to input averaged over the integration period.

b) Output voltage is proportional to input averaged over the integration period
¢) Output voltage is proportional to sum of input voltage
d) Input voltage is proportional to sum of input voltage.
Answer: b

20. Mention the application of dual slope ADC.

a) Thermocouple
b) Digital panel meter
9) Weighting scale
d) All of the mentioned
Answer: b

21. Which of the following represents over sampling DAC?

a) PWM DAC

c) Binary weighted DAC

d) Switched resistor DAC
Answer: b
22. In DAC. 1s the smallest analog output change that can occur as a result of an increment
in the
digital input.

a) Monotonicity
b) Resolution
c) Sampling rate
d) Dynamicity
Answer:b

23. In the sample and hold circuit, the period during which the voltage across capacitor ts equal to input
voltage

a) Sample period
b) Hold period
c) Delay period
d) Charging period

Answer: a I

24. The primary disadvantage of the flash analog-to digital converter (ADC) ts that

a) it requires the input voltage to be applied to the inputs simultancously

b) along conversion time is required

c) large number of output lines is required to simultaneously decode the mput voltage

d) large number of comparators is required to represent a reasonable sized binary number

Answer. d
25. is the serious problem in R-2R ladder type DAC.
a) more number of resisters required
b) Wide range of resistors value
c) Low resolution
d) Non-linearity
Answer: d
26. How mary equal intervals are present in a 14-bit D-A converter?

a) 16383
by 4095

c} 65535
d) 1023
Answer, a

27. Resolution ofa 6 bit DAC can be stated as

a) Resolution of | part m 63

bb) 6-bit resolution

¢) Resolution of 1.568% of full scale
d) All of the mentioned,

Answer: d

28. For n-bit DAC, Resolution should be

a) Vig(2™})
b) Ves/2"
c) Wrs/(2"-1)
d) Ves(Q"+1)
Answer ¢

29, The maximum deviation between actual and ideal converter output after the removal of error is
a) Absolute accuracy
b) Relative accuracy
c) Relative ‘absolute accuracy
d) Linearity
Answer: b

30. Accuracy of DAC should be

a) + (1/2) ofits MSB
b) = (1/2) of its LSB
c) Greater than of equal to (1/2)LSB
d) (1/2) of its LSB

Answer. d
 31. Find the lock m range of IC PLL 565.
Afl=+7.8 £/V
Afi=+5.8 £/V
Af,=+6.8 fo
Aft=47.8 V
Answer: a
32. Calculate the value of external timing capacitor, if no modulating imput signal 1s applied to VCO.
Consider £=25 kHz and Rr=5 kQ.
a) 6nF
b) 100uF
c) 2nF
d) 10nF
Answer: c I
33. Calculate the output frequency in a frequency multiplier if, fix = 200Hz is applied to a 7 divide by N-
network.
a) 1.2kHz
b) 1.6kHz
c) 1.2kHz

d) 1.9kHz
Answer: c

34, Determine the offset frequency of frequency translation, when the output and input frequency are

given as 75kHz and 1000Hz.

a) 35 kHz
b) 20 kHz I
c) 29 kHz
d) 14 kHz
Answer. b

35. Given f, = 1.2kHz and V = 13v, find the lock-in range of monolithic Phase-Locked Loop.
a) +575Hz
b) 2720Hz
ce) +150Hz
d) +1kHz
Answer: b

36, Determine the capture range of IC PLL 565 for a lock-in range of + [kHz , R=3.6 kQ and C=0.1 uF
a) AE = =430 KHz
b) af. = 2410 KHz
c) Af; = 2422 KHz
d) af, = +442 KHz

Answer: d
37. Find the lock-in range of monolithic Phase-Locked Loop from the given diagram.
(11/2)KgA
Ve

~(T1/2)KgA
a) -f-Afl to fer Afi
b) -f- Afi, to -f-Afc
©) f- Off, to f- Ofc
d) -fe Afg to f,-Afc
Answer: a

38. At what range the PLL can maintain

the lock in the circuit?
a) Lock
mm range

b) Input range

c) Feedback loop range

d) Capture range
Answer: a

39. In dual slope ADC, how the time period is converted into digital output?
a) Digital output = (counts/second) t;

b) Digital output = (counts/second)

Vi
c) Digital output = (counts/second)RC
d) Digital output = (counts/second) t2
Answer: d
T

40. In PLL. the capture range is always the lock range.

a) Greater than

b) Equal to
c) Less than

d) Greater than or equal to

Answer: ¢

41. Name the modulation technique in which the carrier frequency is shifted between two fixed

frequencies.
a) ASK IT

b) AM
c) FM
d) FSK
Answer: d
 42. Define the range of frequencies over which the PLL can maimtain lock with the incoming signal.
a) Free-running state
b) Pull-in time
c) Lock-in range
d) Capture range
Answer: c

43_ The total time taken by the PLL to establish lock 15 called

a) Pull-in time
b) Transit time
c) Free running time
d) Capture time

Answer: a
44. What could be the output voltage of phase detector?

a) Phase voltage
b) Free running voltage

c) Error voltage
d) None of the mentioned.
Answer: c

45. What is the function of low_pass filter in phase-locked loop?

a) Improves low frequency noise

b) Removes high frequency noise

c) Tracks the voltage changes
d) Changes the input frequency.

Answer: b

46. Which among the following has better capture tracking & locking characteristics?
a) XOR phase detector
b) Edge triggered phase detector
c) Analog phase detector
d) All of the mentioned
Answer: b

47. The frequency corresponding to logic 1 state in FSK is called

a) Space frequency

») Mark frequency
c) Both mark and space frequency
d) high frequency
Answer: b I
 48. In PLL. the capture range is always the lock range.

a) Greater than
b) Equal to
c) Less than
d) Greater
than or equal to
Answer. ¢
49. The conversion ratio of the phase detector for IC 565 VCO.
a) K,e=14/a
b) Ke=04n

c) Ke= 14a
d) Ky=24/n
Answer: a

cuPYS. a
50. Name the modulation technique in which the carrier frequency is shifted between two fixed
frequencies.
a) ASK
b) AM
c) FM
d) FSK
Answer: d
$1. The drawback
of varible transconductance multiplier is

a) temperature dependent
b) low resolution
c) low speed
d) low accuracy

Answer: a

52. At which state the phase-locked loop tracks any change in input frequency?
a) Free running state
b) Capture state
c) Phase locked state
d) Lock in range.
Answer: ¢
1. Calculate the voltage to frequency conversion factor, where £=155Hz and V.=10V.
a) 130
b) 124
c) 134
d) 116
Answer: b
2. Give the expression for the VCO free running frequency
a) fo=0.25/RrCr
b) fg =0.25/Rr
c) fo=0:5/RrCr
d) fg=0.25/Cr
Answer a

3. Determine output voltage of analog multiplier provided with two input signal Vy and Vy.

a) Vo= (Wa Na)! Vy

b)Vo= (Mis =¥x) (Mie

c) Vo=
(Vu, *V) / Va
d) Vo= (a. *V5) / Var?
Answer.b

4. Calculate the value of external timing capacitor, if no modulating imput signal is applied to VCO.
Consider f,=25 kHz and Rr=5 kQ.
a) 6nF
b) 100uF
c) 2nF
d) 10nF
Answer: c

a) Ve(max) ==Kex a -
b) Ve(max) == Bs w2
c) Ve(max) =+ 2Kox

d)Ve(max) = + Ke
Answer: b
 + sere

6. If the average error voltage & the phase shift are given as 6.2v & m/4. Determine the phase angle to
voltage transfer coefficient of full wave switching phase detector.
a) -0.19
b) -0.09
c) -0.03
d) -0.13
Answer: d
7. Determine the value of current flow in VCO, when the NE366 VCO external timing resistor
RT =250Q and the modulating input voltage Ve=3.25V.(Assume Vec=+5v).
a) 3mA
b) 12mA
c) 7mA

d) 10mA
Answer: ¢

8. Given the DC output voltage versus phase difference 9 curve. Find the conversion gain values
DC putput voltage

Sv
'
|
S/av |
|
\
|

n
Phase emiinitssn Q

a) 15.7V/rad
b) 1.26V/rad
c) 1.59V/rad

d) O.8V/rad
Answer: c
21. A dual slope has the following specifications,
16bit counter, Clock rate =4 MHz: faput voltage=12v; Output voltage =7v and
Capacitor=0.47 pF.
If the counters have cycled through 2n counts, determine the value of resistor in the
integrator.
a) 60k
b) 50kO!
c) 120k
d) 100Ke
Answer: a

Explanation: Time period of the dual slope integrator,

A(t) =t-t, =2°counts/clock rate =2"/4Mhz=16.38ms.
For integration,
AV.=(-1/RC)*V( t-t)
=> RC = -(12v/-7v) x16.38ms=28 08ms
« R= 28.08ms =59744 =60k0.

22. Find the output voltage equation of inverted voltage mode R- 2R ladder type
converter.
a) [1+ (RR)
b) [1- RyYRD]Vs
c) (RYRi)Vs
d) [I+ (RYRDJVs
Answer: d

16. An 8-bit successive approximation ADC ts driven by 1MHz clock. Find its
conversion time
a) 2 us
b) 8 ps
¢) 7 us
d)9 ps
Answer: d

17. The digital mput for 4-bit DAC 1s 0110, calculate its final output voltage if Ves =15v
a) 10v
b) 12v
c) 6v
d) Sv I
Answer: ¢
18. The basic step ofa 8-bit DAC ts 12 4mv_If the binary input 00000000 represents Ov.
Determine the output, if the inputts 101101111?
a) 1.36v
b) 2.27v
ce) 5.45v
d) 3.27v

Answer: b
19. At what condition the digital * analog conversion 1s made?

a)Ma> Na
b) Mas Me
c) N32 Na
d) Va=Na
Answer: a

20. A 12 bit dual ramp generation has a maximum output voltage of +12v. Compute the
equivalent digital number for the analog signal of +6v
a) 1000000000
b) 10000000000
c) 1000000000000
d) 100000000000
Answer: d

N= 2"x(6/12v) = 4096x0.5 =2048

Binary equivalent for 2048 => 100000000000.
ee

21. Determine the Full scale output in a 8-bit DAC for 0-15v range?
a) Full scale outpur=15.1v
 b) Full scale output=15.2v
c) Full scale output=14.5v
d) Full scale output=14.94y

Answer: d
22. For a particular 8-bit ADC, the conversion time is 9 us, what is the maximum
frequency of input sine wave that can be digitized.
a) 8SHz

b) 69Hz
c) 100Hz

d) 9SHz
Answer: b

23. Calculate the conversion time of a 12-bit counter type ADC with 1MHz clock
frequent to convert a full scale input?
a) 4.095 us
b) 4.095ms I
c) 4.095s
d) 6.095s
Answer: b

. Which type of ADC follow the conversion techmque of changing the analog mput
iT

signal to a lear function of frequency?

a) Dect type ADC

b) Integrating type ADC
c) Both integrating and direct type ADC
d) Flash type ADC.
Answer: b

Point out the control lines used for ADC conversion.

a) START. EOC
b) START, STOP
c) MAIN, END
d) ASSIGN, EOC
Answer: a
7. How many clock pulses do a 8- bit successive approximation converter requires for
obtaining a digital output? I
a) Twelve
b) Six
c) Eight
d) seven
Answer ¢
4. Name the curcuit that umprowes the accuracy of ADC conversion?

a) PLL circuit
b) Sample and Hold circuit.
c) Integrator circuut.
d) Low pass filter.
Answer: b

2. In a D-A converter with binary weighted resistor, a desired step size can be obtained
by
a) Selecting proper value of Vrs
b) Selecting proper value of R
c) Selecting proper value of Rr
d) Selecting proper value of Vyef
Answer: ¢
What is the disadvantage of binary weighted type DAC?
a) Require wide range of resistors

b) High operating frequency

c) High power consumption
d) Slow switching
Answer: a

Why the switches used in weighted resistor DAC are of single pole double throw
(SPDT) type?
a) To connect the resistance to reference voltage
b) To connect the resistance to ground
¢) To connect the resistance to either reference voltage or ground
d) To connect the resistance to output
Answer: c.

2. In a D-A converter with binary weighted resistor, a desired step size can be obtained.
by
a) Selecting proper value of Vrs
b) Selecting proper value of R
¢) Selecting proper value of Ry
d) Selecting proper value of Vye¢
Answer c
14. The maximum deviation between actual and ideal converter output after the removal
of error is
a) Absolute accuracy
b) Relative accuracy
c) Relative /absolute accuracy
d) Linearity
Answer: b

15. Accuracy of DAC should be

l=

a) = (1/2) of its MSB

b) + (1/2) of its LSB
c) Greater than or equal to (1/2)LSB
d) + (1/2) of its LSB
Answer: d
6. Which of the following represents over sampling DAC?

a) PWM DAC
b) Delta-sigma DAC
c) Binary weighted DAC
d) Switched resistor DAC
Answer: b

7. InDAC, is the smallest analog output change that can occur as a result of an
increment
in the digital input.

a) Monotomerty
b) Resolution
c) Sampling rate
d) Dynamucity
Answer: b

§. Inthe sample and hold circuit, the period during which the voltage across capacitor is
equal to mput voltage

a) Sample period
b) Hold period
c) Delay period
d) Charging period

Answer:a

9. The primary disadvantage of the flash analog-to digital converter (ADC) is that

a) it requires the input voltage to be applied to the inputs simultancously

b) along conversion tume 1s required
c) large number of output lines is required to simultaneously decode the input

voltage
d) large number of comparators 1s required to represent a reasonable sized binary

number
Answer: d
10. is the serious problem in R-2R ladder type DAC
a) more number of resisters required
b) Wide range of resistors value

c) Low resolution
d) Non-hnearity
Answer: d

11. How many equal intervals are present m a 14-bit D-A converter?
a) 16383
b) 4095
¢) 65535
d) 1023
Answer: a