Scribd
Upload
21 views2 pages

Assignment - II: Udayapura, Kanakapura Road, Bengaluru-560082, Karnataka

This document contains an assignment on advanced computer architecture from Dayananda Sagar Academy of Technology and Management. The assignment covers topics such as pipelined execution, scalar and superscalar processor architectures, processor design space, caching techniques, bus protocols, memory interleaving, pipelined memory access, synchronous and asynchronous pipelines, dynamic instruction scheduling, branch prediction, adder architectures, and multiprocessor interconnection structures. Students are asked to explain these concepts through diagrams and definitions.

Uploaded by

ashi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
21 views2 pages

Assignment - II: Udayapura, Kanakapura Road, Bengaluru-560082, Karnataka

This document contains an assignment on advanced computer architecture from Dayananda Sagar Academy of Technology and Management. The assignment covers topics such as pipelined execution, scalar and superscalar processor architectures, processor design space, caching techniques, bus protocols, memory interleaving, pipelined memory access, synchronous and asynchronous pipelines, dynamic instruction scheduling, branch prediction, adder architectures, and multiprocessor interconnection structures. Students are asked to explain these concepts through diagrams and definitions.

Uploaded by

ashi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

DAYANANDA SAGAR ACADEMY OF TECHNOLOGY AND MANAGEMENT

Udayapura, Kanakapura Road, Bengaluru- 560082, Karnataka.


(Affiliated to VTU, Approved by AICTE)

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING


(Accredited by NBA for 3 years (26-7-18 to 30-6-2021), NewDelhi)

Semester VII (CSE) Subject Title Advanced Computer Architecture


Subject Code 15CS72 Name of the Faculty Ms. Shylaja B

Course Outcomes:
CO2: Understand the hardware technologies
CO3: Compare and contrast the parallel architectures

Assignment –II
Note: (RS – Revised Syllabus)
1a. With diagrams, explain the pipelined execution of successive instructions in a base scalar processor
and in two under pipelined cases. (4M, RS, CO2)

b. Explain the architectural models of a basic scalar computer system using block diagrams.(4M, RS, CO2)

2a. Describe the structure of a superscalar pipeline with the help of a diagram. (4M, RS, CO2)

b. Draw and explain the block diagram of a typical superscalar RISC processor architecture consisting of
an integer unit and a floating-point unit. (4M, RS, CO2)

3a. Define the following basic terms related to modern processor technology. (4M, RS, CO2)

a) Processor Design Space


b) Instruction Issue latency
c) Instruction Issue Rate
d) Simple Operation Latency
e) Resource Conflicts
f) Processor versus coprocessor
g) General Purpose Registers
h) Addressing Modes
i) Unified versus Split Caches
j) Hardwired versus microcoded control
b. With the help of a diagram, explain the backplane buses, system interfaces and slot connections to
various functional boards in a multiprocessor system. (4M, RS, CO2)
4a. Discuss the typical time sequence for information transfer between a master and a slave over a system
bus. (4M, RS, CO2)

b. Differentiate between synchronous and asynchronous bus timing protocols. (4M, RS, CO2)

5a. Explain the 2 interleaved memory organizations with m=2a modules and w=2b words per module.
(4M, RS, CO2)
b. With diagrams, explain the eight-way low-order interleaving and pipelined access of eight
consecutive words in a C-access memory. (4M, RS, CO2)

6a. Explain an asynchronous pipeline model, a synchronous pipeline model and reservation table of a
four-stage linear pipeline with appropriate diagrams. (4M, RS, CO3)

b. Define the following terms with regard to clocking and timing control.
i) Clock cycle and throughput ii) Clock skewing iii) Speedup factor (4M, RS, CO3)

7a. Describe the speedup factors and the optimal number of pipeline stages for a linear pipeline unit.
(4M, RS, CO3)
b. Explain the features of non-linear pipeline processors with feed forward and feed backward
connections. (4M, RS, CO3)

8a. Explain Tomasulo’s algorithm for dynamic instruction scheduling.


(4 marks June 2012, Dec 2012/13/14, June 2015, Jan 2016, CO3)
b. With diagrams, explain branch history buffer and a state transition diagram used in dynamic branch
prediction. (4M, RS, CO3)

9a. Differentiate between a carry-propagate adder (CPA) and a carry save adder. (4M, RS, CO3)

b.With diagram, explain the interconnection structures in a generalized multiprocessor system with local
memory, private caches, shared memory and shared peripherals. (4M, RS, CO3)

10a. Explain the bus systems at board level, backplane level and I/O level. (4M, RS, CO3)

b. Explain the hierarchical cache/bus architecture for designing a scalable multiprocessor. (4M, RS, CO3)
***************************

You might also like