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Experiment - 1 DC Analysis of NMOS Transistor Circuit Diagram

The document describes an experiment to perform DC analysis of an NMOS transistor. The circuit diagram shows an NMOS transistor with drain connected to node 3, gate to node 1, and source to node 2. SPICE code is provided for the DC analysis, sweeping the drain-source voltage from 0-5V and gate-source voltage from 0-5V in steps. The output will be a plot of the drain current versus the varying voltages.

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shubham kumar mishra
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111 views3 pages

Experiment - 1 DC Analysis of NMOS Transistor Circuit Diagram

The document describes an experiment to perform DC analysis of an NMOS transistor. The circuit diagram shows an NMOS transistor with drain connected to node 3, gate to node 1, and source to node 2. SPICE code is provided for the DC analysis, sweeping the drain-source voltage from 0-5V and gate-source voltage from 0-5V in steps. The output will be a plot of the drain current versus the varying voltages.

Uploaded by

shubham kumar mishra
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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EXPERIMENT -1

DC analysis of NMOS Transistor

CIRCUIT DIAGRAM:

*Spice Code for DC analysis of NMOS Transistor

.include "D:\sudama\soonu\layout\tspice\models\ml5_20.md"

M1 3 1 2 2 NMOS L=2u W=6u AD=42p PD=26u AS=42p PS=26u


* M1 DRAIN GATE SOURCE BULK (20 22 22 28)

vds 3 2 dc 5v
vgs 1 2 dc 5v
.dc vds 0 5 0.1v vgs 0 5 1v
.print id(M1)
.END
LAYOUT OF NMOS
Waveform OF NMOS

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