Digital Design & Computer Arch.

Lecture 6: Sequential Logic Design

Prof. Onur Mutlu

ETH Zürich
Spring 2020
6 March 2020
We Are Almost Done with This
n Building blocks of modern computers
q Transistors
q Logic gates

n Combinational circuits

n Boolean algebra

n How to use Boolean algebra to represent combinational

circuits

n Minimizing logic circuits

2
Agenda for Today and Next Week
n Today

q Wrap up Combinational Logic and Circuit Minimization

q Start (and finish) Sequential Logic

n Next week

q Hardware Description Languages and Verilog

n Combinational Logic
n Sequential Logic

q Timing and Verification

3
Assignment: Required Lecture Video
n Why study computer architecture?
n Why is it important?
n Future Computing Architectures

n Required Assignment
q Watch Prof. Mutlu’s inaugural lecture at ETH and understand it
q https://www.youtube.com/watch?v=kgiZlSOcGFM

n Optional Assignment – for 1% extra credit

q Write a 1-page summary of the lecture and email us
n What are your key takeaways?
n What did you learn?
n What did you like or dislike?
n Submit your summary to Moodle – Deadline: April 1
4
Extra Assignment: Moore’s Law (I)
n Paper review
n G.E. Moore. "Cramming more components onto integrated
circuits," Electronics magazine, 1965

n Optional Assignment – for 1% extra credit

q Write a 1-page review
q Upload PDF file to Moodle – Deadline: April 1

n I strongly recommend that you follow my guidelines for

(paper) review (see next slide)

5
Extra Assignment 2: Moore’s Law (II)
n Guidelines on how to review papers critically

q Guideline slides: pdf ppt

q Video: https://www.youtube.com/watch?v=tOL6FANAJ8c

q Example reviews on “Main Memory Scaling: Challenges and

Solution Directions” (link to the paper)
n Review 1
n Review 2

q Example review on “Staged memory scheduling: Achieving

high performance and scalability in heterogeneous
systems” (link to the paper)
n Review 1
6
Assignment: Required Readings
n Combinational Logic
q P&P Chapter 3 until 3.3 + H&H Chapter 2
n Sequential Logic
q P&P Chapter 3.4 until end + H&H Chapter 3 in full
n Hardware Description Languages and Verilog
q H&H Chapter 4 in full
n Timing and Verification
q H&H Chapters 2.9 and 3.5 + (start Chapter 5)

n By the end of next week, make sure you are done with
q P&P Chapters 1-3 + H&H Chapters 1-4

7
Wrap-Up Combinational Logic
Circuits and Design

8
Recall: Tri-State Buffer
n A tri-state buffer enables gating of different signals onto a
wire

n Floating signal (Z): Signal that is not driven by any circuit

q Open circuit, floating wire

9
Recall: Example: Use of Tri-State Buffers
n Imagine a wire connecting the CPU and memory

q At any time only the CPU or the memory can place a value on
the wire, both not both

q You can have two tri-state buffers: one driven by CPU, the
other memory; and ensure at most one is enabled at any time

10
Recall: Example Design with Tri-State Buffers

GateCPU

CPU

GateMem

Memory
Shared Bus

11
Recall: Another Example

12
Multiplexer Using Tri-State Buffers

13
Aside: Logic Using Multiplexers
n Multiplexers can be used as lookup tables to perform logic
functions

14
Aside: Logic Using Multiplexers (II)
n Multiplexers can be used as lookup tables to perform logic
functions

15
Aside: Logic Using Multiplexers (III)
n Multiplexers can be used as lookup tables to perform logic
functions

Read H&H Chapter 2.8 16

Aside: Logic Using Decoders (I)
n Decoders can be combined with OR gates to build logic
functions.

Read H&H Chapter 2.8 17

Logic Simplification using
Boolean Algebra Rules

18
Recall: Full Adder in SOP Form Logic

Full Adder
ai

bi
ci+1 ai bi carryi carryi+1 Si
ci
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
si 0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

19
Goal: Simplified Full Adder

How do we simplify Boolean logic?

20
Quick Recap on Logic Simplification
n The original Boolean expression (i.e., logic circuit) may not
be optimal

F = ~A(A + B) + (B + AA)(A + ~B)

n Can we reduce a given Boolean expression to an equivalent

expression with fewer terms?

F=A+B

n The goal of logic simplification:

q Reduce the number of gates/inputs
q Reduce implementation cost

A basis for what the automated design tools are doing today
21
Logic Simplification
n Systematic techniques for simplifications
q amenable to automation
$ + 𝑨𝑩
Key Tool: The Uniting Theorem — 𝑭 = 𝑨𝑩

𝑭= $ + 𝑨𝑩 = 𝑨 𝑩
𝑨𝑩 $ +𝑩 =𝑨 𝟏 =𝑨

B's value changes within the rows where F==1 (“ON set”)
Essence of Simplification:
Find two elementA's subsets
value doesof
NOT
thechange within
ON-set the ON-set
where onlyrows
one variable
changes its value.
If anThis
inputsingle
(B) can varying variable
change without can the
changing be output,
eliminated!
that input
value is not needed
➙ B is eliminated, A remains

$𝑩
𝑮= 𝑨 $ + 𝑨𝑩 $+𝑨 𝑩
$= 𝑨 $=𝑩
$

B's value stays the same within the ON-set rows

A's value changes within the ON-set rows

➙ A is eliminated, B remains
22
Logic Simplification:
Karnaugh Maps (K-Maps)

23
Karnaugh Maps are Fun…
n A pictorial way of minimizing circuits by visualizing
opportunities for simplification
n They are for you to study on your own…

n See Backup Slides

n Read H&H Section 2.7
n Watch videos of Lectures 5 and 6 from 2019 Digitech
course:
q https://youtu.be/0ks0PeaOUjE?list=PL5Q2soXY2Zi8J58xLKBNF
QFHRO3GrXxA9&t=4570
q https://youtu.be/ozs18ARNG6s?list=PL5Q2soXY2Zi8J58xLKBN
FQFHRO3GrXxA9&t=220

24
Sequential Logic Circuits and
Design

25
What We Will Learn Today
n Circuits that can store information
q Cross-coupled inverter
q R-S Latch
q Gated D Latch
q D Flip-Flop
q Register

n Finite State Machines (FSM)

q Moore Machine
q Mealy Machine

n Verilog implementations of sequential circuits (next week)

26
Circuits that Can
Store Information

27
Introduction
n Combinational circuit output depends only on current input
n We want circuits that produce output depending on
current and past input values – circuits with memory
n How can we design a circuit that stores information?

Sequential Circuit

outputs
inputs

Combinational
Circuit

Storage
Element

28
Capturing Data

29
Basic Element: Cross-Coupled Inverters

n Has two stable states: Q=1 or Q=0.

n Has a third possible “metastable” state with both outputs
oscillating between 0 and 1 (we will see this later)
n Not useful without a control mechanism for setting Q
Image source: Harris and Harris, Digital Design and Computer Architecture, 2nd Ed., p.110. 30
More Realistic Storage Elements
n Have a control mechanism for setting Q
q We will see the R-S latch soon
q Let’s look at an SRAM (static random access memory) cell first

bitline bitline
wordline

SRAM cell
n We will get back to SRAM (and DRAM) later
31
The Big Picture: Storage Elements
n Latches and Flip-Flops
q Very fast, parallel access
q Very expensive (one bit costs tens of transistors)

n Static RAM (SRAM)

q Relatively fast, only one data word at a time
q Expensive (one bit costs 6+ transistors)

n Dynamic RAM (DRAM)

q Slower, one data word at a time, reading destroys content
(refresh), needs special process for manufacturing
q Cheap (one bit costs only one transistor plus one capacitor)

n Other storage technology (flash memory, hard disk, tape)

q Much slower, access takes a long time, non-volatile
q Very cheap
Basic Storage Element:
The R-S Latch

33
The R-S (Reset-Set) Latch
n Cross-coupled NAND gates
q Data is stored at Q (inverse at Q’)
q S and R are control inputs
n In quiescent (idle) state, both S and R are held at 1

n S (set): drive S to 0 (keeping R at 1) to change Q to 1

n R (reset): drive R to 0 (keeping S at 1) to change Q to 0
n S and R should never both be 0 at the same time

S Q
Input Output
R S Q
1 1 Qprev
1 0 1
0 1 0
R Q’ 0 0 Forbidden

34
Why not R=S=0?
S
1
0 Q
Input Output

1
0 R S Q
1 1 Qprev
1 0 1
1
0 0 1 0
R Q’ 0 0 Forbidden
1
0
1. If R=S=0, Q and Q’ will both settle to 1, which breaks
our invariant that Q = !Q’
2. If S and R transition back to 1 at the same time, Q and Q’
begin to oscillate between 1 and 0 because their final
values depend on each other (metastability)
q This eventually settles depending on variation in the
circuits (more metastability to come in Lecture 8)
35
The Gated D Latch

36
The Gated D Latch
n How do we guarantee correct operation of an R-S Latch?

S Q

Q’
R

37
The Gated D Latch
n How do we guarantee correct operation of an R-S Latch?
q Add two more NAND gates!

D S Q

Write
Enable

Q’
R

q Q takes the value of D, when write enable (WE) is set to 1

q S and R can never be 0 at the same time!

38
The Gated D Latch

D S
Q

Write
Enable

Q’
R
Input Output
WE D Q
0 0 Qprev
0 1 Qprev
1 0 0
1 1 1

39
The Register

40
The Register
How can we use D latches to store more data?
• Use more D latches!
• A single WE signal for all latches for
simultaneous writes Here we have a
register, or a
D3 D2 D1 D0
structure that
stores more than
Write
Enable
one bit and can be
read from and
written to

This register holds

4 bits, and its data
Q3 Q2 Q1 Q0 is referenced as
Q[3:0]
41
The Register
How can we use D latches to store more data?
• Use more D latches!
• A single WE signal for all latches for
simultaneous writes Here we have a
register, or a
D3:0
structure that
4 stores more than
one bit and can be
read from and
WE Register x (Rx) written to

This register holds

4 4 bits, and its data
is referenced as
Q3:0
Q[3:0]
42
Memory

43
Memory
n Memory is comprised of locations that can be written to or
read from. An example memory array with 4 locations:

Addr(00): 0100 1001 Addr(01): 0100 1011

Addr(10): 0010 0010 Addr(11): 1100 1001

n Every unique location in memory is indexed with a unique

address. 4 locations require 2 address bits
(log[#locations]).
n Addressability: the number of bits of information stored
in each location. This example: addressability is 8 bits.
n The entire set of unique locations in memory is referred to
as the address space.
n Typical memory is MUCH larger (billions of locations)
44
Addressing Memory
Let’s implement a simple memory array with:
• 3-bit addressability & address space size of 2 (total of 6 bits)
1 Bit
D Q
WE

6-Bit Memory Array

Addr(0) Bit2 Bit1 Bit0

Addr(1) Bit2 Bit1 Bit0

45
Reading from Memory
How can we select the address to read?
• Because there are 2 addresses, address size is log(2)=1 bit

46
Reading from Memory
How can we select an address to read?
• Because there are 2 addresses, address size is log(2)=1 bit
Addr[0]

Wordline

D[2] D[1] D[0]

47
Reading from Memory
How can we select an address to read?
• Because there are 2 addresses, address size is log(2)=1 bit
Addr[0]

Wordline

Address Decoder

D[2] D[1] D[0]

48
Reading from Memory
How can we select an address to read?
• Because there are 2 addresses, address size is log(2)=1 bit
Addr[0]

Wordline

Address Decoder

D[2] D[1] D[0]

Multiplexer

49
Writing to Memory
How can we select an address and write to it?

50
Writing to Memory
How can we select an address and write to it?
• Input is indicated with Di
Addr[0]
Di[2] Di[1] Di[0]
WE

51
Putting it all Together
Let’s enable reading and writing to a memory array

Addr[0]
Di[2] Di[1] Di[0]
WE

D[2] D[1] D[0]

52
 A Bigger Memory Array
Addr[1:0]
Di[2] Di[1] Di[0]
WE

D[2] D[1] D[0]

53
 A Bigger Memory Array
Addr[1:0]
Di[2] Di[1] Di[0]
WE

Address Decoder

Multiplexer D[2] D[1] D[0]

54
Sequential Logic Circuits

55
Sequential Logic Circuits
n We have looked at designs of circuit elements that can
store information
n Now, we will use these elements to build circuits that
remember past inputs

Combinational Sequential
Only depends on current inputs Opens depending on past inputs
https://www.easykeys.com/228_ESP_Combination_Lock.aspx
https://www.fosmon.com/product/tsa-approved-lock-4-dial-combo 56
State
n In order for this lock to work, it has to keep track
(remember) of the past events!
n If passcode is R13-L22-R3, sequence of states to unlock:
A. The lock is not open (locked), and no relevant operations have
been performed
B. Locked but user has completed R13
C. Locked but user has completed R13-L22
D. Unlocked: user has completed R13-L22-R3

n The state of a system is a snapshot of all relevant

elements of the system at the moment of the snapshot
q To open the lock, states A-D must be completed in order
q If anything else happens (e.g., L5), lock returns to state A

57
State Diagram of Our Sequential Lock
n Completely describes the operation of the sequential lock

n We will understand “state diagrams” fully later today

Image source: Patt and Patel, “Introduction to Computing Systems”, 2nd ed., page 76. 58
Another Simple Example of State
n A standard Swiss traffic light has 4 states
A. Green
B. Yellow
C. Red
D. Red and Yellow

n The sequence of these states are always as follows

A B C D

59
Changing State: The Notion of Clock (I)

A B C D

n When should the light change from one state to another?

n We need a clock to dictate when to change state
q Clock signal alternates between 0 & 1
1
CLK:
0

n At the start of a clock cycle ( ), system state changes

q During a clock cycle, the state stays constant
q In this traffic light example, we are assuming the traffic light stays in
each state an equal amount of time
60
Changing State: The Notion of Clock (II)
n Clock is a general mechanism that triggers transition from
one state to another in a sequential circuit

n Clock synchronizes state changes across many sequential

circuit elements

n Combinational logic evaluates for the length of the clock

cycle

n Clock cycle should be chosen to accommodate maximum

combinational circuit delay
q More on this later, when we discuss timing

61
Finite State Machines

62
Finite State Machines
n What is a Finite State Machine (FSM)?
q A discrete-time model of a stateful system
q Each state represents a snapshot of the system at a given time

n An FSM pictorially shows

1. the set of all possible states that a system can be in
2. how the system transitions from one state to another

n An FSM can model

q A traffic light, an elevator, fan speed, a microprocessor, etc.

n An FSM enables us to pictorially think of a stateful

system using simple diagrams
63
Finite State Machines (FSMs) Consist of:
n Five elements:
1. A finite number of states
n State: snapshot of all relevant elements of the
system at the time of the snapshot
2. A finite number of external inputs
3. A finite number of external outputs
4. An explicit specification of all state transitions
n How to get from one state to another
5. An explicit specification of what determines
each external output value

64
Finite State Machines (FSMs)
n Each FSM consists of three separate parts:
q next state logic
q state register
q output logic

CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

state register

At the beginning of the clock cycle, next state is latched into the state register

65
Finite State Machines (FSMs) Consist of:
n Sequential circuits CLK

q State register(s)
n Store the current state and S’ S
Next Current
n Load the next state at the clock edge State State

n Combinational Circuits Next State

Logic
q Next state logic
n Determines what the next state will be CL Next
State

Output
q Output logic Logic
n Generates the outputs
CL Outputs

66
Finite State Machines (FSMs) Consist of:
n Sequential circuits CLK

q State register(s)
n Store the current state and S’ S
Next Current
n Load the next state at the clock edge State State

n Combinational Circuits Next State

Logic
q Next state logic
n Determines what the next state will be CL Next
State

Output
q Output logic Logic
n Generates the outputs
CL Outputs

67
State Register Implementation
n How can we implement a state register? Two properties:
1. We need to store data at the beginning of every clock cycle

2. The data must be available during the entire clock cycle

1
CLK:
0

Register
Input:

Register Desired behavior

Output:

68
The Problem with Latches
Recall the D Q
Gated D Latch
CLK = WE

n Currently, we cannot simply wire a clock to WE of a latch

q Whenever the clock is high, the latch propagates D to Q
q The latch is transparent

1
CLK:
0

Register
Input:

Register
Output:

69
The Problem with Latches
Recall the D Q
Gated D Latch
CLK = WE

n Currently, we cannot simply wire a clock to WE of a latch

q Whenever the clock is high, the latch propagates D to Q
q The latch is transparent

1
CLK:
0

Register
Input:

Register
Output:
Undesirable!
70
The Problem with Latches
Recall the D Q
Gated D Latch
CLK = WE

n Currently, we cannot simply wire a clock to WE of a latch

q When the clock is high Q will not take on D’s value AND
q Howthe
When can weis change
clock thewilllatch,
low the latch soDthat
propagate to Q

1
1) D (input) is observable at Q (output)
CLK:
0

only
Input:
at the beginning of next clock cycle?

2) Q is available for the full clock cycle

Output:

71
The Need for a New Storage Element
n To design viable FSMs

n We need storage elements that allow us

q to read the current state throughout the current clock

cycle

AND

q not write the next state values into the storage elements
until the beginning of the next clock cycle.

72
 The D Flip-Flop
n 1) state change on clock edge, 2) data available for full cycle

D Latch (Master)
D D Latch (Slave)

CLK
1
CLK:
0
n When the clock is low, master propagates D to the input of slave (Q unchanged)
n Only when the clock is high, slave latches D (Q stores D)
q At the rising edge of clock (clock going from 0->1), Q gets assigned D
73
The D Flip-Flop
n 1) state change on clock edge, 2) data available for full cycle

D CLK Q

__
Q
D Flip-Flop

1
CLK:
0

n At the rising edge of clock (clock going from 0->1), Q gets assigned D
n At all other times, Q is unchanged

74
The D Flip-Flop
n How do we implement this?

D CLK Q

__
Q
We can useD Flip-Flop
these Flip-Flops
to implement the state register!
1
CLK:
0
n At the rising edge of clock (clock going from 0->1), Q gets assigned D
n At all other times, Q is unchanged

75
Rising-Clock-Edge Triggered Flip-Flop
n Two inputs: CLK, D

D Flip-Flop
n Function CLKSymbols
q The flip-flop “samples” D on the rising edge
of CLK (positive edge)
D Q
q When CLK rises from 0 to 1, D passes
Q
through to Q
q Otherwise, Q holds its previous value

q Q changes only on the rising edge of CLK

n A flip-flop is called an edge-triggered state element

because it captures data on the clock edge
q A latch is a level-triggered state element
76
Register
n Multiple parallel flip-flops, each of which storing 1 bit
CLK

Con
D0 D Q Q0 d ens
ed CLK
D1 D Q Q1
4 4
D3:0 Q3:0
D2 D Q Q2

This line represents 4 wires

D3 D Q Q3
This register stores 4 bits

77
A 4-Bit D-Flip-Flop-Based Register (Internally)

Image source: Patt and Patel, “Introduction to Computing Systems”, 3rd ed., tentative page 95. 78
Finite State Machines (FSMs)
n Next state is determined by the current state and the inputs
n Two types of finite state machines differ in the output
logic:
q Moore FSM: outputs depend only on the current state

Moore FSM

CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

79
Finite State Machines (FSMs)
n Next state is determined by the current state and the inputs
n Two types of finite state machines differ in the output
logic:
q Moore FSM: outputs depend only on the current state
q Mealy FSM: outputs depend on the current state and the
inputs Moore FSM

CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

80
Finite State Machine Example
n “Smart” traffic light controller
q 2 inputs:
n Traffic sensors: TA , TB (TRUE when there’s traffic)
q 2 outputs:
n Lights: LA , LB (Red, Yellow, Green)

Bravado
q State can change every 5 seconds Dining
Hall
n Except if green and traffic, stay green
LB

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms

Blvd.
From H&H Section 3.4.1 Fields
81
Finite State Machine Black Box
n Inputs: CLK, Reset, TA , TB
n Outputs: LA , LB
CLK

TA Traffic LA
Light
TB Controller LB

Reset

82
Finite State Machine Transition Diagram
n Moore FSM: outputs labeled in each state
q States: Circles
q Transitions: Arcs

Reset
Bravado

Dining S0
Hall LA: green
LB LB: red

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms
Blvd.

Fields
83
Finite State Machine Transition Diagram
n Moore FSM: outputs labeled in each state
q States: Circles
q Transitions: Arcs

TA
Reset
Bravado

Dining S0 TA S1
Hall LA: green LA: yellow
LB LB: red LB: red

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms S3 S2
LA: red LA: red
LB: yellow LB: green
Blvd.

TB
Fields TB

84
Finite State Machine Transition Diagram
n Moore FSM: outputs labeled in each state
q States: Circles
q Transitions: Arcs

TA
Reset
Bravado

Dining S0 TA S1
Hall LA: green LA: yellow
LB LB: red LB: red

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms S3 S2
LA: red LA: red
LB: yellow LB: green
Blvd.

TB
Fields TB

85
Finite State Machine Transition Diagram
n Moore FSM: outputs labeled in each state
q States: Circles
q Transitions: Arcs

TA
Reset
Bravado

Dining S0 TA S1
Hall LA: green LA: yellow
LB LB: red LB: red

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms S3 S2
LA: red LA: red
LB: yellow LB: green
Blvd.

TB
Fields TB

86
Finite State Machine Transition Diagram
n Moore FSM: outputs labeled in each state
q States: Circles
q Transitions: Arcs

TA
Reset
Bravado

Dining S0 TA S1
Hall LA: green LA: yellow
LB LB: red LB: red

LA TB
LA

Academic TA TA Ave.

Labs TB LB Dorms S3 S2
LA: red LA: red
LB: yellow LB: green
Blvd.

TB
Fields TB

87
Finite State Machine:
State Transition Table

88
FSM State Transition Table
Reset
TA Current State Inputs Next State
S0 TA S1 S TA TB S'
LA: green LA: yellow
LB: red LB: red
S0 0 X
S0 1 X
S1 X X
S2 X 0
S3 S2 S2 X 1
LA: red LA: red
LB: yellow LB: green S3 X X
TB
TB

59
FSM State Transition Table
Reset
TA Current State Inputs Next State
S0 TA S1 S TA TB S'
LA: green LA: yellow
LB: red LB: red
S0 0 X S1
S0 1 X S0
S1 X X S2
S2 X 0 S3
S3 S2 S2 X 1 S2
LA: red LA: red
LB: yellow LB: green S3 X X S0
TB
TB

60
FSM State Transition Table
Reset
TA Current State Inputs Next State
S0 TA S1 S TA TB S'
LA: green LA: yellow
LB: red LB: red
S0 0 X S1
S0 1 X S0
S1 X X S2
S2 X 0 S3
S3 S2 S2 X 1 S2
LA: red LA: red
LB: yellow LB: green S3 X X S0
TB
TB State Encoding
S0 00
S1 01
S2 10
S3 11
61
FSM State Transition Table
Reset
TA Current State Inputs Next State
S0 TA S1 S1 S0 TA TB S’1 S’0
LA: green LA: yellow
LB: red LB: red
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
S3 S2 1 0 X 1 1 0
LA: red LA: red
LB: yellow LB: green 1 1 X X 0 0
TB
TB State Encoding
S0 00
S1 01
S2 10
S3 11
62
FSM State Transition Table
Reset
TA Current State Inputs Next State
S0 TA S1 S1 S0 TA TB S’1 S’0
LA: green LA: yellow
LB: red LB: red
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
S3 S2 1 0 X 1 1 0
LA: red LA: red
LB: yellow LB: green 1 1 X X 0 0
TB
TB State Encoding
S0 00
S1 01
S’1 = ?
S2 10
S3 11
63
FSM State Transition Table
Reset
TA Current State Inputs Next State
S0 TA S1 S1 S0 TA TB S’1 S’0
LA: green LA: yellow
LB: red LB: red
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
S3 S2 1 0 X 1 1 0
LA: red LA: red
LB: yellow LB: green 1 1 X X 0 0
TB
TB State Encoding
S0 00
S1 01
S’1 = (S1 ∙ S0) + (S1 ∙ S0 ∙ TB) + (S1 ∙ S0 ∙ TB)
S2 10
S3 11
64
FSM State Transition Table
Reset
TA Current State Inputs Next State
S0 TA S1 S1 S0 TA TB S’1 S’0
LA: green LA: yellow
LB: red LB: red
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
S3 S2 1 0 X 1 1 0
LA: red LA: red
LB: yellow LB: green 1 1 X X 0 0
TB
TB State Encoding
S0 00
S1 01
S’1 = (S1 ∙ S0) + (S1 ∙ S0 ∙ TB) + (S1 ∙ S0 ∙ TB)
S2 10
S’0 = ? S3 11
65
FSM State Transition Table
Reset
TA Current State Inputs Next State
S0 TA S1 S1 S0 TA TB S’1 S’0
LA: green LA: yellow
LB: red LB: red
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
S3 S2 1 0 X 1 1 0
LA: red LA: red
LB: yellow LB: green 1 1 X X 0 0
TB
TB State Encoding
S0 00
S1 01
S’1 = (S1 ∙ S0) + (S1 ∙ S0 ∙ TB) + (S1 ∙ S0 ∙ TB)
S2 10
S’0 = (S1 ∙ S0 ∙ TA) + (S1 ∙ S0 ∙ TB) S3 11
66
FSM State Transition Table
Reset
TA Current State Inputs Next State
S0 TA S1 S1 S0 TA TB S’1 S’0
LA: green LA: yellow
LB: red LB: red
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
S3 S2 1 0 X 1 1 0
LA: red LA: red
LB: yellow LB: green 1 1 X X 0 0
TB
TB State Encoding
S0 00
S1 01
S’1 = S1 xor S0 (Simplified)
S2 10
S’0 = (S1 ∙ S0 ∙ TA) + (S1 ∙ S0 ∙ TB) S3 11
67
Finite State Machine:
Output Table

98
FSM Output Table
Reset
TA Current State Outputs
S0 TA S1 S1 S0 LA LB
LA: green LA: yellow
LB: red LB: red
0 0 green red
0 1 yellow red
1 0 red green
1 1 red yellow
S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB

69
FSM Output Table
Reset
TA Current State Outputs
S0 TA S1 S1 S0 LA LB
LA: green LA: yellow
LB: red LB: red
0 0 green red
0 1 yellow red
1 0 red green
1 1 red yellow
S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB Output Encoding
green 00
yellow 01
red 10

70
FSM Output Table
Reset
TA Current State Outputs
S0 TA S1 S1 S0 LA1 LA0 LB1 LB0
LA: green LA: yellow
LB: red LB: red
0 0 0 0 1 0
0 1 0 1 1 0
1 0 1 0 0 0
1 1 1 0 0 1
S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB Output Encoding
green 00
LA1 = S1
yellow 01
red 10

71
FSM Output Table
Reset
TA Current State Outputs
S0 TA S1 S1 S0 LA1 LA0 LB1 LB0
LA: green LA: yellow
LB: red LB: red
0 0 0 0 1 0
0 1 0 1 1 0
1 0 1 0 0 0
1 1 1 0 0 1
S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB Output Encoding
green 00
LA1 = S1
yellow 01
LA0 = S1 ∙ S0
red 10

72
FSM Output Table
Reset
TA Current State Outputs
S0 TA S1 S1 S0 LA1 LA0 LB1 LB0
LA: green LA: yellow
LB: red LB: red
0 0 0 0 1 0
0 1 0 1 1 0
1 0 1 0 0 0
1 1 1 0 0 1
S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB Output Encoding
green 00
LA1 = S1
yellow 01
LA0 = S1 ∙ S0
LB1 = S1 red 10

73
FSM Output Table
Reset
TA Current State Outputs
S0 TA S1 S1 S0 LA1 LA0 LB1 LB0
LA: green LA: yellow
LB: red LB: red
0 0 0 0 1 0
0 1 0 1 1 0
1 0 1 0 0 0
1 1 1 0 0 1
S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB Output Encoding
green 00
LA1 = S1
yellow 01
LA0 = S1 ∙ S0
LB1 = S1 red 10
LB0 = S1 ∙ S0
74
Digital Design & Computer Arch.
Lecture 6: Sequential Logic Design

Prof. Onur Mutlu

ETH Zürich
Spring 2020
6 March 2020
We did not cover the remaining slides.
They are for your preparation for the
next lecture.

106
Finite State Machine:
Schematic

107
FSM Schematic: State Register

108
FSM Schematic: State Register
CLK
S'1 S1

S'0 S0
r
Reset
state register

109
FSM Schematic: Next State Logic
CLK
S'1 S1

TA S'0 S0
r
TB Reset
S1 S0

inputs next state logic state register

S’1 = S1 xor S0

S’0 = (S1 ∙ S0 ∙ TA) + (S1 ∙ S0 ∙ TB)

110
FSM Schematic: Output Logic
CLK LA1
S'1 S1
LA0

TA S'0 S0
LB1
r
TB Reset
S1 S0 LB0

inputs next state logic state register output logic outputs

LA1 = S1
LA0 = S1 ∙ S0
LB1 = S1
LB0 = S1 ∙ S0
111
 FSM Timing Diagram Reset
S0
TA __
TA S1
LA: yellow LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)

112
 FSM Timing Diagram Reset
S0
TA __
TA S1
LA: yellow LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)

113
 FSM Timing Diagram Reset
S0
TA __
TA S1
LA: yellow LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)

114
 FSM Timing Diagram Reset
S0
TA __
TA S1
LA: yellow LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)

115
 FSM Timing Diagram Reset
S0
TA __
TA S1
LA: yellow LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)

116
 FSM Timing Diagram Reset
S0
TA __
TA S1
LA: yellow LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)

117
 FSM Timing Diagram Reset
S0
TA __
TA S1
LA: yellow LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)

118
 FSM Timing Diagram Reset
S0
TA __
TA S1
LA: yellow LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
This is from H&H Section 3.4.1 TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)

119
 FSM Timing Diagram Reset
S0
TA __
TA S1
LA: yellow LA: yellow
LB: red LB: red

S3 S2
LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)

120
 FSM Timing Diagram Reset
S0
TA __
TA S1
LA: yellow LA: yellow
LB: red LB: red

See H&H Chapter 3.4 S3 S2

LA: red LA: red
LB: yellow __ LB: green
TB
TB

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

CLK

Reset

TA

TB

S'1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00) S1 (01)

S1:0 ?? S0 (00) S1 (01) S2 (10) S3 (11) S0 (00)

LA1:0 ?? Green (00) Yellow (01) Red (10) Green (00)

LB1:0 ?? Red (10) Green (00) Yellow (01) Red (10)

0 5 10 15 20 25 30 35 40 45 t (sec)

121
Finite State Machine:
State Encoding

122
FSM State Encoding
n How do we encode the state bits?
q Three common state binary encodings with different tradeoffs
1. Fully Encoded
2. 1-Hot Encoded
3. Output Encoded

n Let’s see an example Swiss traffic light with 4 states

q Green, Yellow, Red, Yellow+Red

123
FSM State Encoding (II)
1. Binary Encoding (Full Encoding):
q Use the minimum number of bits used to encode all states

n Use log2(num_states) bits to represent the states

q Example states: 00, 01, 10, 11

q Minimizes # flip-flops, but not necessarily output logic or

next state logic

2. One-Hot Encoding:
q Each bit encodes a different state

n Uses num_states bits to represent the states

n Exactly 1 bit is “hot” for a given state

q Example states: 0001, 0010, 0100, 1000
q Simplest design process – very automatable
q Maximizes # flip-flops, minimizes next state logic
124
FSM State Encoding (III)
3. Output Encoding:
q Outputs are directly accessible in the state encoding

q For example, since we have 3 outputs (light color),

encode state with 3 bits, where each bit represents a
color
q Example states: 001, 010, 100, 110
n Bit0 encodes green light output,
n Bit1 encodes yellow light output
n Bit2 encodes red light output

q Minimizes output logic

q Only works for Moore Machines (output function of state)
125
FSM State Encoding (III)
3. Output Encoding:
q Outputs are directly accessible in the state encoding

q For example, since we have 3 outputs (light color),

encode state with 3 bits, where each bit represents a
The designer must carefully choose
color
an encoding
q Example scheme
states: to100,
001, 010, optimize
110 the design
n
under given constraints
Bit0 encodes green light output,
n Bit1 encodes yellow light output
n Bit2 encodes red light output

q Minimizes output logic

q Only works for Moore Machines (output function of state)
126
Moore vs. Mealy Machines

127
Recall: Moore vs. Mealy FSMs
n Next state is determined by the current state and the inputs
n Two types of finite state machines differ in the output
logic:
q Moore FSM: outputs depend only on the current state
q Mealy FSM: outputs depend on the current state and the
inputs Moore FSM

CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

128
Moore vs. Mealy FSM Examples
n Alyssa P. Hacker has a snail that crawls down a paper tape with
1’s and 0’s on it.
n The snail smiles whenever the last four digits it has crawled over
are 1101.
n Design Moore and Mealy FSMs of the snail’s brain.
Moore FSM

CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

129
Moore vs. Mealy FSM Examples
n Alyssa P. Hacker has a snail that crawls down a paper tape with
1’s and 0’s on it.
n The snail smiles whenever the last four digits it has crawled over
are 1101.
n Design Moore and Mealy FSMs of the snail’s brain.
Moore FSM

CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

Mealy FSM

CLK
M next
next k state k state output N
inputs state outputs
logic
logic

130
State Transition Diagrams
Moore FSM 1
reset
1 1 0 1

S0 S1 S2 S3 S4
0 0 0 0 1
0
1 0 0
0

What are the tradeoffs?

Mealy FSM
1/1
reset
1/0 1/0 0/0

S0 S1 S2 S3
0/0 1/0 0/0
0/0

131
FSM Design Procedure
n Determine all possible states of your machine
n Develop a state transition diagram
q Generally this is done from a textual description
q You need to 1) determine the inputs and outputs for each state and
2) figure out how to get from one state to another
n Approach
q Start by defining the reset state and what happens from it – this is
typically an easy point to start from
q Then continue to add transitions and states
q Picking good state names is very important
q Building an FSM is like programming (but it is not programming!)
n An FSM has a sequential “control-flow” like a program with conditionals and goto’s
n The if-then-else construct is controlled by one or more inputs
n The outputs are controlled by the state or the inputs
q In hardware, we typically have many concurrent FSMs

132
What is to Come: LC-3 Processor

133
What is to Come: LC-3 Datapath

134
Backup Slides:
Different Types of Flip Flops

135
Enabled Flip-Flops
n Inputs: CLK, D, EN
q The enable input (EN) controls when new data (D) is stored
n Function:
q EN = 1: D passes through to Q on the clock edge
q EN = 0: the flip-flop retains its previous state

Internal
Circuit Symbol

EN CLK

0
D Q Q D Q
D 1
EN

136
Resettable Flip-Flop
n Inputs: CLK, D, Reset
q The Reset is used to set the output to 0.
n Function:
q Reset = 1: Q is forced to 0

q Reset = 0: the flip-flop behaves like an ordinary D flip-flop

Symbols

D Q
r
Reset

137
Resettable Flip-Flops
n Two types:
q Synchronous: resets at the clock edge only
q Asynchronous: resets immediately when Reset = 1
n Asynchronously resettable flip-flop requires changing the
internal circuitry of the flip-flop (see Exercise 3.10)
n Synchronously resettable flip-flop?

Internal
Circuit
CLK

D
D Q Q
Reset

138
Settable Flip-Flop
n Inputs: CLK, D, Set
n Function:
q Set = 1: Q is set to 1
q Set = 0: the flip-flop behaves like an ordinary D flip-flop

Symbols

D Q
s
Set

139
Logic Simplification:
Karnaugh Maps (K-Maps)

140
Logic Simplification
n Systematic techniques for simplifications
q amenable to automation
$ + 𝑨𝑩
Key Tool: The Uniting Theorem — 𝑭 = 𝑨𝑩

𝑭= $ + 𝑨𝑩 = 𝑨 𝑩
𝑨𝑩 $ +𝑩 =𝑨 𝟏 =𝑨

B's value changes within the rows where F==1 (“ON set”)
Essence of Simplification:
Find two elementA's subsets
value doesof
NOT
thechange within
ON-set the ON-set
where onlyrows
one variable
changes its value.
If anThis
inputsingle
(B) can varying variable
change without can the
changing be output,
eliminated!
that input
value is not needed
➙ B is eliminated, A remains

$𝑩
𝑮= 𝑨 $ + 𝑨𝑩 $+𝑨 𝑩
$= 𝑨 $=𝑩
$

B's value stays the same within the ON-set rows

A's value changes within the ON-set rows

➙ A is eliminated, B remains
141
Complex Cases
n One example
& 𝑩𝑪 + 𝑨𝑩
𝑪𝒐𝒖𝒕 = 𝑨 & + 𝑨𝑩𝑪
& 𝑪 + 𝑨𝑩𝑪
n Problem
q Easy to see how to apply Uniting Theorem…
q Hard to know if you applied it in all the right places…
q …especially in a function of many more variables

n Question
q Is there an easier way to find potential simplifications?
q i.e., potential applications of Uniting Theorem…?

n Answer
q Need an intrinsically geometric representation for Boolean f( )
q Something we can draw, see…

142
Karnaugh Map
n Karnaugh Map (K-map) method
q K-map is an alternative method of representing the truth table
that helps visualize adjacencies in up to 6 dimensions
q Physical adjacency ↔ Logical adjacency

2-variable K-map 3-variable K-map 4-variable K-map

𝑩 0 1 𝑩𝑪 𝑪𝑫
𝑨
𝑨 00 01 11 10 𝑨𝑩 00 01 11 10
0 00 01
0 000 001 011 010 00 0000 0001 0011 0010

1 10 11
1 100 101 111 110 01 0100 0101 0111 0110

11 1100 1101 1111 1110

10 1000 1001 1011 1010

Numbering Scheme: 00, 01, 11, 10 is called a

“Gray Code” — only a single bit (variable) changes
from one code word and the next code word

143
Karnaugh Map Methods
Adjacent

𝑩𝑪
𝑨 00 01 11 10
000 100
010 110
001 101
0 000 001 011 010 011 111

1 100 101 111 110 000 010 110 100

001 011 111 101

Adjacent

K-map adjacencies go “around the edges”

Wrap around from first to last column
Wrap around from top row to bottom row

144
K-map Cover - 4 Input Variables

𝐅(𝐀, 𝐁, 𝐂, 𝐃) = . 𝒎(𝟎, 𝟐, 𝟓, 𝟖, 𝟗, 𝟏𝟎, 𝟏𝟏, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓)

𝑪𝑫
𝑨𝑩 00 01 11 10 9𝑫 9
9 + 𝐁𝑪𝑫
𝐅=𝐀+𝑩
00 1 0 0 1
01 0 1 0 0
11 1 1 1 1 Strategy for “circling” rectangles on Kmap:
10 1 1 1 1
As big as possible
Biggest “oops!” that people forget:
Wrap-arounds

145
Logic Minimization Using K-Maps
n Very simple guideline:
q Circle all the rectangular blocks of 1’s in the map, using the
fewest possible number of circles
n Each circle should be as large as possible
q Read off the implicants that were circled

n More formally:
q A Boolean equation is minimized when it is written as a sum of
the fewest number of prime implicants
q Each circle on the K-map represents an implicant
q The largest possible circles are prime implicants

147
K-map Rules
n What can be legally combined (circled) in the K-map?
q Rectangular groups of size 2k for any integer k
q Each cell has the same value (1, for now)
q All values must be adjacent
n Wrap-around edge is okay

n How does a group become a term in an expression?

q Determine which literals are constant, and which vary across group
q Eliminate varying literals, then AND the constant literals
n 9
constant 1 ➙ use 𝐗, constant 0 ➙ use 𝑿

n What is a good solution?

q Biggest groupings ➙ eliminate more variables (literals) in each term
q Fewest groupings ➙ fewer terms (gates) all together
q OR together all AND terms you create from individual groups
148
K-map Example: Two-bit Comparator
A B C D F1 F2 F3
0 0 0 0 1 0 0
0 0 0 1 0 1 0
A AB = CD 0 0 1 0 0 1 0
F1
0 0 1 1 0 1 0
B AB < CD 0 1 0 0 0 0 1
F2
0 1 0 1 1 0 0
C AB > CD 0 1 1 0 0 1 0
F3
0 1 1 1 0 1 0
D 1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 1 0 0
1 0 1 1 0 1 0
Design Approach: 1 1 0 0 0 0 1

Write a 4-Variable K-map 1 1 0 1 0 0 1

for each of the 3 1 1 1 0 0 0 1
output functions 1 1 1 1 1 0 0

149
K-map Example: Two-bit Comparator (2)
K-map for F1 A B C D F1 F2 F3
0 0 0 0 1 0 0
𝑪
0 0 0 1 0 1 0
𝑪𝑫 00 01 11 10 0 0 1 0 0 1 0
𝑨𝑩
00 0 0 1 1 0 1 0
1 0 1 0 0 0 0 1

01 0 1 0 1 1 0 0
1 0 1 1 0 0 1 0

11 𝑩 0 1 1 1 0 1 0
1
𝑨 1 0 0 0 0 0 1
1 0 0 1 0 0 1
10
1 1 0 1 0 1 0 0
1 0 1 1 0 1 0
1 1 0 0 0 0 1
𝑫 1 1 0 1 0 0 1
1 1 1 0 0 0 1
F1 = A'B'C'D' + A'BC'D + ABCD + AB'CD'
1 1 1 1 1 0 0

150
K-map Example: Two-bit Comparator (3)
K-map for F2 A B C D F1 F2 F3
𝑪 0 0 0 0 1 0 0
𝑪𝑫 00 01 11 10 0 0 0 1 0 1 0
𝑨𝑩 0 0 1 0 0 1 0
00
1 1 1 0 0 1 1 0 1 0
0 1 0 0 0 0 1
01
1 1 0 1 0 1 1 0 0
0 1 1 0 0 1 0
11 𝑩
0 1 1 1 0 1 0
𝑨 1 0 0 0 0 0 1
10
1 1 0 0 1 0 0 1
1 0 1 0 1 0 0
1 0 1 1 0 1 0
𝑫 1 1 0 0 0 0 1

F2 = A'C + A'B'D + B'CD 1 1 0 1 0 0 1

1 1 1 0 0 0 1
F3 = ? (Exercise for you) 1 1 1 1 1 0 0

151
K-maps with “Don’t Care”
n Don’t Care really means I don’t care what my circuit outputs if this
appears as input
q You have an engineering choice to use DON’T CARE patterns
intelligently as 1 or 0 to better simplify the circuit

A B C D F G

•••
I can pick 00, 01, 10, 11
0 1 1 0 X X independently of below
0 1 1 1
1 0 0 0 X X
1 0 0 1 I can pick 00, 01, 10, 11
independently of above
•••

152
Example: BCD Increment Function
n BCD (Binary Coded Decimal) digits
q Encode decimal digits 0 - 9 with bit patterns 00002 — 10012
q When incremented, the decimal sequence is 0, 1, …, 8, 9, 0, 1

A B C D W X Y Z
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
These input patterns should
1 1 0 1 X X X X never be encountered in practice
1 1 1 0 X X X X (hey -- it’s a BCD number!)
1 1 1 1 X X X X So, associated output values are
“Don’t Cares”
153
K-map for BCD Increment Function
W X
𝑪𝑫 𝑪𝑫
Z
ABCD
(without
𝑨𝑩 don’t
00 01 cares)
11 10 = A'D'
𝑨𝑩 +00B'C'D’
01 11 10
00 00 1
+ 1
Z (with don’t
01 cares)1 = D' 01 1 1 1
WXYZ 11 X X X X 11 X X X X
10 1 X X 10 X X

Y 𝑪𝑫
Z 𝑪
00 01 11 10 𝑪𝑫
𝑨𝑩 𝑨𝑩 00 01 11 10
00 1 1 00 1 1
01 1 1 01 1 1
11 X X X X 11 X X X X
𝑩
𝑨
10 X X 10 1 X X
𝑫 154
K-map Summary

n Karnaugh maps as a formal systematic approach

for logic simplification

n 2-, 3-, 4-variable K-maps

n K-maps with “Don’t Care” outputs

n H&H Section 2.7

155