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DEMUX

The document describes different modeling approaches for a 1x8 demultiplexer (demux) circuit: 1. An if-else statement models the demux using logic conditions to assign the output. 2. A case statement models the demux using a case expression to assign the appropriate output. 3. Dataflow modeling uses assign statements to directly assign outputs based on input conditions. 4. Ternary operators model the demux using conditional expressions of the form (condition) ? true_value: false_value.

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Pooja Dhakane
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39 views9 pages

DEMUX

The document describes different modeling approaches for a 1x8 demultiplexer (demux) circuit: 1. An if-else statement models the demux using logic conditions to assign the output. 2. A case statement models the demux using a case expression to assign the appropriate output. 3. Dataflow modeling uses assign statements to directly assign outputs based on input conditions. 4. Ternary operators model the demux using conditional expressions of the form (condition) ? true_value: false_value.

Uploaded by

Pooja Dhakane
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1:8 DEMUX

A. If statement with multiple else-if clause

module demux18 (sel, I, Y);


input [2:0] sel;
input I;
output [7:0] Y;
reg Y;
always @ (sel or I)
begin
if (sel= = 3’b000)
Y[0]=I;
module demux18 (sel, I, Y);
input [2:0] sel;
input I;
output [7:0] Y;
reg Y;
always @ (sel or I)
begin
if (sel= = 3’b000)
Y[0]=I;
else if (sel= = 3’b110)
Y[6]=I;
else
Y[7]=I;
end
endmodule

B. Case statement
module demux18 (sel, I, Y);
input [2:0] sel;
input I;
output [7:0] Y;
reg Y;
always @ (sel or I)
begin
case (sel)
3’b000 : Y[0]=I;
3’b001 : Y[1]=I;
3’b010 : Y[2]=I;
3’b011 : Y[3]=I;
3’b100 : Y[4]=I;
3’b101 : Y[5]=I;
3’b110 : Y[6]=I;
3’b111 : Y[7]=I;
default : Y[0]=I;
endcase
end
endmodule

C. Dataflow Modeling

module demux18 (sel, I, Y);


input [2:0] sel;
input I;
output [7:0] Y;
assign Y[0] = ( ~s2 & ~s1 & ~s0 & I) ,
Y[1] = ( ~s2 & ~s1 & s0 & I) ,
Y[2] = ( ~s2 & s1 & ~s0 & I) ,
Y[3] = ( ~s2 & s1 & s0 & I) ,
Y[4] = ( s2 & ~ s1 & ~ s0 & I) ,
Y[5] = ( s2 & ~ s1 & s0 & I),
Y[6] = ( s2 & s1 & ~ s0 & I),
Y[7] = ( s2 & s1 & s0 & I) ;
Endmodule

D. Ternary Operator

module demux18 (sel, I, Y);


input [2:0] sel;
input I;
output [7:0] Y;
assign Y[0] = (sel==3'b000) ? I : 1'b0;
assign Y[1] = (sel==3'b001) ? I : 1'b0;
assign Y[2] = (sel==3'b010) ? I : 1'b0;
assign Y[3] = (sel==3'b011) ? I : 1'b0;
assign Y[4] = (sel==3'b100) ? I : 1'b0;
assign Y[5] = (sel==3'b101) ? I : 1'b0;
assign Y[6] = (sel==3'b110) ? I : 1'b0;
assign Y[7] = (sel==3'b111) ? I : 1'b0;
endmodule

E. Structural Modeling

module demux18str(in,s0,s1,s2,d0,d1 ,d2,d3,d4,d5,d6,d7);


input in,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
and g1(d0,in,s0,s1,s2);
and g2(d1,in,(~s0),s1,s2);
and g3(d2,in,s0,(~s1),s2);
and g4(d3,in,(~s0),(~s1),s2);
and g5(d4,in,s0,s1,(~s2));
and g6(d5,in,(~s0),s1,(~s2));
and g7(d6,in,s0,(~s1),(~s2));
and g8(d7,in,(~s0),(~s1),(~s2));
endmodule
1:4 DEMUX
1) Gate-Level Modelling :

module demux(i, s0, s1, y0, y1, y2, y3);

input i;

input s0;

input s1;

output y0;

output y1;

output y2;

output y3;

wire s0b,s1b;

not(s1b,s1);

not(s0b,s0);

and(y0,i,s1b,s0b);

and(y1,i,s1b,s0);

and(y2,i,s1,s0b);

and(y3,i,s1,s0);

endmodule

2) DataFlow Modelling :

module demux1_4(I, S0, S1, Y0, Y1, Y2, Y3);

input I;

input S0;

input S1;
output Y0;

output Y1;

output Y2;

output Y3;

wire s0b,s1b;

assign S0b=~S0;

assign S1b=~S1;
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assign Y0= I & S0b & S1b;

assign Y1= I & S0 & S1b;

assign Y2= I & S0b & S1;

assign Y3= I & S0 & S1;

endmodule

3) Behavioural Modelling :

module demux7(I, S, Y);

input I;

input [1:0] S;

output reg [3:0] Y;

always@(I,S)

begin

case({S[0],S[1]})

2'b00: beginY[0]=I;Y[1]=1'b0;Y[2]=1'b0;Y[3]=1'b0; end


2'b01: beginY[0]=1'b0;Y[1]=I;Y[2]=1'b0;Y[3]=1'b0; end

2'b10: beginY[0]=1'b0;Y[1]=1'b0;Y[2]=I;Y[3]=1'b0; end

2'b11: begin Y[0]=1'b0;Y[1]=1'b0;Y[2]=1'b0;Y[3]=I; end

default: $display("Invalid");

endcase

end

endmodule

Gate level

module 8x1_mux_using_2_4x1_mux{O,s,i);

input [7:0]i;

input[2:0]s;

output O;

mux a ({s[1:0]},{ i[3:0]},w1);

mux a1({s[1:0]},{ i[7:4]},w2);

not n(w3,s[2]);

and an(w4,w1,w3):
and an1(w5,w2,s[2]):

nor n1(o,w4,w5):

endmodule

BEHAVE

module mux( sel, in, out );

input[1:0] sel;

input[3:0] in;

output out;

reg output;

always @( sel or in )

begin

if( sel == 0)

out = in[0];

else if( sel == 1)

out = in[1];

else if( sel == 2)

out = in[2];

else if( sel == 3)

out = in[3];

else
out=1’bX

end

endmodule

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