The All Parallel Autotransformer
The All Parallel Autotransformer
system
Submitted To
Submitted By
Department of Physics
Fig.1 Block Diagram of 8051 GSM based power transformer fault detection system
failure of winding, core heating and fall of usually requires the combination of these
into a short circuit and removed from the from one circuit to another, especially a pair
system. Usually provides protection against of multiple wound, inductively coupled wire
By using a winding with a central tapping, leakage of magnetic field around the
Insulation Test
1 to 1.25 1 to 2 Dubious
1.4 to 1.6 2 to 4 Good
PIN CONFIGURATION
AT8051 microcontroller has 40 pins with a bytes during Flash programming and
single Volt power supply. The pin 40 is verification.
illustrated
Port2:
as follows:
Port 2 is an 8-bit bi-directional I/O port with
Vcc: Supply Voltage. internal pull-ups. The Port 2 output buffers
GND: Ground. cansink/ source four TTL inputs. When 1s
are written to Port 2 pins, they are pulled
Port0:
high by the internal pull-ups and can be used
Port 0 is an 8-bit open drain bi-directional
as inputs. As inputs, Port 2 pins that are
I/O port. As an output port, each pin can
externally being pulled low will source
sink eight
current (IIL) because of the internal pull-ups.
TTL inputs. When 1s are written to port 0
Port 2 emits the high-order address byte
pins, the pins can be used as high-impedance
during fetching from external program
inputs.
memory and during access to external data
Port 0 can also be configured to be the
memory that uses 16-bit addresses (MOVX
multiplexed low-order address/data bus
@DPTR). In this application, Port 2 uses
during accesses to external programmed data
strong internal pullups when emitting 1s.
memory. In this mode, P0 has internal pull-
During accesses to external data memory
ups. Port 0 also receives the code bytes
that uses 8-bit address (MOVX
during Flash programming and outputs the
@R1), Port 2 emits the contents of the P2
code bytes during program verification.
Special Function Register. Port 2 also
Port1: receives the high-order address bits and
Port 1 is an 8-bit bi-directional I/O port with some control signals during Flash program
internal pull-ups. The Port 1 output buffers and verification.
can sink/ source four TTL inputs. When 1s
Port3:
are written to Port 1 pins, they are pulled
Port 3 is an 8-bit bi-directional I/O port with
high by the internal pull-ups and can be used
internal pull-ups. The Port 3 output buffers
as inputs. As inputs, port 1 pins that are
can sink/ source four TTL inputs. When 1s
externally being pulled low will source
are written to Port 3 pins, they are pulled
current (IIL) because of the internal pull-ups.
high by the internal pull-ups and can be used
Port 1 also receives the low-order address
as inputs. As inputs, Port 3 pins that are In normal operation, ALE is emitted at a
externally being pulled low will source constant rate of 1/6 the oscillator frequency
current because of the pull-ups. Port 3 also and may be used for external timing or
serves the functions of Port 3 pin alternate clocking purposes. Note, however, that one
Functions: ALE pulse is skipped during each access to
external data memory. If desired, ALE
P 3.0 RXD (Serial Input Port)
operation can be disabled by setting bit 0 of
P 3.1 TXD (Serial Output Port)
SFR location 8EH. With the bit set, ALE is
P 3.2 INT0 (External Interrupt 0)
active only during a MOVX or MOVC
P 3.3 INT1 (External Interrupt 1)
instruction. Otherwise, the pin is weakly
P 3.4 T0 (Timer 0 External Input)
pulled high. Setting the ALE-disable bit has
P 3.5 T1 (Timer 1 External Input)
no effect if the Microcontroller is in external
P 3.6 WR (External Data Memory Write
execution mode.
Strobe)
P 3.7 RD (External Data Memory Read PSEN:
Strobe)
Program Store Enable It is the read strobe to
Port 3 also receives some control signals for external program memory. When the
Flash programming and programming AT8051 is executing code from external
verification. program memory, PSEN is activated twice
RST: Reset Input each machine cycle, except that two PSEN
A high on this pin for two machine cycles activations are skipped during each access to
while the oscillator is running resets the external data memory.
device. This
EA/Vpp:
pin drives High for 98 oscillator periods
after the Watchdog times out. External Access Enable/ Programming
Enable Voltage External Access Enable
ALE/PROG:
must be strapped to GND in order to enable
Address Latch Enable is an output pulse for
the device to fetch code from external
latching the low byte of the address during
program memory locations starting at
accesses to external memory. This pin is
0000H up to FFFFH. Note, however, that if
also the program pulse input (PROG) during
lock bit 1 is programmed, EA will be
Flash programming.
internally latched on reset. EA should be
strapped to Vcc for internal program device which has in-built CPU memory and
executions. This pin also receives the 12- peripherals to make it act as a mini-
volt programming enable voltage (Vpp) computer
during Flash programming. Microcontroller has one or two operational
codes for moving data from external to CPU
XTAL1:
Input to the inverting oscillator amplifier Microcontroller has many bit handling
4. Conclusion