DIGITAL LOGIC

AND MICROPROCESSOR
Dr.M.Sindhuja
Assistant Professor(Senior Grade)
School of Electronics
VIT, Chennai
 MODULE-3

SEQUENTIAL LOGIC CIRCUITS

 INTRODUCTION

Block diagram of a sequential circuit

 Output at any instant of time depend not only on the present inputs but
also on the past outputs are called sequential circuit.
 Output are fed back to the input side
 It consist of combinational circuit to which memory element connected to
form feedback path
 TYPES OF SEQUENTIAL CIRCUITS
Synchronous- knowledge of its signals
at discrete instants of time
Asynchronous-depends upon the input
signals at any instant of time

Synchronous sequential circuit

 Most frequently encountered in practice
Synchronization is achieved by a timing
device called a clock generator (Clk), provides Clocked sequential circuit
clock signal
use clock pulses to control storage elements ar
e called clocked sequential circuits
feasible because it manifest stability problems
 FLIP FLOPS

Memory elements used in clocked sequential circuits are called flip-flops.

Store one bit of information

A flip-flop circuit maintain a binary state until directed by an input signal

to switch states
 SR FLIP FLOP WITH NOR GATES
S R Q Q’
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
Q′
1 1 0 0

Truth Table

Flip-flop has two outputs, Q and Q′, and two inputs, set and reset.
Flipflop is sometimes called a direct-coupled SR flip-flop or SR latch.
 OPERATION
 In general NOR gate, output = 0 if any input is 1;output = 1 only when
all inputs are 0.

S = 0, R = 0; normal resting state of the circuit and it has no effect of the

output states.

S = 1, R = 0; this will set Q to 1, it works in SET mode operation.

Q and Q’ will remain in prior state. It works in HOLD (no change) mode
operation.

 S = 0, R = 1; this will reset Q to 0, it works in RESET mode operation.

S = 1, R = 1; Q & Q’ = 0. This condition is undefined and avoided

SR FLIP FLOP WITH NAND GATES

S R Q Q’
1 0 0 1
1 1 0 1
0 1 1 0
1 1 1 0
Q′
0 0 1 1

Truth Table
 OPERATION
In general NOR gate, output = 0 if any input is 1;output = 1 only when
all inputs are 0.

S = 1, R = 1; normal resting state of the circuit and it has no effect on

output states.

S = 1, R = 0; this will set Q to 1, it works in SET mode operation.

Q and Q’ will remain in prior state. It works in HOLD (no change) mode
operation.

S = 0, R = 1; this will reset Q to 0, it works in RESET mode operation.

S = 0, R = 0; Q & Q’ = 1. This condition is undefined and avoided

THANK YOU
 DIGITAL LOGIC
AND MICROPROCESSOR
Dr.M.Sindhuja
Assistant Professor(Senior Grade)
School of Electronics
VIT, Chennai
 CLOCKED SR FLIP-FLOP
CLK S R Q

1 0 0 No change

1 0 1 0; Reset state

1 1 0 1; set state
Q′
1 1 1 Indeterminate

Truth Table

Adding gates to the inputs of the basic circuit, flip-flop respond to input during the
occurrence of a clock pulse is also called edge triggered Flip Flop
When ClK=1,
S = 1 and R = 0, it is in the set state
S= 0 and R= 1, it is in the clear state.
S = 1 and R = 1 , state is undefined and avoided
 OPERATION
CLK S R Qt Qt+1 State
SR
1 0 0 0 0 No change 00 01 11 10
0 0 1 1 Q
1 0 1 0 0 Reset
0 1 1 0 0 X 1
1 1 0 0 1 Set
1 0 1 1 X 1
1 1 0 x Indeterminate
1 1
1 1 1 1 x
Characteristic equation Qt+1= S+R´ Qt
CHARACTERISTIC TABLE OF SR FLIP-FLOP
 D FLIP-FLOP

CLK D Q

1 0 0; Reset state

Q’ 1 1 1; Set state

Logic diagram using NAND gates Truth Table

 OPERATION
Also Known as Data Flip flop
eliminate the indeterminate state in SR flip-flop by D flip-flop
Can be constructed from RS Flip Flop by addition of an inverter.
 D input is directly connected to S input and its complement is connected to
R input.
 when CLK=1, D=1, Q=1, keep the circuit in SET state
 when CLK=1, D=0, Q=0, Keep the circuit in RESET state
D Flip-Flop also called transparent latch because the output follows input
when clock is enabled.
CLK D Qt Qt+1 State D
Q 0 1
0 x Qt Qt No change 0
1
1 0 0 0 Reset
1 0 1 0 1
1
1 1 0 1 Set
1 1 1 1 Characteristic equation Qt+1= D

CHARACTREISTIC TABLE OF D FLIP-FLOP

THANK YOU
 DIGITAL LOGIC
AND MICROPROCESSOR
Dr.M.Sindhuja
Assistant Professor(Senior Grade)
School of Electronics
VIT, Chennai
 JK FLIFLOP
J CLK J K Q
Q
1 0 0 No change

CLK 1 0 1 0; Reset state

1 1 0 1; set state
Q′ Toggle
K 1 1 1

Truth Table
Logic diagram using NAND gates
When J=0 and K=0, no change of state takes place
When J=0 and k=1, the flip-flop goes to reset state
When J=1 and k=0, the flip-flop goes to set state
When J=1 and K=1, the flip-flop toggles or changes its state
CLK J K Qt Qt+1 State JK
00 01 10 11
0 0 0 0 No change
Q 1 1
1 0 0 1 1
0 1 0 0 Reset 0
1 0 1 1 0
1 1
1 0 0 1 Set 1
1 1 0 1 1
1 1 0 1 Toggle
1 1 1 1 0 Characteristic equation Qt+1= J Qt’ + K’ Qt

CHARCTERISTIC TABLE OF JK FLIP-FLOP

 T FLIPFLOP

J
T
CLK T Q

1 0 No change

1 1 Toggle
Q′
Truth Table

LogicT=0,
When diagram using
no change NAND
of state gates
takes place
When T=1, the flip-flop toggles on every clock pulse
CLK T Qt Qt+1 State T
0 1
Q
1 0 0 0 No change
0 1
1 0 1 1
1 1 0 1 Toggle
1 1 1 0 1
1

CHARCTERISTIC TABLE OF T FLIP-FLOP Characteristic equation Qt+1= T Qt’ + T’ Qt

MASTER-SLAVE JK FLIP-FLOP

J
D J
D
MASTER
Q SLAVE
Q

C C Q′
For JK flip-flop if J=K=1 and if width of clock pulse is too long, then
state of flip-flop keep on toggle which leads to uncertainty in determining
output state of flip-flop. This problem is called Race around condition.

 Master- Slave flip-flop used to avoid the problems of race around

condition in clocked flip-flop

A master- slave flip-flop constructed using two separate flip-flop

connected serially

First-flop serve as Master driven by positive edge of clock pulse

 second flip-flop serve as Slave driven by negative edge of clock pulse

 CLOCKED MASTER-SLAVE JK FLIP-FLOP USING
NAND GATES
J
Q
Q
CLK

Q′
K Q′
 OPERATION
If J=1, K=0, Master flip-flop sets on positive edge, then ouptut of master Q=1
(set) drives the input of slave.

When negative edge comes, slave also sets. Slave copies the action of master

If J=0, K=1, the master reset on leading edge of clock pulse, output Q =0 of
master drives the input J of slave flip-flop and slave resets during negative
clock edge.

If J=1,k=1, master flip-flop toggles on positive clock edge and slave toggles on
negative clock edge.

J=k=0, does not produce any change

THANK YOU
 DIGITAL LOGIC
AND MICROPROCESSOR
Dr.M.Sindhuja
Assistant Professor(Senior Grade)
School of Electromics
VIT, Chennai
 REGISTER

It is a group of flip-flops suitable for holding binary information.

Each flip-flop is a binary cell capable of storing one bit of information.

 n-bit register has group of n flip-flops and storing binary information

containing n bits.

 In addition, it have combinational gates that perform data-processing

tasks.

 Gates in register control when and how the information transferred into
register
 REGISTER
Various types of registers are available in MSI circuits.

simplest possible register is one that contains no external gates, and is

constructed of only flip-flops.

4 bit Register
 SHIFT REGISTER
 Shifting its binary information either to right or left is called a shift register

Chain of flip-flop connected in cascade

Output of one flip-flop connected to input of next flip-flop

All flip-flops receive a common clock pulse causes the shift from one stage to
the next

Two methods of shifting the data

- Serial shifting – shift one bit at a time for each clock pulse
- Parallel shifting- all data shifted simultaneously during single
clock pulse
 TYPES OF SHIFT REGISTER
Serial Serial
Serial
data input data output data input n bit Serial-in Parallel-out (SIPO)
n bit

Parallel
Serial-in serial-out(SISO) data output
Parallel Parallel
data input data input

Serial
data output
n bit n bit Parallel-in parallel-out(PIPO)

Parallel-in serial-out(PISO) Parallel

data output
 SERIAL-IN SERIAL-OUT (SISO)
Serial
Serial data output
data input
D QA D QB D QC D QD

D Q D

CLK QA QB QC QD

0 0 0 0 0
1 1 0 0 0
2 1 1 0 0 Operation of SISO
3 1 1 1 0
4 1 1 1 1
 OPERATION OF SISO
This type of shift register, accepts data serially, (one bit at a time on single
input line and also produce single output serially)

Data shifted may be left using shift left register and right using shift right
Register

Clock pulse applied to all flip-flop simultaneously

Bit stored in first FF is transferred to second FF and from second FF to

third FF and so on.
Example consider 4-bit binary number 1111 is to stored in register

Initially when no clock pulse is applied, QA=0, QB=0, QC=0, QD=0

When first clock pulse is applied, 1 is applied to D, and this 1 shifted to FF1
and all other FFs store their respective bits at D inputs

After first clock pulse, QA=1, QB=0, QC=0, QD=0

Similarly shift the bits for other clock pulses by applying other binary inputs

Finally it completes serial entry of 1111.

 SERIAL-IN PARALLEL-OUT (SIPO)
Q3 Q2 Q1 Q0
Serial Parallel
data input data output
D D D D
D Q D

CLK Q3 Q2 Q1 Q0

0 0 0 0 0
Once the data bit are stored, each
bit appears on its respective output
1 1 0 0 0
simultaneously, rather than bit by bit
2 1 1 0 0 basis as with serial output.
3 1 1 1 0
4 1 1 1 1
Operation of SIPO
 PARALLEL-IN PARALLEL-OUT (SIPO)
D3 D2 D1 D0

D D D D
D Q D

Q3 Q1 Q0
Q2
 OPERATION OF PIPO

Data entered into register and taken out from register are in parallel form

When clock pulse is applied, D inputs are shifted into Q outputs of flip-flop.

 Register stores the data and is available instantly for shifting out in parallel
form
 PARALLEL-IN SERIAL-OUT (PISO)
SHIFT/ D2 D1 D0

4 1 5 2 6 3

D3

Q0
D D D D
Q3 Q2 Q1
D Q D
 OPERATION OF PISO
Data bits are entered simultaneously on parallel lines into all flip-flop but d
ata are shifted out serially.
D3, D2, D1, D0 are parallel data input lines and is control input
Control input allow the data to be entered in parallel form and shifted
out serially
When is low, it allow AND gates 1 , 2 and 3 are enabled, allow
data at parallel inputs.
When is high, AND gates 4,5,6 are enabled, allowing the data bits
to shift from one stage to next after clock pulse applied.
OR gates allow either normal shifting operating or parallel data entry opera
tion depends on which AND gates are enabled by
UNIVERSAL SHIFT REGISTER
THANK YOU