Dept. of ECE www.studymaterialz.

in
MCQ for Regulations 2017

Answer: a
Explanation: It takes exactly one clock cycle
EC8791 to perform a basic operation, such as moving
a byte of memory from a location to another
EMBEDDED AND location in the computer.

REAL TIME 3. The operation that does not involves clock

cycles is _________
SYSTEMS a) Installation of a device
b) Execute
ECE - 7th Semester - c) Fetch
d) Decode
Reg. 2017 Answer: a
Explanation: Normally, several clock cycles
are required to fetch, execute and decode a
particular program.
Installation of a device is done by the system
UNIT I INTRODUCTION on its own.
TO EMBEDDED SYSTEM 4. The number of clock cycles per second is
DESIGN referred as ________
a) Clock speed
b) Clock frequency
TOPIC 1.1 COMPLEX SYSTEMS c) Clock rate
AND MICRO PROCESSORS d) Clock timing

1. Computer has a built-in system clock that Answer: a

emits millions of regularly spaced electric Explanation: The number of clock cycles per
pulses per _____ called clock cycles. second is the clock speed. It is generally
a) second measured in gigahertz(109 cycles/sec) or
b) millisecond megahertz (106 cycles/sec).
c) microsecond
d) minute 5. CISC stands for ____________
a) Complex Information Sensed CPU
Answer: a b) Complex Instruction Set Computer
Explanation: The regularly spaced electric c) Complex Intelligence Sensed CPU
pulses per second are referred to as the clock d) Complex Instruction Set CPU
cycles. All the jobs performed by the
processor are on the basis of clock cycles. Answer: b
Explanation: CISC is a large instruction set
2. It takes one clock cycle to perform a basic computer. It has variable length instructions.
operation. It also has variety of addressing modes.
a) True
b) False 6. Which of the following processor has a
fixed length of instructions?
a) CISC

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

b) RISC address register. It holds the address of the

c) EPIC active memory location.
d) Multi-core
10. A circuitry that processes that responds to
Answer: b and processes the basic instructions that are
Explanation: The RISC which stands for required to drive a computer system is
Reduced Instruction set computer has a fixed ________
length of instructions. It has a small a) Memory
instruction set. Also has reduced references to b) ALU
memory to retrieve operands. c) CU
d) Processor
7. Processor which is complex and expensive
to produce is ________ Answer: d
a) RISC Explanation: The processor is responsible for
b) EPIC processing the basic instructions in order to
c) CISC drive a computer. The primary functions of a
d) Multi-core processor are fetch, decode and execute.

Answer: c
Explanation: CISC stands for complex TOPIC 1.2 EMBEDDED SYSTEM
instruction set computer. It is mostly used in DESIGN PROCESS
personal computers. It has a large instruction
set and a variable length of instructions. 1. Which of the following allows the reuse of
the software and the hardware components?
8. The architecture that uses a tighter a) platform based design
coupling between the compiler and the b) memory design
processor is ____________ c) peripheral design
a) EPIC d) input design
b) Multi-core
c) RISC Answer: a
d) CISC Explanation: The platform design allows the
reuse of the software and the hardware
Answer: a components in order to cope with the
Explanation: EPIC stands for Explicitly increasing complexity in the design of
parallel instruction computing. It has a tighter embedded systems.
coupling between the compiler and the
processor. It enables the compiler to extract 2. Which of the following is the design in
maximum parallelism in the original code. which both the hardware and software are
considered during the design?
9. MAR stands for ___________ a) platform based design
a) Memory address register b) memory based design
b) Main address register c) software/hardware codesign
c) Main accessible register d) peripheral design
d) Memory accessible register
Answer: c
Answer: a Explanation: The software/hardware
Explanation: The MAR stands for memory codesign is the one which having both
hardware and software design concerns. This

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

will help in the right combination of the 6. Which design activity helps in the
hardware and the software for the efficient transformation of the floating point arithmetic
product. to fixed point arithmetic?
a) high-level transformation
3. What does API stand for? b) scheduling
a) address programming interface c) compilation
b) application programming interface d) task-level concurrency management
c) accessing peripheral through interface
d) address programming interface Answer: a
Explanation: The high-level transformation
Answer: b are responsible for the high optimizing
Explanation: The platform-based design transformations, that is, for the loop
helps in the reuse of both the hardware and interchanging and the transformation of the
the software components. The application floating point arithmetic to the fixed point
programming interface helps in extending the arithmetic can be done by the high-level
platform towards software applications. transformation.

4. Which activity is concerned with 7. Which design activity is in charge of

identifying the task at the final embedded mapping operations to hardware?
systems? a) scheduling
a) high-level transformation b) high-level transformation
b) compilation c) hardware/software partitioning
c) scheduling d) compilation
d) task-level concurrency management
Answer: c
Answer: d Explanation: The hardware/software
Explanation: There are many design partitioning is the activity which is in charge
activities associated with the platforms in the of mapping operations to the software or to
embedded system and one such is the task- the hardware.
level concurrency management which helps
in identifying the task that needed to be 8. Which of the following is approximated
present in the final embedded systems. during hardware/software partitioning, during
task-level concurrency management?
5. In which design activity, the loops are a) scheduling
interchangeable? b) compilation
a) compilation c) task-level concurrency management
b) scheduling d) high-level transformation
c) high-level transformation
d) hardware/software partitioning Answer: a
Explanation: The scheduling is performed in
Answer: c several contexts. It should be approximated
Explanation: The high-level transformation with the other design activities like the
is responsible for the high optimizing compilation, hardware/software partitioning,
transformations, that is, the loops can be and task-level concurrency management. The
interchanged so that the accesses to array scheduling should be precise for the final
components become more local. code.

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

9. Which of the following is a process of 2. Which of the following is the design in

analyzing the set of possible designs? which both the hardware and software are
a) design space exploration considered during the design?
b) scheduling a) platform based design
c) compilation b) memory based design
d) hardware/software partitioning c) software/hardware codesign
d) peripheral design
Answer: a
Explanation: The design space exploration is Answer: c
the process of analyzing the set of designs Explanation: The software/hardware
and the design which meet the specification is codesign is the one which having both
selected. hardware and software design concerns. This
will help in the right combination of the
10. Which of the following is a meet-in-the- hardware and the software for the efficient
middle approach? product.
a) peripheral based design
b) platform based design 3. What does API stand for?
c) memory based design a) address programming interface
d) processor design b) application programming interface
c) accessing peripheral through interface
Answer: b d) address programming interface
Explanation: The platform is an abstraction
layer which covers many possible Answer: b
refinements to a lower level and is mainly Explanation: The platform-based design
follows a meet-in-the-middle approach. helps in the reuse of both the hardware and
the software components. The application
programming interface helps in extending the
TOPIC 1.3 DESIGN EXAMPLE: platform towards software applications.
MODEL TRAIN CONTROLLER-
DESIGN METHODOLOGIES- 4. Which activity is concerned with
DESIGN FLOWS - identifying the task at the final embedded
systems?
REQUIREMENT ANALYSIS a) high-level transformation
b) compilation
1. Which of the following allows the reuse of c) scheduling
the software and the hardware components? d) task-level concurrency management
a) platform based design
b) memory design Answer: d
c) peripheral design Explanation: There are many design
d) input design activities associated with the platforms in the
embedded system and one such is the task-
Answer: a level concurrency management which helps
Explanation: The platform design allows the in identifying the task that needed to be
reuse of the software and the hardware present in the final embedded systems.
components in order to cope with the
increasing complexity in the design of 5. In which design activity, the loops are
embedded systems. interchangeable?
a) compilation

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

b) scheduling Answer: a
c) high-level transformation Explanation: The scheduling is performed in
d) hardware/software partitioning several contexts. It should be approximated
with the other design activities like the
Answer: c compilation, hardware/software partitioning,
Explanation: The high-level transformation and task-level concurrency management. The
is responsible for the high optimizing scheduling should be precise for the final
transformations, that is, the loops can be code.
interchanged so that the accesses to array
components become more local. 9. Which of the following is a process of
analyzing the set of possible designs?
6. Which design activity helps in the a) design space exploration
transformation of the floating point arithmetic b) scheduling
to fixed point arithmetic? c) compilation
a) high-level transformation d) hardware/software partitioning
b) scheduling
c) compilation Answer: a
d) task-level concurrency management Explanation: The design space exploration is
the process of analyzing the set of designs
Answer: a and the design which meet the specification is
Explanation: The high-level transformation selected.
are responsible for the high optimizing
transformations, that is, for the loop 10. Which of the following is a meet-in-the-
interchanging and the transformation of the middle approach?
floating point arithmetic to the fixed point a) peripheral based design
arithmetic can be done by the high-level b) platform based design
transformation. c) memory based design
d) processor design
7. Which design activity is in charge of
mapping operations to hardware? Answer: b
a) scheduling Explanation: The platform is an abstraction
b) high-level transformation layer which covers many possible
c) hardware/software partitioning refinements to a lower level and is mainly
d) compilation follows a meet-in-the-middle approach.

Answer: c
Explanation: The hardware/software TOPIC 1.4 SPECIFICATIONS-
partitioning is the activity which is in charge SYSTEM ANALYSIS AND
of mapping operations to the software or to ARCHITECTURE DESIGN
the hardware.
1. Architectural design is a creative process
8. Which of the following is approximated
satisfying only functional-requirements of a
during hardware/software partitioning, during
system.
task-level concurrency management?
a) True
a) scheduling
b) False
b) compilation
c) task-level concurrency management Answer: b
d) high-level transformation Explanation: In architectural design you

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MCQ for Regulations 2017

design a system organization satisfying the 5. Which of the following is an architectural

functional and non-functional requirements of conflict?
a system. a) Using large-grain components improves
performance but reduces maintainability
2. A ________ view shows the system b) Introducing redundant data improves
hardware and how software components are availability but makes security more difficult
distributed across the processors in the c) Localizing safety-related features usually
system. means more communication so degraded
a) physical performance
b) logical d) All of the mentioned
c) process
d) all of the mentioned Answer: d
Explanation: High availability architecture
Answer: a can be affected by several design factors that
Explanation: A physical view is are required to be maintained to ensure that
implemented by system engineers no single points of failure exist in such
implementing the system hardware. design.

3. The UML was designed for describing 6. Which of the following is not included in
_________ Architectural design decisions?
a) object-oriented systems a) type of application
b) architectural design b) distribution of the system
c) SRS c) architectural styles
d) Both object-oriented systems and d) testing the system
Architectural design
Answer: d
Answer: d Explanation: Architectural design decisions
Explanation: The UML was designed for include decisions on the type of application,
describing object-oriented systems and, at the the distribution of the system, the
architectural design stage, you often want to architectural styles to be used, and the ways
describe systems at a higher level of in which the architecture should be
abstraction. documented and evaluated.

4. Which of the following view shows that 7. Architecture once established can be
the system is composed of interacting applied to other products as well.
processes at run time? a) True
a) physical b) False
b) development
c) logical Answer: b
d) process Explanation: Systems in the same domain
often have similar architectures that reflect
Answer: d domain concepts.
Explanation: This view is useful for making
judgments about non-functional system 8. Which of the following pattern is the basis
characteristics such as performance and of interaction management in many web-
availability. based systems?
a) architecture
b) repository pattern

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

c) model-view-controller DESIGNING WITH

d) different operating system COMPUTING PLATFORMS
Answer: c
Explanation: Model-View-Controller pattern 1. Which of the following is not included in
is the basis of interaction management in failure costs?
many web-based systems. a) rework
b) repair
9. What describes how a set of interacting c) failure mode analysis
components can share data? d) none of the mentioned
a) model-view-controller
b) architecture pattern Answer: d
c) repository pattern Explanation: Failure costs are those that
d) none of the mentioned would disappear if no defects appeared before
shipping a product to customers.
Answer: c
Explanation: The majority of systems that 2. Which requirements are the foundation
use large amounts of data are organized from which quality is measured?
around a shared database or repository. a) Hardware
b) Software
10. Which view in architectural design shows c) Programmers
the key abstractions in the system as objects d) None of the mentioned
or object classes?
a) physical Answer: b
b) development Explanation: Lack of conformance to
c) logical requirements is lack of quality.
d) process
3. Which of the following is not a SQA plan
Answer: c for a project?
Explanation: It is possible to relate the a) evaluations to be performed
system requirements to entities in a logical b) amount of technical work
view. c) audits and reviews to be performed
d) documents to be produced by the SQA
11. Which of the following is a type of group
Architectural Model?
a) Static structural model Answer: b
b) Dynamic process model Explanation: All other options support a
c) Distribution model SQA plan.
d) All of the mentioned
4. Degree to which design specifications are
Answer: d followed in manufacturing the product is
Explanation: All these models reflects the called
basic strategy that is used to structure a a) Quality Control
system. b) Quality of conformance
c) Quality Assurance
d) None of the mentioned
TOPIC 1.5 QUALITY
ASSURANCE TECHNIQUES - Answer: b
Explanation: None.

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MCQ for Regulations 2017

5. Which of the following is not included in c) test equipment

External failure costs? d) equipment calibration and maintenance
a) testing
b) help line support Answer: d
c) warranty work Explanation: The cost of quality includes all
d) complaint resolution costs incurred in the pursuit of quality or in
performing quality-related activities.
Answer: a
Explanation: External failure costs are 10. Software quality assurance consists of the
associated with defects found after the auditing and reporting functions of
product has been shipped to the customer. management.
a) True
6. Which of the following is not an appraisal b) False
cost in SQA?
a) inter-process inspection Answer: a
b) maintenance Explanation: None.
c) quality planning
d) testing TOPIC 1.6 CONSUMER
Answer: c ELECTRONICS
Explanation: It is associated prevention cost. ARCHITECTURE - PLATFORM-
LEVEL PERFORMANCE
7. Who identifies, documents, and verifies
that corrections have been made to the
ANALYSIS
software?
a) Project manager 1. Which of the following allows the reuse of
b) Project team the software and the hardware components?
c) SQA group a) platform based design
d) All of the mentioned b) memory design
c) peripheral design
Answer: c d) input design
Explanation: None.
Answer: a
8. The primary objective of formal technical Explanation: The platform design allows the
reviews is to find _________ during the reuse of the software and the hardware
process so that they do not become defects components in order to cope with the
after release of the software. increasing complexity in the design of
a) errors embedded systems.
b) equivalent faults
c) failure cause 2. Which of the following is the design in
d) none of the mentioned which both the hardware and software are
considered during the design?
Answer: a a) platform based design
Explanation: Errors lead to faults b) memory based design
c) software/hardware codesign
9. What is not included in prevention costs? d) peripheral design
a) quality planning
b) formal technical reviews

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MCQ for Regulations 2017

Answer: c interchanged so that the accesses to array

Explanation: The software/hardware components become more local.
codesign is the one which having both
hardware and software design concerns. This 6. Which design activity helps in the
will help in the right combination of the transformation of the floating point arithmetic
hardware and the software for the efficient to fixed point arithmetic?
product. a) high-level transformation
b) scheduling
3. What does API stand for? c) compilation
a) address programming interface d) task-level concurrency management
b) application programming interface
c) accessing peripheral through interface Answer: a
d) address programming interface Explanation: The high-level transformation
are responsible for the high optimizing
Answer: b transformations, that is, for the loop
Explanation: The platform-based design interchanging and the transformation of the
helps in the reuse of both the hardware and floating point arithmetic to the fixed point
the software components. The application arithmetic can be done by the high-level
programming interface helps in extending the transformation.
platform towards software applications.
7. Which design activity is in charge of
4. Which activity is concerned with mapping operations to hardware?
identifying the task at the final embedded a) scheduling
systems? b) high-level transformation
a) high-level transformation c) hardware/software partitioning
b) compilation d) compilation
c) scheduling
d) task-level concurrency management Answer: c
Explanation: The hardware/software
Answer: d partitioning is the activity which is in charge
Explanation: There are many design of mapping operations to the software or to
activities associated with the platforms in the the hardware.
embedded system and one such is the task-
level concurrency management which helps 8. Which of the following is approximated
in identifying the task that needed to be during hardware/software partitioning, during
present in the final embedded systems. task-level concurrency management?
a) scheduling
5. In which design activity, the loops are b) compilation
interchangeable? c) task-level concurrency management
a) compilation d) high-level transformation
b) scheduling
c) high-level transformation Answer: a
d) hardware/software partitioning Explanation: The scheduling is performed in
several contexts. It should be approximated
Answer: c with the other design activities like the
Explanation: The high-level transformation compilation, hardware/software partitioning,
is responsible for the high optimizing and task-level concurrency management. The
transformations, that is, the loops can be

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

scheduling should be precise for the final Answer: b

code. Explanation: ARM is a type of system
architecture.
9. Which of the following is a process of
analyzing the set of possible designs? 2. The main importance of ARM micro-
a) design space exploration processors is providing operation with
b) scheduling ______
c) compilation a) Low cost and low power consumption
d) hardware/software partitioning b) Higher degree of multi-tasking
c) Lower error or glitches
Answer: a d) Efficient memory management
Explanation: The design space exploration is
the process of analyzing the set of designs Answer: a
and the design which meet the specification is Explanation: The Stand alone feature of the
selected. ARM processors is that they’re economically
viable.
10. Which of the following is a meet-in-the-
middle approach? 3. ARM processors where basically designed
a) peripheral based design for _______
b) platform based design a) Main frame systems
c) memory based design b) Distributed systems
d) processor design c) Mobile systems
d) Super computers
Answer: b
Explanation: The platform is an abstraction Answer: c
layer which covers many possible Explanation: These ARM processors are
refinements to a lower level and is mainly designed for handheld devices.
follows a meet-in-the-middle approach.
4. The ARM processors don’t support Byte
addressability.
a) True
b) False
UNIT II ARM
Answer: b
PROCESSOR AND Explanation: The ability to store data in the
PERIPHERALS form of consecutive bytes.

5. The address space in ARM is ___________

TOPIC 2.1 ARM a) 224
ARCHITECTURE VERSIONS b) 264
c) 216
1. ARM stands for _____________ d) 232
a) Advanced Rate Machines
b) Advanced RISC Machines Answer: d
c) Artificial Running Machines Explanation: None.
d) Aviary Running Machines
6. The address system supported by ARM
systems is/are ___________

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a) Little Endian 10. The additional duplicate register used in

b) Big Endian ARM machines are called as _______
c) X-Little Endian a) Copied-registers
d) Both Little & Big Endian b) Banked registers
c) EXtra registers
Answer: d d) Extential registers
Explanation: The way in which, the data gets
stored in the system or the way of address Answer: b
allocation is called as address system. Explanation: The duplicate registers are used
in situations of context switching.
7. Memory can be accessed in ARM systems
by __________ instructions. 11. The banked registers are used for ______
i) Store a) Switching between supervisor and interrupt
ii) MOVE mode
iii) Load b) Extended storing
iv) arithmetic c) Same as other general purpose registers
v) logical d) None of the mentioned
a) i, ii, iii
b) i, ii Answer: a
c) i, iv, v Explanation: When switching from one
d) iii, iv, v mode to another, instead of storing the
register contents somewhere else it’ll be kept
Answer: b in the duplicate registers and the new values
Explanation: None. are stored in the actual registers.

8. RISC stands for _________ 12. Each instruction in ARM machines is

a) Restricted Instruction Sequencing encoded into __________ Word.
Computer a) 2 byte
b) Restricted Instruction Sequential Compiler b) 3 byte
c) Reduced Instruction Set Computer c) 4 byte
d) Reduced Induction Set Computer d) 8 byte

Answer: c Answer: c
Explanation: This is a system architecture, in Explanation: The data is encrypted to make
which the performance of the system is them secure.
improved by reducing the size of the
instruction set. 13. All instructions in ARM are conditionally
executed.
9. In the ARM, PC is implemented using a) True
___________ b) False
a) Caches
b) Heaps Answer: a
c) General purpose register Explanation: None.
d) Stack
14. The addressing mode where the EA of the
Answer: c operand is the contents of Rn is ______
Explanation: PC is the place where the next a) Pre-indexed mode
instruction about to be executed is stored. b) Pre-indexed with write back mode

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c) Post-indexed mode provides direct high speed interface to a

d) None of the mentioned PC/laptop with speeds up to 12Mb/s.

Answer: c 3. Xbee/Bluetooth/Wifi wireless modules and

Explanation: None. SD/MMC card are included in the board?
a) True
15. The effective address of the instruction b) False
written in Post-indexed mode,
MOVE[Rn]+Rm is _______ Answer: b
a) EA = [Rn] Explanation: Xbee/Bluetooth/Wifi wireless
b) EA = [Rn + Rm] modules and SD/MMC card are not included
c) EA = [Rn] + Rm in the board and it can be separately brought
d) EA = [Rm] + Rn from Net Robotics Website.

Answer: a 4. In LPC 2148 we require separate

Explanation: Effective address is the address programmer?
that the computer acquires from the current a) True
instruction being executed. b) False

Answer: b
TOPIC 2.2 FEATURES OF THE Explanation: The UART boot loader
LPC 214X FAMILY eliminates the need of an additional
PERIPHERALS programmer and allows you to program using
serial port.
1. LPC 2148 pro development board has
5. Which LCD display is present in LPC 2148
_________ on chip memory.
Development Board?
a) 500k
a) 8*8 LED
b) 625k
b) 2*32 LCD
c) 512k
c) 2*16 LCD connected peripherally
d) 425k
d) 2*16 LCD on-chip
Answer: c
Answer: d
Explanation: LPC 2148 Pro Development
Explanation: On-board two line LCD
Board is a powerful development platform
Display (2*16) with jumper selection option
based on LPC2148 ARM7TDMI micro
to disable LCD when not required.
controller with 512k on-chip memory.
6. Does it have in system programming or in
2. The USB controller provides high speed
application programming?
interface to laptop/PC with a speed of
a) True
________
b) False
a) On-chip USB with 12Mb/s
b) On-chip USB with 15Mb/s Answer: a
c) Peripheral USB with 12Mb/s Explanation: In system programming is
d) Peripheral USB with 15Mb/s generally what we do, i.e., using Jtag the
program is dumped in to the board.
Answer: a
In application programming means without
Explanation: The on-chip USB controller
any external devices the program can be

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MCQ for Regulations 2017

changed (which we already written in the Answer: c

original program). Explanation: Using Real view compiler the
keil uVersion 4 is used. Whereas, AVR studio
7. It provides real time debugging with the on 4 is used for ATmega128 microcontroller.
chip real monitor software. And code block is used for c programming.
a) True
b) False 11. ________ bit ARM7TDMI controller is
present?
Answer: a a) 128 bit
Explanation: Embedded ICE RT and b) 8 bit
Embedded Trace Interfaces offer real-time c) 64 bit
debugging with the on chip Real monitor d) 32 bit
software and high speed tracing execution.
Answer: d
8. Who is the founder of LPC2148 board? Explanation: LPC 2148 Pro Development
a) Intel Board is a powerful development platform
b) Atmel based on LPC2148 ARM7TDMI micro
c) Motorola controller with 512k on-chip memory. With a
d) Philips 16-bit/32-bit ARM7TDMI-S microcontroller
is a tiny LQFP64 package.
Answer: d
Explanation: ARM LPC2148 is 12. USB 2.0 full speed compliant device
ARM7TDMI-S core board microcontroller controller with _________ of end point
that uses 16/32-Bit 64 pin(LQFP) RAM.
microcontroller No.LPC2148 from a) 6 kB
Philips(NXP). b) 4 kB
c) 2 kB
9. What is the program counter value when d) 8 kB
the board turns on?
a) 0x00000 Answer: c
b) 0xFFFFF Explanation: The on-chip USB controller
c) Where the previous program ends provides direct high speed interface to a
d) At the location where we write the code PC/laptop with speeds up to 12 Mb/s. USB
2.0 full speed compliant device controllers
Answer: a with 2 kB of end point RAM.
Explanation: Usually the program counter
will store the address of the instruction to be 13. Single 10-bit DAC provides variable
executed but, when we start the board it _________ output.
points to the first address memory location. a) Digital
b) Analog
10. Which IDE is supported by LPC2148 c) Analog and digital
board? d) Neither analog nor digital
a) Code Blocks
b) AVR Studio 4 Answer: b
c) Keil uVersion 4 Explanation: Two 10-bit ADCs provide a
d) Walldorf total of 14 analog inputs whereas single 10-
bit DAC provides variable analog output.

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14. Timer in the board has _________ Answer: c

compare and _________ capture channels. Explanation: The data can be detected by the
a) 3 and 4 local clock reference which is generated from
b) 4 and 3 the baud rate generator.
c) 4 and 4
d) 3 and 3 3. Which of the signal is set to one, if no data
is transmitted?
Answer: c a) READY
Explanation: Two 32-bit timer/external event b) START
counters have four capture and four compare c) STOP
channels each and also a PWM unit with six d) TXD
outputs and a watchdog.
Answer: d
15. What is the operating voltage of the Explanation: The TXD signal goes to logic
board? one when no data is transmitted. When data
a) 5v transmit, it sets to logic zero.
b) 2.5v
c) 3v 4. What rate can define the timing in the
d) 4.5v UART?
a) bit rate
Answer: c b) baud rate
Explanation: Single power supply with POR c) speed rate
and BOD circuits and operated at the supply d) voltage rate
voltage of 3.0 to 3.6v with 5v tolerant I/O
pads. Answer: b
Explanation: The timing is defined by the
baud rate in which both the transmitter and
TOPIC 2.3 UART receiver are used. The baud rate is supplied
by the counter or an external timer called
1. What does UART stand for? baud rate generator which generates a clock
a) universal asynchronous receiver transmitter signal.
b) unique asynchronous receiver transmitter
c) universal address receiver transmitter 5. How is the baud rate supplied?
d) unique address receiver transmitter a) baud rate voltage
b) external timer
Answer: a c) peripheral
Explanation: The UART or universal d) internal timer
asynchronous receiver transmitter is used for
the data transmission at a predefined speed or Answer: b
baud rate. Explanation: The baud rate is supplied by the
counter or an external timer called baud rate
2. How is data detected in a UART? generator which generates a clock signal.
a) counter
b) timer 6. Which is the most commonly used UART?
c) clock a) 8253
d) first bit b) 8254
c) 8259
d) 8250

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 Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

Answer: d 10. Which of the signal can control bus

Explanation: The Intel 8253, 8254 and 8259 arbitration logic in 8250?
are timers whereas Intel 8250 is a UART a) MR
which is commonly used. b) DDIS
c) INTR

M
7. Which company developed 16450? d) RCLK
a) Philips
b) Intel Answer: b

O
c) National semiconductor Explanation: DDIS signal goes low when the
d) IBM CPU is reading data from the UART and it

C
also controls the bus arbitration logic.
Answer: c

T.
Explanation: The Intel 8250 is replaced by
the 16450 and 16550 which are developed by TOPIC 2.4 BLOCK DIAGRAM
the National Semiconductors. 16450 is a chip OF ARM9 AND ARM CORTEX
which can combine all the PC’s input output M3 MCU.

O
devices into a single piece of silicon.
1. What is the processor used by ARM7?

SP
8. What does ADS indicate in 8250 UART?
a) 8-bit CISC
a) address signal
b) 8-bit RISC
b) address terminal signal
c) 32-bit CISC
c) address strobe signal
d) 32-bit RISC
G
d) address generating signal
Answer: d
Answer: c
LO

Explanation: ARM7 is a group 32-bit RISC

Explanation: The ADS is address strobe
ARM processor cores licensed by ARM
signal and is working as active low in 8250
Holdings for microcontroller use.
UART. The ADS signal is used to latch the
address and chip select signals while 2. What is the instruction set used by ARM7?
.B

processor access. a) 16-bit instruction set

b) 32-bit instruction set
9. Which of the following signals are active
c) 64-bit instruction set
low in the 8250 UART?
17

d) 8-bit instruction set

a) BAUDOUT
b) DDIS Answer: a
c) INTR Explanation: ARM introduced the Thumb
d) MR 16-bit instruction set providing improved
-R

code density compared to previous designs.

Answer: a
The most widely used ARM7 designs
Explanation: The BAUDOUT signal is
implement the ARMv4T architecture, but
active low whereas DDIS, INTR and MR are
SE

some implement ARM3 or ARMv5TEJ.

active high in the 8250 UART. BAUDOUT is
the clock signal from the transmitter part of 3. How many registers are there in ARM7?
the UART. DDIS signal goes low when the a) 35 register( 28 GPR and 7 SPR)
CPU is reading data from the UART. INTR is
C

b) 37 registers(28 GPR and 9 SPR)

the interrupt pin. MR is the master reset pin. c) 37 registers(31 GPR and 6 SPR)
d) 35 register(30 GPR and 5 SPR)

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

Answer: c c) ARM71a0
Explanation: ARM7TDMI has 37 d) ARMv4T
registers(31 GPR and 6 SPR). All these
designs use a Von Neumann architecture, thus Answer: b
the few versions comprising a cache do not Explanation: The original ARM7 was based
separate data and instruction caches. on the earlier ARM6 design and used the
same ARM3 instruction set.
4. ARM7 has an in-built debugging device?
a) True 8. What are t, d, m, I stands for in
b) False ARM7TDMI?
a) Timer, Debug, Multiplex, ICE
Answer: a b) Thumb, Debug, Multiplier, ICE
Explanation: Some ARM7 cores are c) Timer, Debug, Modulation, IS
obsolete. It had a JTAG based on-chip d) Thumb, Debug, Multiplier, ICE
debugging; the preceding ARM6 cores did
not support it. The “D” represented a JTAG Answer: b
TAP for debugging. Explanation: The ARM7TDMI(ARM7 + 16
bit Thumb + JTAG Debug + fast Multiplier +
5. What is the capability of ARM7 f enhanced ICE) processor implements the
instruction for a second? ARM4 instruction set.
a) 110 MIPS
b) 150 MIPS 9. ARM stands for _________
c) 125 MIPS a) Advanced RISC Machine
d) 130 MIPS b) Advanced RISC Methadology
c) Advanced Reduced Machine
Answer: d d) Advanced Reduced Methadology
Explanation: It is a versatile device for
mobile devices and other low power Answer: a
electronics. This processor architecture is Explanation: ARM, originally Acorn RISC
capable of up to 130MIPS on a typical 0.13 Machine, later Advanced RISC Machine, is a
um process. family of reduced instruction set computing
(RISC) architectures for computing
6. We have no use of having silicon processors.
customization?
a) True 10. What are the profiles for ARM
b) False architecture?
a) A,R
Answer: b b) A,M
Explanation: It achieve custom design goals, c) A,R,M
such as higher clock speed, very low power d) R,M
consumption, instruction set extension,
optimization for size, debug support, etc. Answer: c
Explanation: ARMv7 defines 3 architecture
7. Which of the following has the same “profiles”:
instruction set as ARM7? A-profile, Application profile
a) ARM6 R-profile, Real-time profile
b) ARMv3 M-profile, Microcontroller profile.

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11. ARM7DI operates in which mode? Answer: a

a) Big Endian Explanation: The ARM7EJ-s processor has a
b) Little Endian Von Neumann architecture. This feature is a
c) Both big and little Endian single 32-bit data bus that carries both
d) Neither big nor little Endian instructions and data. Only load, store, and
swap instructions can access data from
Answer: c memory. Data can be 8- bit.
Explanation: Big Endian configuration,
when BIGEND signal is HIGH the processor 15. What is the cache memory for
treats bytes in memory as being in Big Endian ARM710T?
format. When it is LOW memory is treated as a) 12Kb
little Endian. b) 16Kb
c) 32Kb
12. In which of the following ARM d) 8Kb
processors virtual memory is present?
a) ARM7DI Answer: d
b) ARM7TDMI-S Explanation: The ARM710T is a general
c) ARM7TDMI purpose 32-bit microprocessor with 8Kb
d) ARM7EJ-S cache, enlarged write buffer and memory
management unit combined in a single chip.
Answer: a
Explanation: ARM7DI is capable of running
a virtual memory system. The abort input to
the processor may be used by the memory
manager to inform ARM7DI of page faults. UNIT III EMBEDDED
13. How many instructions pipelining is used PROGRAMMING
in ARM7EJ-S?
a) 3-Stage TOPIC 3.1 COMPONENTS FOR
b) 4-Stage
c) 5-Stage EMBEDDED PROGRAMS-
d)2-stage MODELS OF PROGRAMS-
ASSEMBLY, LINKING AND
Answer: c LOADING, COMPILATION
Explanation: A five-stage pipelining is used,
consisting of Fetch, Decode, Execute,
TECHNIQUES- PROGRAM
Memory, and Writeback stages. A six-stage LEVEL PERFORMANCE
pipelining is used in Jazelle state, consisting ANALYSIS
of Fetch, Jazelle, Execute, Memory, and
Writeback stages. 1. Which of the following are header files?
a) #include
14. How many bit data bus is used in
b) file
ARM7EJ-s?
c) struct()
a) 32-bit
d) proc()
b) 16-bit
c) 8-bit Answer: a
d) Both 16 and 32 bit Explanation: The #include is a header file
which defines the standard constants, variable

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

types, and many other functions. This can a) -c

also include some standard libraries. b) -p
c) -f
2. Which is the standard C compiler used for d) -g
the UNIX systems?
a) simulator Answer: d
b) compiler Explanation: The -g generates the symbolic
c) cc debug information for the debuggers. Without
d) sc this, the debugger cannot print the variable
values, it can only work at the assembler
Answer: c level. The symbolic information is passed
Explanation: The cc is the standard C through the compilation process and stored in
compiler used in the UNIX system. Its the executable file.
command lines can be pre-processed,
compiled, assembled and linked to create an 6. Which of the following is also known as
executable file. loader?
a) locater
3. Which compiling option is used to compile b) linker
programs to form part of a library? c) assembler
a) -c d) compiler
b) -p
c) -f Answer: b
d) -g Explanation: The linker is also known as a
loader. It can take the object file and searches
Answer: a the library files to find the routine it calls.
Explanation: There are several options for
the compilers. The option -c compiles the 7. Which of the following gives the final
linking stage and then leaves the object file. control to the programmer?
This option is used to compile programs to a) linker
form a part of the library. b) compiler
c) locater
4. Which compiling option can be used for d) simulator
finding which part of the program is
consuming most of the processing time? Answer: a
a) -f Explanation: The linker can give the final
b) -g control to the programmer concerning how
c) -p unresolved references are reconciled, where
d) -c the sections are located in the memory, which
routines are used, and so on.
Answer: c
Explanation: The -p instructs the compiler to 8. Which command takes the object file and
produce codes which count the number of searches library files to find the routine calls?
times each routine is called and this is useful a) simulator
for finding the processing time of the b) emulator
programs. c) debugger
d) linker
5. Which compiling option can generate
symbolic debug information for debuggers?

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MCQ for Regulations 2017

Answer: d b) text
Explanation: The linker is also known as a c) video
loader. It can take the object file and searches d) audio
the library files to find the routine it calls. The
linker can give the final control to the Answer: a

M
programmer concerning how unresolved Explanation: 64% of any website’s page is
references are reconciled, where the sections made up of images. The loading speed of the
websites also slows down due to this much

O
are located in the memory, which routines are
used, and so on. contribution of images in a web page. To
reduce this loading time we use web

C
9. Which assembler option is used to turn off performance optimization.
long or short address optimization?

T.
a) -n 2. For image compression which tool is
b) -V helpful?
c) -m a) WordPress cache enable a plugin
d) -o b) Optimus wordpress plugin

O
c) Glup-uglify
Answer: a d) Speed test tool

SP
Explanation: The option -o puts the
assembler into the file obj file, -V can write Answer: b
the assembler’s version number on the Explanation: Optimus WordPress plugin is
standard error output, -m runs the macro used for lossless as well as lossy image
G
preprocessor on the source file and -n turns compression. It automatically reduces the size
off the long or short address optimization. of the file. Reduction in size is possible up to
70%. There are three versions of Optimus i.e.
LO

10. Which assembler option runs the m4 Optimus HQ, Optimus, Optimus HQ PRO.
macro preprocessor on the source file? Speed test tools are used to measure/note
a) -n down your pages speed performance.
b) -m WordPress cache enable a plugin used to
.B

c) -V enable caching.
d) -o
3. HTTP request is between
Answer: b _______________
17

Explanation: The option -o puts the a) client and host

assembler into the file obj file, -V can write b) client and server
the assembler’s version number on the c) server and host
standard error output, -m runs the macro d) user and server
-R

preprocessor on the source file and -n turns

off the long or short address optimization. Answer: a
Explanation: HTTP stands for Hypertext
SE

Transfer Protocol. For fetching, data from

TOPIC 3.2 SOFTWARE server browser uses HTTP request, and in
PERFORMANCE between client and host. The more HTTP
OPTIMIZATION request slower the loading of a page will be.
C

4. What does not come under minification?

1. Major portion of web page contributes
a) removal of comments
_________________
b) removal of new line characters
a) image

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

c) removal of white space characters Answer: a

d) removal of multimedia elements Explanation: TTFB stands for time to the
first byte and measures the responsiveness of
Answer: d server. Its calculation is done as: process
Explanation: For better web performance we request time+ HTTP request time+ HTTP
use removal of unnecessary characters from response time. This speed up the website by
the source code like white space characters, downloading various smaller images through
comments, new line characters, block sockets.
delimiters etc.
8. 404 HTTP error is generated due to
E.g. the given JavaScript code
____________
var arr=[]; for(var i=0;i<10;i++) {arr[i]=i}; }
is equivalent to the code a) missing JavaScript file
for(var arr=[i=0];++i<10;arr[i]=i); b) any missing file
c) slow loading of the web page
5. Which of the following is not render d) on removing the newline character
blocking resource?
a) CSS Answer: b
b) HTML Explanation: HTTP 404 is an error which
c) JavaScript indicates that the client was able to
d) Jquery communicate with the server but the server
could not find the request. Due to missing of
Answer: d any file 404 error is generated, this is a taxing
Explanation: HTML, CSS and JavaScript are error for the page.
render blocking resources to the DOM. To
enhance the speed of your web page these 9. What is the work of Gzip compression?
resources should be properly used. a) compresses an image
b) compresses web pages only
6. For best speed position of JavaScript code c) compresses JavaScript and CSS code only
should be at ______________ d) compresses web pages, JavaScript and
a) top of the code CSS
b) bottom of the code
c) middle of the code Answer: d
d) anywhere in the code Explanation: Basically Gzip compression is
used to compress text data in websites. Gzip
Answer: b compression is very useful in web
Explanation: For better loading time of the performance optimization. It compresses web
page it is always recommended to put pages, JavaScript and CSS. Gzip is also one
JavaScript code at the bottom of the main of the file formats. Gzip compression can be
code of the page before </body> tag. CSS enabled via webserver configuration.
code should be at the beginning of the code. Common webservers where it can me make
enable is .htaccess, Nginx, Apache and
7. What is the work of TTFB? Litspeed.
a) measures the responsiveness of web server
b) increases the load speed of web page 10. What is hotlink protection?
c) compresses the image a) stopping other sites from displaying images
d) remove unnecessary characters b) stopping other sites from displaying videos
c) stopping access of source code
d) compresses an image

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

Answer: a front end of the websites. These are the kind

Explanation: Hotlink protection is a kind of of graphs which shows the order of
tool. Hotlink protection is related to requesting of resources from a browser. One
restricting HTTP, it stops other sites from of the best online tools is WebPageTest.org
displaying images of your webpage. We can also known as WPT.
create a list of hostnames that can access the
resources of our website. 14. Which of the following is not the layer of
the OSI Model?
11. For best speed position of CSS code a) Transport Layer
should be at __________ b) Network Layer
a) at the bottom of the code c) Session Layer
b) at the middle of the code d) Atomic Layer
c) at the top of the code
d) anywhere in the code Answer: d
Explanation: OSI model stands for Open
Answer: c Systems Interconnection model. It is
Explanation: CSS styling and code should be commonly used for representing various parts
placed at the top of the code for best loading of network traffic. There are seven layers in
result of the webpage. JavaScript code should the OSI model, Physical Layer, Data Link
be placed at the bottom of the page for best layer, Network Layer, Transport Layer,
performance and rapid loading speed of the Session Layer, Presentation Layer and
website. Application Layer.

12. What is not the work of database 15. Which browser gives maximum parallel
optimization? connections per host?
a) cleaning out old tables a) Opera 10
b) creating indexes b) Chrome 1 and 2
c) optimize datatype c) Safari 3 and 4
d) delete database d) Firefox 3

Answer: d Answer: a
Explanation: We store various information in Explanation: Parallel downloading is very
the database. A database is a collection of beneficial to performance. Opera 10 provides
tables that contain information. Database the maximum parallel connections per host
delay takes a long waiting time, so there are i.e. 8, Chrome 1 and 2, Chrome 4 to 23 gives
various techniques for database optimization. 6 maximum parallel connections per host,
Database optimization basically optimizes Safari 3 and 4 gives 4 maximum parallel
data types, tables, data size. connections per host, Firefox 3, Firefox 4 to
17 gives 6 maximum parallel connections per
13. Which of the following is the Waterfall host.
tool?
a) WebPageTest.org
b) dotcom-monitor TOPIC 3.3 PROGRAM LEVEL
c) Pingdom Speed Test ENERGY AND POWER
d) GTmetrix ANALYSIS AND OPTIMIZATION
Answer: a
1. Which of the following helps in reducing
Explanation: Waterfall views are useful for
the energy consumption of the embedded

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

system? Answer: c
a) compilers Explanation: Tiwari proposed the first power
b) simulator model in the year 1974. The model includes
c) debugger the so-called bases and the inter-instruction
d) emulator instructions. Base costs of the instruction
correspond to the energy consumed per
Answer: a instruction execution when an infinite
Explanation: The compilers can reduce the sequence of that instruction is executed. Inter
energy consumption of the embedded system instruction costs model the additional energy
and the compilers performing the energy consumed by the processor if instructions
optimizations are available. change.

2. Which of the following help to meet and 5. Who proposed the third power model?
prove real-time constraints? a) Tiwari
a) simulator b) Russell
b) debugger c) Jacome
c) emulator d) Russell and Jacome
d) compiler
Answer: d
Answer: d Explanation: The third model was proposed
Explanation: There are several reasons for by Russell and Jacome in the year 1998.
designing the optimization and compilers and
one such is that it could help to meet and 6. Which compiler is based on the precise
prove the real-time constraints. measurements of two fixed configurations?
a) first power model
3. Which of the following is an important b) second power model
ingredient of all power optimization? c) third power model
a) energy model d) fourth power model
b) power model
c) watt model Answer: c
d) power compiler Explanation: The third model was proposed
by Russell and Jacome in the year 1998 and is
Answer: b based on the precise measurements of the two
Explanation: Saving energy can be done at fixed configurations.
any stage of the embedded system
development. The high-level optimization 7. What does SPM stand for?
techniques can reduce power consumption a) scratch pad memories
and similarly compiler optimization also can b) sensor parity machine
reduce the power consumption and the most c) scratch pad machine
important thing in power optimization are the d) sensor parity memories
power model.
Answer: a
4. Who proposed the first power model? Explanation: The smaller memories provide
a) Jacome faster access and consume less energy per
b) Russell access and SPM or scratch pad memories is a
c) Tiwari kind of small memory which access fastly
d) Russell and Jacome and consume less energy per access and it can
be exploited by the compiler.

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8. Which model is based on precise 1. Which of the following allows the reuse of
measurements using real hardware? the software and the hardware components?
a) encc energy-aware compiler a) platform based design
b) first power model b) memory design
c) third power model c) peripheral design
d) second power model d) input design

Answer: a Answer: a
Explanation: The encc-energy aware Explanation: The platform design allows the
compiler uses the energy model by Steinke et reuse of the software and the hardware
al. it is based on the precise measurements of components in order to cope with the
the real hardware. The power consumption of increasing complexity in the design of
the memory, as well as the processor, is embedded systems.
included in this model.
2. Which of the following is the design in
9. What is the solution to the knapsack which both the hardware and software are
problem? considered during the design?
a) many-to-many mapping a) platform based design
b) one-to-many mapping b) memory based design
c) many-to-one mapping c) software/hardware codesign
d) one-to-one mapping d) peripheral design

Answer: d Answer: c
Explanation: The knapsack problem is Explanation: The software/hardware
associated with the size constraints, that is the codesign is the one which having both
size of the scratch pad memories. This hardware and software design concerns. This
problem can be solved by one-to-one will help in the right combination of the
mapping which was presented in an integer hardware and the software for the efficient
programming model by Steinke et al. product.

10. How can one compute the power 3. What does API stand for?
consumption of the cache? a) address programming interface
a) Lee power model b) application programming interface
b) First power model c) accessing peripheral through interface
c) Third power model d) address programming interface
d) CACTI
Answer: b
Answer: d Explanation: The platform-based design
Explanation: The CACTI can compute the helps in the reuse of both the hardware and
power consumption of the cache which is the software components. The application
proposed by Wilton and Jouppi in the year programming interface helps in extending the
1996. platform towards software applications.

4. Which activity is concerned with

TOPIC 3.4 ANALYSIS AND identifying the task at the final embedded
OPTIMIZATION OF PROGRAM systems?
SIZE- PROGRAM VALIDATION a) high-level transformation
AND TESTING. b) compilation

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

c) scheduling Answer: c
d) task-level concurrency management Explanation: The hardware/software
partitioning is the activity which is in charge
Answer: d of mapping operations to the software or to
Explanation: There are many design the hardware.
activities associated with the platforms in the
embedded system and one such is the task- 8. Which of the following is approximated
level concurrency management which helps during hardware/software partitioning, during
in identifying the task that needed to be task-level concurrency management?
present in the final embedded systems. a) scheduling
b) compilation
5. In which design activity, the loops are c) task-level concurrency management
interchangeable? d) high-level transformation
a) compilation
b) scheduling Answer: a
c) high-level transformation Explanation: The scheduling is performed in
d) hardware/software partitioning several contexts. It should be approximated
with the other design activities like the
Answer: c compilation, hardware/software partitioning,
Explanation: The high-level transformation and task-level concurrency management. The
is responsible for the high optimizing scheduling should be precise for the final
transformations, that is, the loops can be code.
interchanged so that the accesses to array
components become more local. 9. Which of the following is a process of
analyzing the set of possible designs?
6. Which design activity helps in the a) design space exploration
transformation of the floating point arithmetic b) scheduling
to fixed point arithmetic? c) compilation
a) high-level transformation d) hardware/software partitioning
b) scheduling
c) compilation Answer: a
d) task-level concurrency management Explanation: The design space exploration is
the process of analyzing the set of designs
Answer: a and the design which meet the specification is
Explanation: The high-level transformation selected.
are responsible for the high optimizing
transformations, that is, for the loop 10. Which of the following is a meet-in-the-
interchanging and the transformation of the middle approach?
floating point arithmetic to the fixed point a) peripheral based design
arithmetic can be done by the high-level b) platform based design
transformation. c) memory based design
d) processor design
7. Which design activity is in charge of
mapping operations to hardware? Answer: b
a) scheduling Explanation: The platform is an abstraction
b) high-level transformation layer which covers many possible
c) hardware/software partitioning refinements to a lower level and is mainly
d) compilation follows a meet-in-the-middle approach.

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

a) shorter duration job has higher priority

b) longer duration job has higher priority
c) priority does not depend on the duration of
UNIT IV REAL TIME the job
d) none of the mentioned
SYSTEMS
Answer: a
TOPIC 4.1 STRUCTURE OF A Explanation: None.
REAL TIME SYSTEM 5. In which scheduling certain amount of
CPU time is allocated to each process?
1. In real time operating system a) earliest deadline first scheduling
____________ b) proportional share scheduling
a) all processes have the same priority c) equal share scheduling
b) a task must be serviced by its deadline d) none of the mentioned
period
c) process scheduling can be done only once Answer: b
d) kernel is not required Explanation: None.

Answer: b 6. The problem of priority inversion can be

Explanation: None. solved by ____________
a) priority inheritance protocol
2. Hard real time operating system has b) priority inversion protocol
______________ jitter than a soft real time c) both priority inheritance and inversion
operating system. protocol
a) less d) none of the mentioned
b) more
c) equal Answer: a
d) none of the mentioned Explanation: None.

Answer: a 7. Time duration required for scheduling

Explanation: Jitter is the undesired deviation dispatcher to stop one process and start
from the true periodicity. another is known as ____________
a) process latency
3. For real time operating systems, interrupt b) dispatch latency
latency should be ____________ c) execution latency
a) minimal d) interrupt latency
b) maximum
c) zero Answer: b
d) dependent on the scheduling Explanation: None.

Answer: a 8. Time required to synchronous switch from

Explanation: Interrupt latency is the time the context of one thread to the context of
duration between the generation of interrupt another thread is called?
and execution of its service. a) threads fly-back time
b) jitter
4. In rate monotonic scheduling c) context switch time
____________ d) none of the mentioned

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

Answer: c Answer: c
Explanation: None. Explanation: The WCTE is the worst case
execution time which is an upper bound on
9. Which one of the following is a real time the execution times of task. It can be
operating system? computed for certain programs like while
a) RTLinux loops, programs without recursion, iteration
b) VxWorks count etc.
c) Windows CE
d) All of the mentioned 3. For which of the following WCET can be
computed?
Answer: d a) C program
Explanation: None. b) assembly language
c) VHDL
10. VxWorks is centered around d) program without recursion
____________
a) wind microkernel Answer: d
b) linux kernel Explanation: The WCET computing is a
c) unix kernel difficult task for assembly language and for
d) none of the mentioned computing WCTE for any high-level
language without the knowledge of the
Answer: a generated assembly code is impossible.
Explanation: None.
4. The WCET of which component can be
TOPIC 4.2 ESTIMATING computed if the task is mapped to hardware?
a) hardware
PROGRAM RUN TIMES b) task
c) both task and hardware
1. Identify the standard software components d) application manager
that can be reused?
a) application manager Answer: a
b) operating system Explanation: The worst case execution time
c) application software of the hardware can be computed if the task is
d) memory mapped to the hardware which in turn
requires the synthesis of the hardware.
Answer: b
Explanation: There are certain software 5. Which estimation approach is used by Jha
components that can be reused in an and Dutt for hardware?
embedded system design. These are the a) accurate cost and performance value
operating systems, real-time databases and b) estimated cost and performance value
some other forms of middleware. c) performance value
d) accurate cost
2. What does WCTE stand for?
a) wait case execution time Answer: b
b) wait case encoder time Explanation: There are different estimation
c) worst case execution time techniques used. One such is the estimated
d) worst code execution time cost and performance value which is
proposed by Jha and Dutt for hardware. The

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

accurate cost and performance value is c) execution time

proposed by Jain et al for software. d) address accessing time

6. Which estimate approach is more precise? Answer: a

a) estimated cost and performance value Explanation: The base for scheduling
b) accurate cost and performance value algorithm is the WCET, worst case execution
c) performance value and execution time time which is a bound on the execution time
d) estimated cost of tasks. Such computing is undecidable in
the general case, so it is decidable for certain
Answer: b programs only such as programs without
Explanation: The accurate cost and recursion, iteration count, while loops etc.
performance value is possible if interfaces to
software synthesis tools and hardware
synthesis tools exist and is more precise than TOPIC 4.3 TASK ASSIGNMENT
any other methods. AND SCHEDULING
7. Which estimate approach takes more time 1. To schedule the processes, they are
to consume? considered _________
a) accurate value a) infinitely long
b) estimated value b) periodic
c) accurate cost and performance value c) heavy weight
d) estimated cost and performance value d) light weight
Answer: c Answer: b
Explanation: The accurate cost and the Explanation: None.
performance value method is time-consuming
but the other estimating approaches are less 2. If the period of a process is ‘p’, then what
time consuming. is the rate of the task?
a) p2
8. Which estimation technique can be used if
b) 2*p
interfaces to software synthesis tools and
c) 1/p
hardware synthesis tools exist?
d) p
a) performance value
b) estimated cost Answer: c
c) estimated cost and performance value Explanation: None.
d) accurate cost and performance value
3. The scheduler admits a process using
Answer: d __________
Explanation: The accurate cost and a) two phase locking protocol
performance value is possible if interfaces to b) admission control algorithm
software synthesis tools and hardware c) busy wait polling
synthesis tools exist. d) none of the mentioned
9. Which of the following is the base for Answer: c
scheduling algorithm? Explanation: None.
a) WCET
b) time 4. The ____________ scheduling algorithm
schedules periodic tasks using a static priority

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

policy with preemption. __________

a) earliest deadline first a) they can be scheduled by EDF algorithm
b) rate monotonic b) they cannot be scheduled by EDF
c) first cum first served algorithm
d) priority c) they cannot be scheduled by any other
algorithm
Answer: b d) none of the mentioned
Explanation: None.
Answer: c
5. Rate monotonic scheduling assumes that Explanation: None.
the __________
a) processing time of a periodic process is 9. A process P1 has a period of 50 and a CPU
same for each CPU burst burst of t1 = 25, P2 has a period of 80 and a
b) processing time of a periodic process is CPU burst of 35. The total CPU utilization is?
different for each CPU burst a) 0.90
c) periods of all processes is the same b) 0.74
d) none of the mentioned c) 0.94
d) 0.80
Answer: a
Explanation: None. Answer: c
Explanation: None.
6. In rate monotonic scheduling, a process
with a shorter period is assigned __________ 10. A process P1 has a period of 50 and a
a) a higher priority CPU burst of t1 = 25, P2 has a period of 80
b) a lower priority and a CPU burst of 35. Can the processes be
c) higher & lower priority scheduled without missing the deadlines?
d) none of the mentioned a) Yes
b) No
Answer: a c) Maybe
Explanation: None. d) None of the mentioned

7. There are two processes P1 and P2, whose Answer: b

periods are 50 and 100 respectively. P1 is Explanation: None.
assigned higher priority than P2. The
processing times are t1 = 20 for P1 and t2 =
35 for P2. Is it possible to schedule these TOPIC 4.4 FAULT TOLERANCE
tasks so that each meets its deadline using TECHNIQUES , RELIABILITY,
Rate monotonic scheduling? EVALUATION
a) yes
b) no 1. What type of fault remains in the system
c) maybe for some period and then disappears?
d) none of the mentioned a) Permanent
b) Transient
Answer: a
c) Intermittent
Explanation: None.
d) All of the mentioned
8. If a set of processes cannot be scheduled by
Answer: b
rate monotonic scheduling algorithm, then
Explanation: For example many faults in

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

communication systems are transient in 6. Non-occurrence of improper alteration of

nature. information is known as
a) Available Dependability
2. Which of the following approaches are b) Confidential Dependability
used to achieve reliable systems? c) Maintainable Dependability
a) Fault prevention d) Integral Dependability
b) Fault removal
c) Fault tolerance Answer: d
d) All of the mentioned Explanation: Integrity is to keep the original
content safe from alteration.
Answer: d
Explanation: All the options lead to 7. In N-version programming which is the
formation of a reliable system. independent generation of N, the value of N
is
3. A system maintaining its integrity while a) greater than 1
accepting a temporary halt in its operation is b) less than 1
said to be in a state of c) greater than 2
a) Full Fault Tolerance d) less than 2
b) Graceful Degradation
c) Fail Soft Answer: c
d) Fail Safe Explanation: N-version programming
(NVP), also known as multiversion
Answer: d programming or multiple-version dissimilar
Explanation: None. software, is a method or process in software
engineering where multiple functionally
4. Which of the following Error Detection equivalent programs are independently
checks is not a part of Application detection? generated from the same initial specifications.
a) Hardware checks
b) Timing checks 8. In Log-based fault tolerance, logs of
c) Reversal checks undetermined events are saved and replayed
d) Coding checks on failure.
a) True
Answer: a b) False
Explanation: Hardware is a part of
environment detection check. Answer: a
Explanation: None.
5. Exception handling is a type of
a) forward error recovery mechanism 9. All fault-tolerant techniques rely on
b) backward error recovery mechanism a) Integrity
c) All of the mentioned b) Dependability
d) None of the mentioned c) Redundancy
d) None of the mentioned
Answer: a
Explanation: Exception handling is a Answer: c
forward error recovery mechanism, as there is Explanation: All fault-tolerant techniques
no roll back to a previous state; instead rely on extra elements introduced into the
control is passed to the handler so that system to detect & recover from faults.
recovery procedures can be initiated.

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Dept. of ECE www.studymaterialz.in
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10. It is imperative for a communicating 4. A process can enter into its critical section
processes to reach consistent recovery points ____________
to avoid the _________ effect, with backward a) anytime
error recovery mechanism. b) when it receives a reply message from its
a) Static parent process
b) Dynamic c) when it receives a reply message from all
c) Domino other processes in the system
d) Whirlpool d) none of the mentioned

Answer: c Answer: c
Explanation: None. Explanation: None.

5. For proper synchronization in distributed

TOPIC 4.5 CLOCK systems ____________
SYNCHRONISATION a) prevention from the deadlock is must
b) prevention from the starvation is must
1. In distributed systems, a logical clock is c) prevention from the deadlock & starvation
associated with ______________ is must
a) each instruction d) none of the mentioned
b) each process
c) each register Answer: c
d) none of the mentioned Explanation: None.

Answer: b 6. In the token passing approach of

Explanation: None. distributed systems, processes are organized
in a ring structure ____________
2. If timestamps of two events are same, then a) logically
the events are ____________ b) physically
a) concurrent c) both logically and physically
b) non-concurrent d) none of the mentioned
c) monotonic
d) non-monotonic Answer: a
Explanation: None.
Answer: a
Explanation: None. 7. In distributed systems, what will the
transaction coordinator do?
3. If a process is executing in its critical a) starts the execution of transaction
section ____________ b) breaks the transaction into number of sub
a) any other process can also execute in its transactions
critical section c) coordinates the termination of the
b) no other process can execute in its critical transaction
section d) all of the mentioned
c) one more process can execute in its critical
section Answer: d
d) none of the mentioned Explanation: None.

Answer: b 8. In case of failure, a new transaction

Explanation: None. coordinator can be elected by ____________

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

a) bully algorithm Answer: b

b) ring algorithm Explanation: The multitasking operating
c) both bully and ring algorithm system works by dividing the processor’s
d) none of the mentioned time into different discrete time slots, that is,
each application requires a defined number of
Answer: c time slots to complete its execution.
Explanation: None.
2. Which of the following decides which task
9. In distributed systems, election algorithms can have the next time slot?
assumes that ____________ a) single task operating system
a) a unique priority number is associated with b) applications
each active process in system c) kernel
b) there is no priority number associated with d) software
any process
c) priority of the processes is not required Answer: c
d) none of the mentioned Explanation: The operating system kernel
decides which task can have the next time
Answer: a slot. So instead of the task executing
Explanation: None. continuously until completion, the execution
of the processor is interleaved with the other
10. According to the ring algorithm, links tasks.
between processes are ____________
a) bidirectional 3. Which of the following controls the time
b) unidirectional slicing mechanism in a multitasking operating
c) both bidirectional and unidirectional system?
d) none of the mentioned a) kernel
b) single tasking kernel
Answer: b c) multitasking kernel
Explanation: None. d) application manager

Answer: c
Explanation: The multitasking operating
systems are associated with the multitasking
UNIT V PROCESSES AND kernel which controls the time slicing
OPERATING SYSTEMS mechanism.

4. Which of the following provides a time

TOPIC 5.1 MULTIPLE TASKS period for the context switch?
AND MULTIPLE PROCESSES a) timer
b) counter
c) time slice
1. Which of the following works by dividing d) time machine
the processor’s time?
a) single task operating system Answer: c
b) multitask operating system Explanation: The time period required for
c) kernel each task for execution before it is stopped
d) applications and replaced during a context switch is
known as the time slice.

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

5. Which of the following can periodically performed, the current program or task is
trigger the context switch? interrupted, so the processor’s registers are
a) software interrupt saved in a special table which is known as
b) hardware interrupt task control block.
c) peripheral
d) memory 8. Which of the following stores all the task
information that the system requires?
Answer: b a) task access block
Explanation: The multitasking operating b) register
systems are associated with the multitasking c) accumulator
kernel which controls the time slicing d) task control block
mechanism. The time period required for
each task for execution before it is stopped Answer: d
and replaced during a context switch is Explanation: The task control block stores all
known as the time slice. These are the task information that the system requires
periodically triggered by a hardware interrupt and this is done when the context switch is
from the system timer. performed so that the currently running
program is interrupted.
6. Which interrupt provides system clock in
the context switching? 9. Which of the following contains all the
a) software interrupt task and their status?
b) hardware interrupt a) register
c) peripheral b) ready list
d) memory c) access list
d) task list
Answer: b
Explanation: The multitasking operating Answer: b
systems deals with the multitasking kernel Explanation: The ‘ready’ list possesses all
which controls the time slicing mechanism the information regarding a task, that is, all
and the time period required for each task for the task and its corresponding status which is
execution before it is stopped and replaced used by the scheduler to decide which task
during a context switch is known as the time should execute in the next time slice.
slice which are periodically triggered by a
hardware interrupt from the system timer. 10. Which determines the sequence and the
This hardware interrupt provides the system associated task’s priority?
clock in which several interrupts are executed a) scheduling algorithm
and counted before a context switch is b) ready list
performed. c) task control block
d) application register
7. The special tale in the multitasking
operating system is also known as Answer: a
a) task control block Explanation: The scheduling algorithm
b) task access block determines the sequence and an associated
c) task address block task’s priority. It also determines the present
d) task allocating block status of the task.

Answer: a 11. Which can control memory usage?

Explanation: When a context switch is a) operating system

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 Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

b) applications 15. Which of the following can carry

c) hardware information and control task?
d) kernel a) semaphore
b) messages
Answer:d c) flags

M
Explanation: The kernel can control the d) address message
memory usage and it can also prevent the
tasks from corrupting each other. Answer: b

O
Explanation: The messages can carry
12. Which can control the memory sharing information and it can also control the task

C
between the tasks? regarding the real-time operating systems.
a) kernel These are also known as events.

T.
b) application
c) software
d) OS TOPIC 5.2 MULTIRATE
SYSTEMS- PREEMPTIVE

O
Answer: a REALTIME OPERATING
Explanation: The kernel can control memory SYSTEMS- PRIORITY BASED

SP
sharing between tasks which allow sharing
common program modules. SCHEDULING

13. Which of the following can implement the 1. In real time operating system
message passing and control?
G
____________
a) application software a) all processes have the same priority
b) operating system b) a task must be serviced by its deadline
LO

c) software period
d) kernel c) process scheduling can be done only once
d) kernel is not required
Answer: d
Explanation: The kernel can implement the
.B

Answer: b
message passing and control which acts as a Explanation: None.
message passer and controller between the
tasks. 2. Hard real time operating system has
17

______________ jitter than a soft real time

14. How many types of messages are operating system.
associated with the real-time operating a) less
system? b) more
-R

a) 2 c) equal
b) 3 d) none of the mentioned
c) 4
d) 5 Answer: a
SE

Explanation: Jitter is the undesired deviation

Answer: a from the true periodicity.
Explanation: There are two basic types of
messages associated with the real-time 3. For real time operating systems, interrupt
C

operating system. These are semaphores and latency should be ____________

messages. a) minimal
b) maximum

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

c) zero Answer: b
d) dependent on the scheduling Explanation: None.

Answer: a 8. Time required to synchronous switch from

Explanation: Interrupt latency is the time the context of one thread to the context of
duration between the generation of interrupt another thread is called?
and execution of its service. a) threads fly-back time
b) jitter
4. In rate monotonic scheduling c) context switch time
____________ d) none of the mentioned
a) shorter duration job has higher priority
b) longer duration job has higher priority Answer: c
c) priority does not depend on the duration of Explanation: None.
the job
d) none of the mentioned 9. Which one of the following is a real time
operating system?
Answer: a a) RTLinux
Explanation: None. b) VxWorks
c) Windows CE
5. In which scheduling certain amount of d) All of the mentioned
CPU time is allocated to each process?
a) earliest deadline first scheduling Answer: d
b) proportional share scheduling Explanation: None.
c) equal share scheduling
d) none of the mentioned 10. VxWorks is centered around
____________
Answer: b a) wind microkernel
Explanation: None. b) linux kernel
c) unix kernel
6. The problem of priority inversion can be d) none of the mentioned
solved by ____________
a) priority inheritance protocol Answer: a
b) priority inversion protocol Explanation: None.
c) both priority inheritance and inversion
protocol
d) none of the mentioned
TOPIC 5.3 INTERPROCESS
COMMUNICATION
Answer: a MECHANISMS
Explanation: None.
1. What is Inter process communication?
7. Time duration required for scheduling
a) allows processes to communicate and
dispatcher to stop one process and start
synchronize their actions when using the
another is known as ____________
same address space
a) process latency
b) allows processes to communicate and
b) dispatch latency
synchronize their actions without using the
c) execution latency
same address space
d) interrupt latency
c) allows the processes to only synchronize

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Dept. of ECE www.studymaterialz.in
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their actions without communication 6. Which of the following are TRUE for
d) none of the mentioned direct communication?
a) A communication link can be associated
Answer: b with N number of process(N = max. number
Explanation: None. of processes supported by system)
b) A communication link can be associated
2. Message passing system allows processes with exactly two processes
to __________ c) Exactly N/2 links exist between each pair
a) communicate with one another without of processes(N = max. number of processes
resorting to shared data supported by system)
b) communicate with one another by resorting d) Exactly two link exists between each pair
to shared data of processes
c) share data
d) name the recipient or sender of the Answer: b
message Explanation: None.

Answer: a 7. In indirect communication between

Explanation: None. processes P and Q __________
a) there is another process R to handle and
3. Which of the following two operations are pass on the messages between P and Q
provided by the IPC facility? b) there is another machine between the two
a) write & delete message processes to help communication
b) delete & receive message c) there is a mailbox to help communication
c) send & delete message between P and Q
d) receive & send message d) none of the mentioned
Answer: d Answer: c
Explanation: None. Explanation: None.
4. Messages sent by a process __________ 8. In the non blocking send __________
a) have to be of a fixed size a) the sending process keeps sending until the
b) have to be a variable size message is received
c) can be fixed or variable sized b) the sending process sends the message and
d) None of the mentioned resumes operation
c) the sending process keeps sending until it
Answer: c receives a message
Explanation: None. d) none of the mentioned
5. The link between two processes P and Q to Answer: b
send and receive messages is called Explanation: None.
__________
a) communication link 9. In the Zero capacity queue __________
b) message-passing link a) the queue can store at least one message
c) synchronization link b) the sender blocks until the receiver
d) all of the mentioned receives the message
c) the sender keeps sending and the messages
Answer: a don’t wait in the queue
Explanation: None. d) none of the mentioned

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

Answer: b can execute with an average of 5 steps. For

Explanation: None. the execution of the same instruction which
processor is faster?
10. The Zero Capacity queue __________ a) A
a) is referred to as a message system with b) B
buffering c) Both take the same time
b) is referred to as a message system with no d) Insufficient information
buffering
c) is referred to as a link Answer: a
d) none of the mentioned Explanation: The performance of a system
can be found out using the Basic performance
Answer: b formula.
Explanation: None.
3. A processor performing fetch or decoding
11. Bounded capacity and Unbounded of different instruction during the execution
capacity queues are referred to as of another instruction is called ______
__________ a) Super-scaling
a) Programmed buffering b) Pipe-lining
b) Automatic buffering c) Parallel Computation
c) User defined buffering d) None of the mentioned
d) No buffering
Answer: b
Answer: b Explanation: Pipe-lining is the process of
Explanation: None. improving the performance of the system by
processing different instructions at the same
TOPIC 5.4 EVALUATING time, with only one instruction performing
one specific operation.
OPERATING SYSTEM
PERFORMANCE- POWER 4. For a given FINITE number of instructions
OPTIMIZATION STRATEGIES to be executed, which architecture of the
FOR PROCESSES processor provides for a faster execution?
a) ISA
b) ANSA
1. During the execution of the instructions, a c) Super-scalar
copy of the instructions is placed in the d) All of the mentioned
______
a) Register Answer: c
b) RAM Explanation: In super-scalar architecture, the
c) System heap instructions are set in groups and they’re
d) Cache decoded and executed together reducing the
amount of time required to process them.
Answer: d
Explanation: None. 5. The clock rate of the processor can be
improved by _________
2. Two processors A and B have clock a) Improving the IC technology of the logic
frequencies of 700 Mhz and 900 Mhz circuits
respectively. Suppose A can execute an b) Reducing the amount of processing done in
instruction with an average of 3 steps and B one step

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Dept. of ECE www.studymaterialz.in
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c) By using the overclocking method 9. As of 2000, the reference system to find

d) All of the mentioned the performance of a system is _____
a) Ultra SPARC 10
Answer: d b) SUN SPARC
Explanation: The clock rate(frequency of the c) SUN II
processor) is the hardware dependent quantity d) None of the mentioned
it is fixed for a given processor.
Answer: a
6. An optimizing Compiler does _________ Explanation: In SPEC system of measuring a
a) Better compilation of the given piece of system’s performance, a system is used as a
code reference against which other systems are
b) Takes advantage of the type of processor compared and performance is determined.
and reduces its process time
c) Does better memory management 10. When Performing a looping operation, the
d) None of the mentioned instruction gets stored in the ______
a) Registers
Answer: b b) Cache
Explanation: An optimizing compiler is a c) System Heap
compiler designed for the specific purpose of d) System stack
increasing the operation speed of the
processor by reducing the time taken to Answer: b
compile the program instructions. Explanation: When a looping or branching
operation is carried out the offset value is
7. The ultimate goal of a compiler is to stored in the cache along with the data.
________
a) Reduce the clock cycles for a programming 11. The average number of steps taken to
task execute the set of instructions can be made to
b) Reduce the size of the object code be less than one by following _______
c) Be versatile a) ISA
d) Be able to detect even the smallest of b) Pipe-lining
errors c) Super-scaling
d) Sequential
Answer: a
Explanation: None. Answer: c
Explanation: The number of steps required to
8. SPEC stands for _______ execute a given set of instructions is
a) Standard Performance Evaluation Code sufficiently reduced by using super-scaling.
b) System Processing Enhancing Code In this method, a set of instructions are
c) System Performance Evaluation grouped together and are processed.
Corporation
d) Standard Processing Enhancement 12. If a processor clock is rated as 1250
Corporation million cycles per second, then its clock
period is ________
Answer: c a) 1.9 * 10-10 sec
Explanation: SPEC is a corporation that
b) 1.6 * 10-9 sec
started to standardize the evaluation method
of a system’s performance. c) 1.25 * 10-10 sec
d) 8 * 10-10 sec

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

Answer: d a) all processes have the same priority

Explanation: None. b) a task must be serviced by its deadline
period
13. If the instruction, Add R1, R2, R3 is c) process scheduling can be done only once
executed in a system that is pipe-lined, then d) kernel is not required
the value of S is (Where S is a term of the
Basic performance equation)? Answer: b
a) 3 Explanation: None.
b) ~2
c) ~1 2. Hard real time operating system has
d) 6 ______________ jitter than a soft real time
operating system.
Answer: c a) less
Explanation: S is the number of steps b) more
required to execute the instructions. c) equal
d) none of the mentioned
14. CISC stands for _______
a) Complete Instruction Sequential Answer: a
Compilation Explanation: Jitter is the undesired deviation
b) Computer Integrated Sequential Compiler from the true periodicity.
c) Complex Instruction Set Computer
d) Complex Instruction Sequential 3. For real time operating systems, interrupt
Compilation latency should be ____________
a) minimal
Answer: c b) maximum
Explanation: CISC is a type of system c) zero
architecture where complex instructions are d) dependent on the scheduling
grouped together and executed to improve
system performance. Answer: a
Explanation: Interrupt latency is the time
15. As of 2000, the reference system to find duration between the generation of interrupt
the SPEC rating are built with _____ and execution of its service.
Processor.
a) Intel Atom SParc 300Mhz 4. In rate monotonic scheduling
b) Ultra SPARC -IIi 300MHZ ____________
c) Amd Neutrino series a) shorter duration job has higher priority
d) ASUS A series 450 Mhz b) longer duration job has higher priority
c) priority does not depend on the duration of
Answer: b the job
Explanation: None. d) none of the mentioned

Answer: a
TOPIC 5.5 EXAMPLE REAL Explanation: None.
TIME OPERATING SYSTEMS-
POSIX-WINDOWS CE 5. In which scheduling certain amount of
CPU time is allocated to each process?
a) earliest deadline first scheduling
1. In real time operating system
b) proportional share scheduling
____________

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

c) equal share scheduling 10. VxWorks is centered around

d) none of the mentioned ____________
a) wind microkernel
Answer: b b) linux kernel
Explanation: None. c) unix kernel
d) none of the mentioned
6. The problem of priority inversion can be
solved by ____________ Answer: a
a) priority inheritance protocol Explanation: None.
b) priority inversion protocol
c) both priority inheritance and inversion
protocol TOPIC 5.6 DISTRIBUTED
d) none of the mentioned EMBEDDED SYSTEMS -
MPSOCS AND SHARED
Answer: a MEMORY MULTIPROCESSORS.
Explanation: None.

7. Time duration required for scheduling TOPIC 5.7 DESIGN EXAMPLE -

dispatcher to stop one process and start
another is known as ____________
AUDIO PLAYER, ENGINE
a) process latency CONTROL UNIT VIDEO
b) dispatch latency ACCELERATOR
c) execution latency
d) interrupt latency 1. Which of the following allows the reuse of
the software and the hardware components?
Answer: b
a) platform based design
Explanation: None.
b) memory design
c) peripheral design
8. Time required to synchronous switch from
d) input design
the context of one thread to the context of
another thread is called?
Answer: a
a) threads fly-back time
Explanation: The platform design allows the
b) jitter
reuse of the software and the hardware
c) context switch time components in order to cope with the
d) none of the mentioned increasing complexity in the design of
embedded systems.
Answer: c
Explanation: None. 2. Which of the following is the design in
9. Which one of the following is a real time which both the hardware and software are
operating system? considered during the design?
a) RTLinux a) platform based design
b) VxWorks b) memory based design
c) software/hardware codesign
c) Windows CE
d) peripheral design
d) All of the mentioned
Answer: c
Answer: d
Explanation: The software/hardware
Explanation: None.
codesign is the one which having both

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

hardware and software design concerns. This 6. Which design activity helps in the
will help in the right combination of the transformation of the floating point arithmetic
hardware and the software for the efficient to fixed point arithmetic?
product. a) high-level transformation
b) scheduling
3. What does API stand for? c) compilation
a) address programming interface d) task-level concurrency management
b) application programming interface
c) accessing peripheral through interface Answer: a
d) address programming interface Explanation: The high-level transformation
are responsible for the high optimizing
Answer: b transformations, that is, for the loop
Explanation: The platform-based design interchanging and the transformation of the
helps in the reuse of both the hardware and floating point arithmetic to the fixed point
the software components. The application arithmetic can be done by the high-level
programming interface helps in extending the transformation.
platform towards software applications.
7. Which design activity is in charge of
4. Which activity is concerned with mapping operations to hardware?
identifying the task at the final embedded a) scheduling
systems? b) high-level transformation
a) high-level transformation c) hardware/software partitioning
b) compilation d) compilation
c) scheduling
d) task-level concurrency management Answer: c
Explanation: The hardware/software
Answer: d partitioning is the activity which is in charge
Explanation: There are many design of mapping operations to the software or to
activities associated with the platforms in the the hardware.
embedded system and one such is the task-
level concurrency management which helps 8. Which of the following is approximated
in identifying the task that needed to be during hardware/software partitioning, during
present in the final embedded systems. task-level concurrency management?
a) scheduling
5. In which design activity, the loops are b) compilation
interchangeable? c) task-level concurrency management
a) compilation d) high-level transformation
b) scheduling
c) high-level transformation Answer: a
d) hardware/software partitioning Explanation: The scheduling is performed in
several contexts. It should be approximated
Answer: c with the other design activities like the
Explanation: The high-level transformation compilation, hardware/software partitioning,
is responsible for the high optimizing and task-level concurrency management. The
transformations, that is, the loops can be scheduling should be precise for the final
interchanged so that the accesses to array code.
components become more local.

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Dept. of ECE www.studymaterialz.in
MCQ for Regulations 2017

9. Which of the following is a process of 10. Which of the following is a meet-in-the-

analyzing the set of possible designs? middle approach?
a) design space exploration a) peripheral based design
b) scheduling b) platform based design
c) compilation c) memory based design
d) hardware/software partitioning d) processor design

Answer: a Answer: b
Explanation: The design space exploration is Explanation: The platform is an abstraction
the process of analyzing the set of designs layer which covers many possible
and the design which meet the specification is refinements to a lower level and is mainly
selected. follows a meet-in-the-middle approach.

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