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AI-OBC: Conceptual Design of a Deep Neural Network based Next Generation

Onboard Computing Architecture for Satellite Systems

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 AI-OBC: Conceptual Design of a Deep Neural
Network based Next Generation Onboard
Computing Architecture for Satellite Systems
Rashedul Huq
Dept.of ECE Monirul Islam Shahnewaz Siddique
North South University Dept.of ECE Dept.of ECE
Dhaka, Bangladesh North South University North South University
[email protected] Dhaka, Bangladesh Dhaka, Bangladesh
[email protected] [email protected]

Abstract—The latest developments in embedded processing On the other hand, the constraints of the space domain
and hardware based low powered artificial intelligence (AI) conflict with the desire for more computing power. Satellite
accelerators employing Deep Neural Network (DNN) have not systems in general have strong requirements to durability and
been implemented in existing real-time computing architecture reliability. This leads to very conservative design decisions.
designs for Nano and microsatellites. The objective of this paper Only qualified components, usually radiation hardened are
is to present a new conceptual design for a real time Deep used, which have predominantly lower performance and are
Learning based on-board computing architecture, which has an of older technologies than current commercial available
onboard Software Defined Radio (SDR) and a low powered components.
Deep Learning module. The concept presented in this paper
simplifies the interfacing between the different modules and is Furthermore, today’s Onboard Computer (On-board
power efficient. AI-OBC will achieve these additional AI and computer) design concepts waste available computing power
image-processing operations by combining high performance on a satellite system by considering redundancy only on
commercial off-the-shelf (COTS) hardware components with subsystem level. Most satellite systems are not developed in a
the latest hardware based low powered AI accelerators and comprehensive approach regarding the OBC. Most
SDR. subsystems, i.e. attitude and orbit control, different payload
sensors, data handling, communications etc., are developed as
Keywords—Artificial Intelligence, Computing Architecture,
independent systems. Every unit comes with its own OBC and
Deep Neural Network, Satellite Systems, Software Defined Radio,
every computing unit has usually its own cold and hot
Embedded Systems, CubeSat Space Protocol.
redundant counterpart. That means a failing OBC of a
I. INTRODUCTION subsystem cannot be replaced by another OBC from another
subsystem. Hence, a lot of computational resources remain
Future and current space missions face enormous unused.
challenges and difficulties in several technical and processing
domains. One is the onboard data processing in both earth These design restrictions impede the provision of adequate
observation satellites and robotics. The generation computing power for future space missions. New designs need
improvement of sensor systems on satellites such as multi and to be found.
hyper spectral cameras and other specialized sensors has
In this paper, we present a new conceptual design of a deep
increased exponentially. Additionally, due to limited
neural network based next generation onboard computing
communication bandwidth to the ground station and lack of
architecture called AI-OBC (Artificial Intelligent – Onboard
flexibility to use different alternative radios, the need for
Computer). The functional requirements of the design are
onboard SDR (Software Defined Radio) are growing as well.
achieved by building a distributed on-board architecture that
In the field of robotic exploration, e.g., deep space probes consists of different processing components like the primary
or rovers, a higher degree of automation is required to support CPU, the Visual Processing Unit (VPU) for the deep neural
complex calculations and tasks to expand scientific activities. network acceleration and Specialized Field-Programmable
Current operations are limited due to small communication Gate Arrays (FPGAs) for SDR, all connected via a network
bandwidth and the long commanding delays. Therefore, level delivery protocol called the CubeSat Space Protocol
powerful onboard processing coupled with machine learning (CSP) over a physical communication protocol called the
is required to handle and process several sensor data and to Inter-Integrated Circuit (I2C). This system enables the use of
support complex control algorithms. machine learning and computer vision to train models on the
huge amounts of data collected from external and internal
Another field that requires our attention is the field of sensors of the satellite to analyze, classify and train in real
satellite image classification and analysis. Currently, all the time. To further increase the capabilities of communication,
processing and classification of sensor data is done on earth the utilization of SDR is also evaluated. To reduce costs and
after transmission from the satellite. This requires high increase computing performance, Commercial Off-The-Shelf
bandwidth and is inefficient as not all data or images is useful. (COTS) parts and current available technologies was assessed.
However, when onboard machine learning based image and
data classification system is implemented, it provides the The remainder of this paper describes the envisioned
necessary computing performance in proximity to the sensor architecture and is structured as follows. The next section
and in real time, making it perform efficiently with low system gives a short overview of the related literature. Section 3
resources. presents the conceptual design of AI-OBC architecture, its
components and subsystems and their reasons for choice from
the hardware point of view, followed by the software acquisition as well as a backup system in case of emergency
components implementation in Section 4. In Section 5, system for the communication link. A set of sensor modules also will
integration of the hardware is discussed, with system be built on board to expand its area of operation. Most
operation explained in Section 6. Finally, Section 7 gives the importantly, there will be a built in Neural Compute Module
conclusion of the paper. (VPU) for advance AI and Deep Learning based operations in
the field of Image Processing and advanced cube & micro
II. LITERATURE REVIEW satellite operations. We also want to have state-of-the-art
There is a long history in using commercial parts for space reliable memory and storage options in AI-OBC, so we will
applications. NASA decided to leverage the exponential use dual memory of STT-MRAM and ECC RAM and eUFS
growth in commercial silicon technology already in the 80s of as the storage.
the last century [1]. Nowadays, the COTS industry is growing
rapidly and almost all CubeSat systems use COTS parts for
their OBC and other modules.
After reviewing several commercial OBC in the market,
we found that nearly everyone uses the ARM-M series
architecture for their CubeSat OBCs main processor, mainly
the ARM M3 or M4. The ARM M4 [2] microprocessor is
being widely used in current OBC designs but the processor is
outdated and there are more advanced and later models of
microprocessor of the M-series architecture that could give
more better performance and functionality.
Vision Processing Unit (VPU) is emerging class of
microprocessors. It is a specific type of AI accelerator
designed to accelerate machine vision tasks as described on
[3]. There are very limited number of VPUs that is
commercially available in the market more and more
companies are planning to bring it to the market. The Figure 1: Block diagram of AI-OBC
application of VPU are mainly suitable for running machine-
learning applications to train DNN for analyze and
classification of images [4], [5], [6].
A. Main Processor
Electrical Power System (EPS) is a network of electrical
The main processor is the brain of the satellite and
components deployed to supply, transfer and use electrical
performs every operations of the satellite. After reviewing
power in CubeSat. We reviewed several EPS solutions [7] that
is available commercially to understand the functionality and several models of OBC that are available commercially, we
importance of this subsystem. concluded that present architecture uses ARM Cortex M4 [1]
or M3 processor, which is quite outdated. Therefore, for our
Software-defined radio (SDR) is a radio communication design, we intend to use the latest processor, ARM Cortex M7
system where components that have been typically [2] for the role of the main processor. The processor is based
implemented in hardware are instead implemented by means on the ARMV7E-M architecture. The advantage of this
of software on an embedded system. We studied several processor compared to the previous one, is that it is almost
commercial available SDR used in CubeSat such as in [9]. twice as fast as M4 but with the same power consumption of
Present applications and uses of SDR in CubeSat was also M4. The Branch Predictor on the Cortex M7 allows executing
studied in [10], [11]. branches faster than the M4. It has also two units for reading
data from memory, meaning it is able to read memory twice
As for memory, [12] was reviewed to gather information as fast. It has also double-precision floating-point support
on current memory use in CubeSat. Information on the current compared to the one in the M4.
use of storage in CubeSat was gathered from [13]. For the
different sensors onboard an OBC, [14], [15] was analyzed
and reviewed for current commercially available seasons.
Lastly, for the software for CubeSat such as the OS and
typical application software, [16] and [6] was reviewed to
learn about the present software used and to know how to
implement machine-learning on a real time operating system
used in CubeSat.
III. CONCEPTUAL DESIGN
Figure shown below is the block diagram of the proposed
design of AI-OBC. This OBC will have some additional
devices and modules built-in relative to the other CubeSat
OBCs to provide new and improved facilities for developing
next generation CubeSats. It will have two built in radios. One Figure 2: Overview of Cortex-M7 processor. [2]
is dedicated for the Telemetry & Telecommand and the other
one is a Software Defined Radio (SDR) functioning for data
B. VPU/Neural Compute Module and self-guided satellite system that can revolutionize future
micro or Nano satellite systems.
D. ADCS Assist module
The ADCS Assist module in our design is the sub-module
of the OBC, comes with an embedded array of sensors and
I/O ports with interface control, for assisting the ADCS of the
satellite system. The data gathered by the sensors will be
stored and logged in the OBC’s storage for later research. We
are proposing several sensors for data collection. They are:-

 Temperature: - For accurate temperature

measurements between 0.1 to 1℃ across a range of -
200 to 600℃, we are proposing a Resistance
Temperature Detector (RTD) sensor. This would give
us a highly precise temperature data of the internal
circuitry of the OBC in space.
Figure 3: Block diagram of Mariad 2 VPU. [13]
 Gyroscope and Accelerometer: - This AI-OBC needs
to have a built-in Gyroscope and accelerometer chip to
Vision processing Unit or VPU is a type of gather angular and movement data. So we are
microprocessor aimed at accelerating machine learning and proposing a built-in gyro & accelerometer chip for this
artificial intelligence technologies. It is a specialized AI-OBC as many of the satellite OBC [14] already
processor that is made to support tasks like image processing, have. This chip will help us to understand and gather
classification etc. For this, we have chosen the Intel Movidius behavioral data of the satellite OBC and as well as the
satellite itself. This will help us to develop more
Myriad 2 VPU [13], contained in the Intel Movidius Neural
advance reliable OBC and also the whole micro and
Compute Stick [3]. It has an ultra-low power design and Nano satellite systems.
contains a programmable architecture, with a small-area
footprint. It will be used for advanced computer vision  Onboard GPS/SPS- For accurate satellite positioning
applications for onboard analysis and classification of through GPS, we are proposing to include a single chip
satellite images, which has been never used in an onboard GPS receiver onboard with a passive antenna [17]. It
satellite system. will offer very low power consumption, high
sensitivity, and best in class signal acquisition and
C. EPS time-to-first-fix performance.
 Geiger Counter/ Radiation meter- For measuring the
radiation levels of both inside and outside the CubeSat
structure, we are proposing to include a digital
radiation meter which will monitor the radiation levels
and trigger alarms if the level becomes too high,
prompting the system to shut down to prevent any
damage [18].
Additionally, we are proposing an ADCS interface
controller with I/O ports in the module, which would transmit
the signal received from the above sensors to the
microcontroller of the ADCS module for processing. It would
also monitor and distribute power supply coming from the
Figure 4: Basic Block diagram of satellite EPS EPS subsystem to the ADCS. In case of ADCS failure, this
assist module can act as an interface for the main OBC
microprocessor to take control and carry out the minimum
Electric Power System (EPS) is a mandatory part for any tasks of the ADCS.
satellites. Generally the satellites have its own separate
Electric Power system module. There are also some satellite
OBCs that have an on-board built-in EPS. For any advance
and complete satellite on-board computer, it needs to have its
own on-board EPS. In this AI-OBC we have also include an
on-board EPS in the design to reduce the dependency of the
computer. Our aim is to control the EPS with Neural Compute
Module and AI so we need to have the built-in EPS to reduce
the system and operational complexity and also increase the
system’s processing performance. If we are able to control the
EPS by the Neural Compute Module, it will help us to create
an opportunity to develop a semi-autonomous self-powered
E. UHF/VHF Transciever for transmitting and receiving data to/from the ground station.
In future, this module can also be used for inter-satellite link
wireless communications in a constellation. The SDR will
contain one set of primary transceiver for communication with
the ground station, and an additional transceiver for telemetry
backup or emergency purpose can be used as inter-satellite
link. If our dedicated telemetry transceiver cannot fulfill the
specific telemetry requirements, we can also use the backup
channel of the SDR for telemetry and telecommand where the
SDR have the freedom to choose the carrier frequency and as
well as the transmission & and modulation scheme.
To handle this task, the SDR will contain a specialized
Figure 5: Diagram of satellite Telemetry Transceiver Radio-Frequency System-on-Chip (RFSoC) powering the
system. This is necessary, as our OBC will be required to
handle the transmission of enormous data computed by the
onboard Deep Neural Network (DNN) to the ground station
This AI-OBC will also have a built-in fixed RF chip over a short period in orbit. We are proposing an RFSoC from
(TxRx) dedicated for satellite telemetry & telecommand the Zynq UltraScale+ RFSoC family by Xilinx Inc. From the
channel. Telemetry & telecommand channel is the lifeline of datasheet [19] provided, it is understood that it integrates
any satellite. This telemetry channel needs to be very stable multi-giga-sample RF data converters and soft-decision
and reliable. As we are using an advanced radio system (SDR) forward error correction into a SoC (System-on-Chip)
in our design, although it may have some complications on architecture. Complete with an ARM Cortex A53 processing
normal operations, we are not fully satisfied for using the SDR subsystem, scalable programming logic, and the highest signal
as a telemetry channel. We need a stable and fixed on-board processing bandwidth, it is an ideal SoC for our particular
built-in transceiver (TxRx) for this vital communication requirements. This will dramatically reduce the size, weight,
channel. Another objective of this AI-OBC is to ensure an on- power consumption and cost of SDR in satellites, which
board operational radio channel with a minimum required RF requires flexible communication options without sacrificing
output power. We have studied and found that, in most cases high data transmit rate.
for CubeSat (with altitude of around 400km) requires 0.5-2W
RF output power for satellite to ground telemetry The RF output power of the SDR will be very low so it
communication. In our design, we will try to ensure around may require a RF amplifier for achieving some specific link
1W on-board RF output power. Although, it will increase the budget. The OBC will have two on-board dedicated RF output
power consumption of the AI-OBC, we think that it will port (2Tx & 2Rx) so that we can connect the antenna
decrease the total power consumption of the satellite connector or amplifier input connector to the AI-OBC.
compared to adding an external transceiver with complex sub
G. Memory
modules not optimized for the system. This RF module will
have an on-board RF output port direct to the satellite antenna After reviewing multiple commercial OBC designs, we
module dedicated for the telemetry & telecommand channel. concluded that the present designs allocate inadequate
If any satellite requires having higher RF output power, it just capacity of memory into their systems and the memory
needs to connect an additional RF amplifier. In this case, we technologies are outdated. To overcome these limitations, we
are proposing to use the UHF channel for downlink and VHF are proposing two different types of memory storage with
channel for uplink for a better telemetry communication. varying capacity and mechanism. This would enable the
system to store and process different applications and
F. SDR (RF Chip) workloads in their own dedicated appropriate memory,
making the system operate efficiently. It would also protect
the system in case of memory failure, by having a backup
memory for the core system tasks.
Primarily, our proposed system will contain a non-
volatile memory [14] i.e. it does not require power to hold
data, a specialized version of MRAM called STT-MRAM
with a total of 512MB capacity, comprising of two blocks of
256MB. This memory will be used to store the customized
core OS files of the satellite, so that in case of system failure
due to radiation and other risks, the core files can be
recovered. MRAM (magnetoresistive random access
memory) is a method of storing data bits using magnetic
states instead of the electrical charges used by dynamic
random access memory (DRAM). STT-MRAM (spin transfer
torque magnetoresistive random access memory) is an
Figure 6: SDR Transceiver conceptual block diagram.[8] advanced type of MRAM that enables higher densities, low
power consumption and reduced cost compared to regular
In completing our OBC architectural design, we are
proposing a Software Defined Radio (SDR) module [8], MRAM. The main advantage of STT-MRAM over MRAM
which will act as our dedicated data communication channel is the ability to scale the STT-MRAM chips to achieve higher
densities at a lower cost. Since MRAM can perform read and
write operations faster than DRAM using less power, while
being a nonvolatile memory. It is considered a "universal
memory" that can be applied to any use, from system
computing to storage. Unlike the current most popular
nonvolatile memory type, flash memory, MRAM does not
wear out and can be read from and written to theoretically
until the physical material degrades, which is ideal for
satellite use.
For the volatile memory, our system will contain ECC
RAM of total 6GB capacity, comprising of three blocks of
2GB capacity. This part of the memory is dedicated for the
use of system applications of the satellite. Error-correcting
code memory (ECC memory) is a type of computer data
storage that can detect and correct the most common kinds of
internal data corruption. ECC memory is used in most
Figure 7: Diagram of Real-Time OS Architecture.
computers where data corruption cannot be tolerated under
any circumstances [14]. Typically, ECC memory maintains a
memory system immune to single-bit errors: the data that is With even more processing modules compared to high
read from each word is always the same as the data that had performance consumer computers, the area of grid or cloud
been written to it, even if one or more bits actually stored have computing is not enough. Even if this high numbers of
been flipped to the wrong state. This makes it ideal for use in processors are not relevant today for embedded systems,
space as radiation causes data corruption, resulting in system especially for space applications, similar issues will also arise
failure. in this domain eventually. One trend that is seen in this field
H. Storage is the development of new operating system approaches [21].
After evaluating a large variety of existing commercial and
Data storage is an important part of any system, and for
academic operating systems, that are targeting embedded
our system, it is extremely obligatory. Since, in our design, we
are aiming to perform DNN training onboard the satellite, our real-time systems, we concluded that none of these systems
storage capacity should be significant to store enormous data can provide all features or run efficiently on the functional
collected from the sensors and cameras onboard the satellite, requirements of the design. Even the support of multi-core
and have very low latency. By analyzing different storage embedded systems can be rarely found. In addition, if the
technologies and commercial available product, we have strong requirements regarding use of machine learning
concluded that the storage for our design will be using the applications, stability, real-time capabilities, and
eUFS 2.1 (Embedded Universal Flash Storage) [20] synchronicity are considered, no available operating system
technology with a capacity of 512GB, manufactured using the is suitable in this context without large modifications.
V-NAND technology by Samsung.
On the other side, some envisioned machine-learning
UFS is designed to be the most advanced standard
applications does support Linux but not specifically designed
for both embedded and removable Flash memory-based
storage in devices where power is limited without to be fully compatible for real-time operating systems. Hence,
compromising speed and reliability. UFS offers a low we are proposing that our architecture will run on a complete
active power level and a near-zero idle power level, which, customized version of RTOS (Real Time Operating System),
combined with the power-saving attributes of the related called iRTOS. It will be built from the ground up for AI and
MIPI specifications, allows for significant reductions in machine learning applications for use in the space domain,
device power consumption. The UFS standard adopts the supporting the ARMV7E-M architecture with future support
well-known SCSI Architecture Model and command for the ARMV8-M architecture. It will be based on Debian
protocols supporting multiple commands with command with support for Linux kernels, which would mean existing
queuing features and enabling a multi-thread programming Linux kernels used for machine learning applications could
paradigm. This differs from conventional Flash-based be ported easily to the iRTOS. With a command line interface,
memory cards and embedded Flash solutions which process for minimum use of system resources, iRTOS will be open
one command at a time, limiting random read/write access source so that developers all over the world can change and
performance. The chosen storage offers a sequential read modify the system codes for their own real-time machine
speed of 880MB/s and a sequential write speed of learning applications. The memory management of iRTOS
200MB/s, with a IOPS (Input/Output Operations Per Second) will be based upon the efficient use of MRAM, which will be
of 47,000. A maximum of 3.3V and a minimum of 1.8V is its used in our architecture. The machine learning applications
power requirements, which makes it ideal for our specific of iRTOS would be based upon the widely used TensorFlow
system power requirements. [22] framework, which comes with strong support for
IV. SOFTWARE machine learning and deep learning and the flexible
numerical computation core of AI accelerators used in our
In addition to the hardware architecture, the supporting
hardware design architecture. As for security, iRTOS will
software is also important. This includes new concepts with
respect to space domain for real-time operating system implement hardware based full disk encryption, where the
(RTOS) and AI application software. symmetric encryption key will be stored separately from the
microprocessor, thus removing memory as a potential attack
vector for unauthorized access from ground stations and other bus. Finally, it gives substantial advantages to the architecture
potential access points. for machine learning involving huge amounts of data moving
between the subsystems and the ability to operate and control
V. SYSTEM INTEGRATION all nodes from Ground Station.
System integration is defined in engineering as the process
of bringing together the component sub-systems into one Next, we are going to define the I/O ports of the OBC. I/O
system and ensuring that the subsystems function together as ports are sockets that is used to connect any peripheral device
a complete whole system. To accomplish this, we need a high- into the system via a hardware communication interface, in
speed hardware communication protocol by which all the this case, the I2C bus running CSP.
components can communicate internally with each other.
Another aspect of system integration is the need of I/O ports We are proposing eight UART (universal asynchronous
by which external components can communicate with the receiver-transmitter) ports with combinations of single, dual,
OBC. quadruple and octal UART’s for various communication
devices that could be or presently used in a CubeSat. Since
the transmission data speeds go high as 25Mbits/s, and is
configurable, these ports would be significantly useful for
transmission of large data sets for machine learning
applications. In the future, optical inter-satellite
communication devices can also be added.

For the USB, we are proposing six USB3.2 Type A ports

for maximum compatibility and the fastest data transmission
speed of 2.5Gbit/s. These ports will be used for connecting
hyperspectral cameras and DNN accelerator devices to the
system, which will make use of the high data speeds.

Lastly, we are proposing two sets of GPIO (General-

purpose input/output) ports onboard the OBC board for
maximum range of experimental devices that can be
Figure 8: Diagram of AI-OBC Architecture connected to the system. The first set will contains a 40 GPIO
ports while the second set will contain 20 GPIO ports. The
After reviewing and comparing several system bus small set will be dedicated to the EPS subsystem and the
standards, with attention given to compare data rate speeds larger set for general use. This division declutters and
and compatibility, we have concluded that AI-OBC will be simplifies the connections in the GPIO ports.
using the well-known and widely used I2C Rev.6 [23] as the
physical layer system bus with CSP (CubeSat Space VI. SYSTEM OPERATION
Protocol) [24] added as a network layer delivery protocol. Satellite systems are generally engaged in the collection
and transfer of information or commands among all of their
I²C (Inter-Integrated Circuit) is a synchronous, multi- subsystems. The OBC is at the heart of this data transfer and
master, multi-slave, packet switched, single- acts as the onboard communication link between all other
ended, serial computer bus invented by Philips subsystems.
Semiconductor (now NXP Semiconductors). It is widely
In our proposed system, the I2C system bus protocol
used for attaching peripheral ICs to processors handles all the communication between the peripherals and
and microcontrollers in short-distance, intra-board the subsystems. In the physical layer, the hardware
communication. It has several data speed modes with components contains all the physical electronic components
maximum of 5Mbit/s and a minimum of 400kbit/s, which can that are located on the PCB. The primary processor of the
be efficiently used for different components. CubeSat Space OBC acting as a control center is connected to each of the
Protocol (CSP) is a small protocol stack written in C. CSP is subsystems such as the dual memory and the high-speed
designed to ease communication between distributed storage. A secondary processor, called the VPU will be
embedded systems in smaller networks, such as on CubeSat. embedded onto the PCB, not only just to have a direct link to
The design follows the TCP/IP model and includes a the main CPU but also to share the system resources of the
transport protocol, a routing protocol and several MAC-layer entire OBC. This processor will be used to train complex
interfaces. The core includes a router, a socket buffer pool neural networks using machine learning for the targeted
and a connection-oriented socket API. CSP enables applications. The third microprocessor to be embedded into
distributed embedded systems to deploy a service-oriented the PCB of the OBC is the RF chip, overseeing the complex
network topology. This topology eases the design of satellite operations of the SDR, which will be used as a dedicated
subsystems, since the I2C itself is the interface to other telemetry and tele command channel for failure-proof direct
subsystems. This means that each subsystem developer only communication from the ground station, using the dedicated
UHF/VHF antennas. As for the memory, our proposal is to use
needs to define a service-contract, and a set of port numbers
dual memory types, each for a different purpose and
their system will be responding on. Furthermore, subsystems
independent to each other, so that in case of critical system
inter-dependencies is reduced, and redundancy is easily failure, it will act as a backup system. For the storage, we fitted
added by adding multiple similar nodes to the communication the system with the fastest flash storage, which is required for
storing large volume of data gathered by the payload. [2] “ARM Cortex-M7 Processor Technical Reference,” ARM Cortex-M7
Additionally, in our proposal, we have introduced a new assist Processor Technical Reference. 2015.
module for the ADCS. The module containing various [3] “Movidius VPU Product Brief,” Movidius VPU Product Brief. Intel,
2016.
sensors, such as temperature, internal and external radiation,
compass and GPS will record and log all the data collected for [4] L. I. Huanliang, “The Research of Intelligent Image Recognition
Technology Based on Neural Network,” pp. 1733–1736.
future studies and research. The module will also act as a
[5] Firdaus, Y. Arkeman, A. Buono, and I. Hermadi, “Earth and
backup module, giving the minimum data required for an Environmental Science,” in Satellite image processing for precision
ADCS to stabilize the satellite in case of ADCS failure. As agriculture and agroindustry using convolutional neural network and
for the EPS, we are embedding it on the OBC to have a genetic algorithm, 2017.
complete all-in-one system design for maximum reliability [6] N.H. Abroyan, and R.G. Hakobyan, Eds., A Review of the Usage of
and complete synchronization. Lastly, the OBC will have Machine Learning in Real-Time Systems, April 07, 2016. Armenia:
several standard and widely used I/O ports for connecting the NPUA, 2016.
payload, external peripherals and devices as needed by the [7] W. Stanton, P. Schulz, J. Wise, and B. King, “Intelligent Power
Management System for a Nanosatellite,” in Intelligent Power
user. Management System for a Nanosatellite.
For the software, all the subsystems of the OBC is [8] M. R. Maheshwarappa and C. P. Bridges, “Software Defined Radios
operated and handled by a custom-built RTOS, with machine for Small Satellites,” in 2014 NASA/ESA Conference on Adaptive
Hardware and Systems (AHS), 2014, pp. 172–179.
learning applications built in. It would be using a custom
[9] “NanoDock SDR,” NanoDock SDR. 2018.
Linux kernel, developed for the VPU and machine learning,
for perfect efficiency and synchronization with the hardware. [10] C. Patil, T. Chavan, N. Jhurani, D. Jethani, and M. Chaudhari,
“Satellite Image Acquisition Using SDR,” International Journal of
Innovative Research in Computer and Communication Engineering,
VII. CONCLUSION vol. 4, no. 3, pp. 3848–3854, Mar. 2016.
In this paper, we have presented our approach for a high [11] L. M. Davis, D. Haley, A. Pollok, and Y. Chen, “Satellite links and
performance on-board computing architecture with onboard software defined radio for remote communications and sensor data
machine-learning capabilities. The architecture is based on a gathering,” ResearchGate, Jan-2011. [Online]. Available:
https://www.researchgate.net/publication/267941331. [Accessed: 01-
distributed systems network, which incorporates several Jun-2015].
COTS-based processers and several specialized [12] “NOR | NAND Flash Guide,” NOR | NAND Flash Guide. Micron.
microprocessors for SDR and AI. It also contains an ADCS [13] “Movidius Myriad 2 Vision Processor,” Movidius Myriad 2 Vision
Assist module, containing several sensors and I/O ports for Processor. Intel, 2014.
interfacing and extra control in case of ADCS failure. This [14] “29th Annual AIAA/USU Conference on Small Satellites,”
distributed system approach with built-in machine learning in Enabling Dependable Data Storage for Miniaturized Satellites.
capabilities opens doors to new possibilities and applications [15] “Clyde Space Nanosatellite OBC,” Clyde Space Nanosatellite OBC.
in space based domains using AI and machine learning. By Clyde Space Ltd., 2016.
incorporating several sub-system of a satellite system into one [16] “PWSAT2 Critical Design Review-On Board Computer,” Students’
board, makes the architecture highly reliable and efficient. It Space Association, issue brief, 2016.
also acts as a backup system in case of emergency for the other [17] “Venus838FLPx GPS Receiver For CubeSat Application Data
system modules. The new hardware architecture and the Sheet,” Venus838FLPx GPS Receiver For CubeSat Application Data
Sheet. SkyTraq Technology, Inc., 2017.
machine-learning capabilities requires new concepts and
[18] “Digital CubeSat Dosimeter piDOSE-DCD Product Datasheet,”
implementations for embedded real-time operating systems
Product Datasheet. Rev.D, SkyFox Labs, 2017
and applications and is a stepping-stone toward developing
[19] “Zynq UltraScale RFSoC Data Sheet: Overview,” Zynq UltraScale
semi-autonomous satellite system. RFSoC Data Sheet: Overview. Xilinx, 2018.
[20] “High Performance Universal Flash Storage (UFS) Solutions,” High
ACKNOWLEDGMENT Performance Universal Flash Storage (UFS) Solutions, Brochure.
The authors would like to thank the professors and faculty Samsung, 2018
members of the Department of Electrical and Computer [21] S. Boyd-Wickizer, H. Chen, R. Chen, Y.Mao, M. F. Kaashoek, R.
Engineering of North South University for giving us the Morris, A. Pesterev, L. Stein, M. Wu, Y. Dai, Y. Zhang, and Z. Zhang,
“Corey: An operating system for many cores,” in Proc. of the 8th OSDI,
platform to work and research into the field. Lastly, we vol, 8, Dec. 2008, pp. 43-57
acknowledge and appreciate the support of Professor Dr. [22] M. Abadi, P. Barham, J. Chen, Z. Chen, A. Davis, J. Dean, M. Devin,
Atique Islam, honorable Vice Chancellor of North South S. Ghemawat, G. Irving, M. Isard, M. Kudlur, J. Levenberg, R. Monga,
University for helping and supporting us to complete this S. Moore, D. G. Murray, B. Steiner, P. Tucker, V. Vasudevan, P.
research paper. Warden, M. Wicke, Y. Yu, and X. Zheng, “12th USENIX Symposium
on Operating Systems Design and Implementation,” in TensorFlow: A
System for Large-Scale Machine Learning, 2016.
[23] “UM10204,” I2C-bus specification and user manual. Rev.6. 4 April
REFERENCES 2015.
[24] “GS-CSP-1.1”, CubeSat Space Protocol (CSP), Issue. 1, GOMspace,
[1] “ARM Cortex-M4 Processor Technical Reference,” ARM Cortex-M4 June 28, 2011
Processor Technical Reference. 2015.

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