9 Instruction Set

The SAB 80C517 instruction set includes 111 instructions, 49 of which are single-byte, 45 two-byte and 17 three-byte instructions. The instruction opcode format consists of a
function mnemonic followed by a ”destination, source” operand field. This field specifies the data type and addressing method(s) to be used.
Like all other members of the 8051-family, the SAB 80C517 can be programmed with the same instruction set common to the basic member, the SAB 8051. Thus, the SAB
80C517 is 100% software compatible to the SAB 8051 and may be programmed with 8051 assembler or high-level languages.
9.1 Addressing Modes
The SAB 80C517 uses five addressing modes:
– register
– direct
– immediate
– register indirect
– base register plus index-register indirect
Table 9-1 summarizes the memory spaces which may be accessed by each of the addressing modes.
Register Addressing
Register addressing accesses the eight working registers (R0 - R7) of the selected register bank. The least significant bit of the instruction opcode indicates which register is to be
used. ACC, B, DPTR and CY, the Boolean processor accumulator, can also be addressed as registers.
Direct Addressing
Direct addressing is the only method of accessing the special function registers. The lower 128 bytes of internal RAM are also directly addressable.
Immediate Addressing
Immediate addressing allows constants to be part of the instruction in program memory.
Table 9-1
Addressing Modes and Associated Memory Spaces
Register addressing R0 through R7 of selected register bank, ACC, B, CY (Bit), DPTR
Direct addressing Lower 128 bytes of internal RAM, special function registers
Immediate addressing Program memory
Register indirect addressing Internal RAM (@R1, @R0, SP), external data memory (@R1, @R0, @DPTR)
Base register plus index register addressing Program memory (@DPTR + A, @PC + A)

Register Indirect Addressing

Register indirect addressing uses the contents of either R0 or R1 (in the selected register bank) as a pointer to locations in a 256-byte block: the 256 bytes of internal RAM or the
lower 256 bytes of external data memory. Note that the special function registers are not accessible by this method. The upper half of the internal RAM can be accessed by indirect
addressing only. Access to the full 64 Kbytes of external data memory address space is accomplished by using the 16-bit data pointer. Execution of PUSH and POP instructions
also uses register indirect addressing. The stack may reside anywhere in the internal RAM.
Base Register plus Index Register Addressing
Base register plus index register addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register
(DPTR or PC) and index register, ACC. This mode facilitates look-up table accesses.
Boolean Processor
The Boolean processor is a bit processor integrated into the SAB 80C517. It has its own instruction set, accumulator (the carry flag), bit-addressable RAM and l/O.
The Bit Manipulation Instructions Allow:
– set bit
– clear bit
– complement bit
– jump if bit is set
– jump if bit is not set
– jump if bit is set and clear bit
– move bit from / to carry
Addressable bits, or their complements, may be logically AND-ed or OR-ed with the contents of the carry flag. The result is returned to the carry register.
9.2 Introduction to the Instruction Set
The instruction set is divided into four functional groups:
– data transfer
– arithmetic
– logic
– control transfer
9.2.1 Data Transfer
Data operations are divided into three classes:
– general-purpose
– accumulator-specific
– address-object
None of these operations affects the PSW flag settings except a POP or MOV directly to the PSW.
General-Purpose Transfers
– MOV performs a bit or byte transfer from the source operand to the destination operand.
– PUSH increments the SP register and then transfers a byte from the source operand to the stack location currently addressed by SP.
– POP transfers a byte operand from the stack location addressed by the SP to the destination operand and then decrements SP.
Accumulator-Specific Transfers
– XCH exchanges the byte source operand with register A (accumulator).
– XCHD exchanges the low-order nibble of the source operand byte with the low-order nibble
of A.
– MOVX performs a byte move between the external data memory and the accumulator. The
external address can be specified by the DPTR register (16 bit) or the R1 or R0 register (8 bit).
– MOVC moves a byte from program memory to the accumulator. The operand in A is used as
an index into a 256-byte table pointed to by the base register (DPTR or PC). The byte operand
accessed is transferred to the accumulator.
Address-Object Transfer
– MOV DPTR, #data loads 16 bits of immediate data into a pair of destination registers, DPH
and DPL.
9.2.2 Arithmetic
The SAB 80C517 has four basic mathematical operations. Only 8-bit operations using unsigned
arithmetic are supported directly. The overflow flag, however, permits the addition and subtraction
operation to serve for both unsigned and signed binary integers. Arithmetic can also be performed
directly on packed BCD representations.
Addition
– INC (increment) adds one to the source operand and puts the result in the operand.
– ADD adds A to the source operand and returns the result to A.
– ADDC (add with carry) adds A and the source operand, then adds one (1) if CY is set, and
puts the result in A.
– DA (decimal-add-adjust for BCD addition) corrects the sum which results from the binary
addition of two-digit decimal operands. The packed decimal sum formed by DA is returned to
A. CY is set if the BCD result is greater than 99; otherwise, it is cleared.
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Instruction Set
Subtraction
– SUBB (subtract with borrow) subtracts the second source operand from the the first operand
(the accumulator), subtracts one (1) if CY is set and returns the result to A.
– DEC (decrement) subtracts one (1) from the source operand and returns the result to the
operand.
Multiplication
– MUL performs an unsigned multiplication of the A register, returning a double byte result. A
receives the low-order byte, B receives the high-order byte. OV is cleared if the top half of the
result is zero and is set if it is not zero. CY is cleared. AC is unaffected.
Division
– DIV performs an unsigned division of the A register by the B register; it returns the integer
quotient to the A register and returns the fractional remainder to the B register. Division by
zero leaves indeterminate data in registers A and B and sets OV; otherwise, OV is cleared.
CY is cleared. AC remains unaffected.
Flags
Unless otherwise stated in the previous descriptions, the flags of PSW are affected as follows:
– CY is set if the operation causes a carry to or a borrow from the resulting high-order bit;
otherwise CY is cleared.
– AC is set if the operation results in a carry from the low-order four bits of the result (during
addition), or a borrow from the high-order bits to the low-order bits (during subtraction);
otherwise AC is cleared.
– OV is set if the operation results in a carry to the high-order bit of the result but not a carry
from the bit, or vice versa; otherwise OV is cleared. OV is used in two’s-complement
arithmetic, because it is set when the signal result cannot be represented in 8 bits.
– P is set if the modulo-2 sum of the eight bits in the accumulator is 1 (odd parity); otherwise P
is cleared (even parity). When a value is written to the PSW register, the P bit remains
unchanged, as it always reflects the parity of A.
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Instruction Set
9.2.3 Logic
The SAB 80C517 performs basic logic operations on both bit and byte operands.
Single-Operand Operations
– CLR sets A or any directly addressable bit to zero (0).
– SETB sets any directly bit-addressable bit to one (1).
– CPL is used to complement the contents of the A register without affecting any flag, or any
directly addressable bit location.
– RL, RLC, RR, RRC, SWAP are the five operations that can be performed on A. RL, rotate left,
RR, rotate right, RLC, rotate left through carry, RRC, rotate right through carry, and SWAP,
rotate left four. For RLC and RRC the CY flag becomes equal to the last bit rotated out. SWAP
rotates A left four places to exchange bits 3 through 0 with bits 7 through 4.
Two-Operand Operations
– ANL performs bitwise logical AND of two operands (for both bit and byte operands) and
returns the result to the location of the first operand.
– ORL performs bitwise logical OR of two source operands (for both bit and byte operands) and
returns the result to the location of the first operand.
– XRL performs logical Exclusive OR of two source operands (byte operands) and returns the
result to the location of the first operand.
9.2.4 Control Transfer
There are three classes of control transfer operations: unconditional calls, returns, jumps,
conditional jumps, and interrupts. All control transfer operations, some upon a specific condition,
cause the program execution to continue a non-sequential location in program memory.
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Instruction Set
Unconditional Calls, Returns and Jumps
Unconditional calls, returns and jumps transfer control from the current value of the program
counter to the target address. Both direct and indirect transfers are supported.
– ACALL and LCALL push the address of the next instruction onto the stack and then transfer
control to the target address. ACALL is a 2-byte instruction used when the target address is
in the current 2K page. LCALL is a 3-byte instruction that addresses the full 64K program
space. In ACALL, immediate data (i.e. an 11-bit address field) is concatenated to the five most
significant bits of the PC (which is pointing to the next instruction). If ACALL is in the last 2
bytes of a 2K page then the call will be made to the next page since the PC will have been
incremented to the next instruction prior to execution.
– RET transfers control to the return address saved on the stack by a previous call operation
and decrements the SP register by two (2) to adjust the SP for the popped address.
– AJMP, LJMP and SJMP transfer control to the target operand. The operation of AJMP and
LJMP are analogous to ACALL and LCALL. The SJMP (short jump) instruction provides for
transfers within a 256-byte range centered about the starting address of the next instruction
(– 128 to + 127).
– JMP @A + DPTR performs a jump relative to the DPTR register. The operand in A is used as
the offset (0 - 255) to the address in the DPTR register. Thus, the effective destination for a
jump can be anywhere in the program memory space.
Conditional Jumps
Conditional jumps perform a jump contingent upon a specific condition. The destination will be
within a 256-byte range centered about the starting address of the next instruction (– 128 to + 127).
– JZ performs a jump if the accumulator is zero.
– JNZ performs a jump if the accumulator is not zero.
– JC performs a jump if the carry flag is set.
– JNC performs a jump if the carry flag is not set.
– JB performs a jump if the directly addressed bit is set.
– JNB performs a jump if the directly addressed bit is not set.
– JBC performs a jump if the directly addressed bit is set and then clears the directly addressed
bit.
– CJNE compares the first operand to the second operand and performs a jump if they are not
equal. CY is set if the first operand is less than the second operand; otherwise it is cleared.
Comparisons can be made between A and directly addressable bytes in internal data memory
or an immediate value and either A, a register in the selected register bank, or a register
indirectly addressable byte of the internal RAM.
– DJNZ decrements the source operand and returns the result to the operand. A jump is
performed if the result is not zero. The source operand of the DJNZ instruction may be any
directly addressable byte in the internal data memory. Either direct or register addressing may
be used to address the source operand.
Interrupt Returns
– RETI transfers control as RET does, but additionally enables interrupts of the current priority
level.
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Instruction Set
9.3 Instruction Definitions
All 111 instructions of the SAB 80C517 can essentially be condensed to 54 basic operations, in the
following alphabetically ordered according to the operation mnemonic section.
A brief example of how the instruction might be used is given as well as its effect on the PSW flags.
The number of bytes and machine cycles required, the binary machine language encoding, and a
symbolic description or restatement of the function is also provided.
Note:
Only the carry, auxiliary carry, and overflow flags are discussed. The parity bit is computed after
every instruction cycle that alters the accumulator.
Similarily, instructions which alter directly addressed registers could affect the other status flags if
the instruction is applied to the PSW. Status flags can also be modified by bit manipulation.
Instruction Flag Instruction Flag
CY OV AC CY OV AC
ADD X X X SETB C 1
ADDC X X X CLR C 0
SUBB X X X CPL C X
MUL 0 X ANL C,bit X
DIV 0 X ANL C,/bit X
DA X ORL C,bit X
RRC X ORL C,/bit X
RLC X MOV C,bit X
CJNE X
Semiconductor Group 177
Instruction Set
Notes on Data Addressing Modes
Rn - Working register R0-R7
direct - 128 internal RAM locations, any l/O port, control or status register
@Ri - Indirect internal or external RAM location addressed by register R0 or R1
#data - 8-bit constant included in instruction
#data 16 - 16-bit constant included as bytes 2 and 3 of instruction
bit - 128 software flags, any bit-addressable l/O pin, control or status bit
A - Accumulator
Notes on Program Addressing Modes
addr16 - Destination address for LCALL and LJMP may be anywhere within the 64-Kbyte
program memory address space.
addr11 - Destination address for ACALL and AJMP will be within the same 2-Kbyte page of
program memory as the first byte of the following instruction.
rel - SJMP and all conditional jumps include an 8-bit offset byte. Range is + 127/– 128
bytes relative to the first byte of the following instruction.
All mnemonics copyrighted:  Intel Corporation 1980
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Instruction Set
ACALL addr11
Function: Absolute call
Description: ACALL unconditionally calls a subroutine located at the indicated address. The
instruction increments the PC twice to obtain the address of the following
instruction, then pushes the 16-bit result onto the stack (low-order byte first) and
increments the stack pointer twice. The destination address is obtained by
successively concatenating the five high-order bits of the incremented PC, op code
bits 7-5, and the second byte of the instruction. The subroutine called must
therefore start within the same 2K block of program memory as the first byte of the
instruction following ACALL. No flags are affected.
Example: Initially SP equals 07 H . The label ”SUBRTN” is at program memory location 0345 H .
After executing the instruction
ACALL SUBRTN
at location 0123 H , SP will contain 09 H , internal RAM location 08 H and 09 H will
contain 25 H and 01 H , respectively, and the PC will contain 0345 H .
Operation: ACALL
(PC) ← (PC) + 2
(SP) ← (SP) + 1
((SP)) ← (PC7-0)
(SP) ← (SP) + 1
((SP)) ← (PC15-8)
(PC10-0) ← page address
Bytes: 2
Cycles: 2
Encoding: a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
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Instruction Set
ADD A, <src-byte>
Function: Add
Description: ADD adds the byte variable indicated to the accumulator, leaving the result in the
accumulator. The carry and auxiliary carry flags are set, respectively, if there is a
carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers,
the carry flag indicates an overflow occurred.
OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but
not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates
a negative number produced as the sum of two positive operands, or a positive sum
from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-
indirect, or immediate.
Example: The accumulator holds 0C3 H (11000011 B ) and register 0 holds 0AA H
(10101010 B ).
The instruction
ADD A,R0
will leave 6D H (01101101 B ) in the accumulator with the AC flag cleared and both
the carry flag and OV set to 1.
ADD A,Rn
Operation: ADD
(A) ← (A) + (Rn)
Bytes: 1
Cycles: 1
ADD A,direct
Operation: ADD
(A) ← (A) + (direct)
Bytes: 2
Cycles: 1
Encoding: 0 0 1 0 1 r r r
Encoding: 0 0 0 1 0 1 0 1 direct address
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Instruction Set
ADD A, @Ri
Operation: ADD
(A) ← (A) + ((Ri))
Bytes: 1
Cycles: 1
ADD A, #data
Operation: ADD
(A) ← (A) + #data
Bytes: 2
Cycles: 1
Encoding: 0 0 1 0 0 1 1 i
Encoding: 0 0 1 0 0 1 0 0 immediate data
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Instruction Set
ADDC A, < src-byte>
Function: Add with carry
Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the
accumulator contents, leaving the result in the accumulator. The carry and auxiliary
carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared
otherwise. When adding unsigned integers, the carry flag indicates an overflow
occurred.
OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but
not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates
a negative number produced as the sum of two positive operands or a positive sum
from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-
indirect, or immediate.
Example: The accumulator holds 0C3 H (11000011 B ) and register 0 holds 0AA H (10101010 B )
with the carry flag set. The instruction
ADDC A,R0
will leave 6E H (01101110 B ) in the accumulator with AC cleared and both the carry
flag and OV set to 1.
ADDC A,Rn
Operation: ADDC
(A) ← (A) + (C) + (Rn)
Bytes: 1
Cycles: 1
ADDC A,direct
Operation: ADDC
(A) ← (A) + (C) + (direct)
Bytes: 2
Cycles: 1
Encoding: 0 0 1 1 1 r r r
Encoding: 0 0 1 1 0 1 0 1 direct address
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Instruction Set
ADDC A, @Ri
Operation: ADDC
(A) ← (A) + (C) + ((Ri))
Bytes: 1
Cycles: 1
ADDC A, #data
Operation: ADDC
(A) ← (A) + (C) + #data
Bytes: 2
Cycles: 1
Encoding: 0 0 1 1 0 1 1 i
Encoding: 0 0 1 1 0 1 0 0 immediate data
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Instruction Set
AJMP addr11
Function: Absolute jump
Description: AJMP transfers program execution to the indicated address, which is formed at run-
time by concatenating the high-order five bits of the PC ( after incrementing the PC
twice), op code bits 7-5, and the second byte of the instruction. The destination must
therefore be within the same 2K block of program memory as the first byte of the
instruction following AJMP.
Example: The label ”JMPADR” is at program memory location 0123 H . The instruction
AJMP JMPADR
is at location 0345 H and will load the PC with 0123 H .
Operation: AJM P
(PC) ← (PC) + 2
(PC10-0) ← page address
Bytes: 2
Cycles: 2
Encoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
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Instruction Set
ANL <dest-byte>, <src-byte>
Function: Logical AND for byte variables
Description: ANL performs the bitwise logical AND operation between the variables indicated
and stores the results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination
is a accumulator, the source can use register, direct, register-indirect, or immediate
addressing; when the destination is a direct address, the source can be the
accumulator or immediate data.
Note:
When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: If the accumulator holds 0C3 H (11000011 B ) and register 0 holds 0AA H
(10101010 B ) then the instruction
ANL A,R0
will leave 81 H (10000001 B ) in the accumulator.
When the destination is a directly addressed byte, this instruction will clear
combinations of bits in any RAM location or hardware register. The mask byte
determining the pattern of bits to be cleared would either be a constant contained
in the instruction or a value computed in the accumulator at run-time.
The instruction
ANL P1, #01110011 B
will clear bits 7, 3, and 2 of output port 1.
ANL A,Rn
Operation: ANL
(A) ← (A) ∧ (Rn)
Bytes: 1
Cycles: 1
ANL A,direct
Operation: ANL
(A) ← (A) ∧ (direct)
Bytes: 2
Cycles: 1
Encoding: 0 1 0 1 1 r r r
Encoding: 0 1 0 1 0 1 0 1 direct address
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Instruction Set
ANL A, @Ri
Operation: ANL
(A) ← (A) ∧ ((Ri))
Bytes: 1
Cycles: 1
ANL A, #data
Operation: ANL
(A) ← (A) ∧ #data
Bytes: 2
Cycles: 1
ANL direct,A
Operation: ANL
(direct) ← (direct) ∧ (A)
Bytes: 2
Cycles: 1
Encoding: 0 1 0 1 0 1 1 i
Encoding: 0 1 0 1 0 1 0 0 immediate data
Encoding: 0 1 0 1 0 1 0 1 direct address
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Instruction Set
ANL direct, #data
Operation: ANL
(direct) ← (direct) ∧ #data
Bytes: 3
Cycles: 2
Encoding: 0 1 0 1 0 0 1 1 direct address immediate data
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Instruction Set
ANL C, <src-bit>
Function: Logical AND for bit variables
Description: If the Boolean value of the source bit is a logic 0 then clear the carry flag; otherwise
leave the carry flag in its current state. A slash (”/” preceding the operand in the
assembly language indicates that the logical complement of the addressed bit is
used as the source value, but the source bit itself is not affected . No other flags are
affected.
Only direct bit addressing is allowed for the source operand.
Example: Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, and OV = 0:
MOV C,P1.0 ; Load carry with input pin state
ANL C,ACC.7 ; AND carry with accumulator bit 7
ANL C,/OV ; AND with inverse of overflow flag
ANL C,bit
Operation: ANL
(C) ← (C) ∧ (bit)
Bytes: 2
Cycles: 2
ANL C,/bit
Operation: ANL
(C) ← (C) ∧ / (bit)
Bytes: 2
Cycles: 2
Encoding: 1 0 0 0 0 0 1 0 bit address
Encoding: 1 0 1 1 0 0 0 0 bit address
Semiconductor Group 188
Instruction Set
CJNE <dest-byte >, < src-byte >, rel
Function: Compare and jump if not equal
Description: CJNE compares the magnitudes of the tirst two operands, and branches if their
values are not equal. The branch destination is computed by adding the signed
relative displacement in the last instruction byte to the PC, after incrementing the
PC to the start of the next instruction. The carry flag is set if the unsigned integer
value of <dest-byte> is less than the unsigned integer value of <src-byte>;
otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations: the accumulator
may be compared with any directly addressed byte or immediate data, and any
indirect RAM location or working register can be compared with an immediate
constant.
Example: The accumulator contains 34 H . Register 7 contains 56 H . The first instruction in the
sequence
CJNE R7, # 60H, NOT_EQ
; . . . . . . . . ; R7 = 60 H
NOT_EQ JC REQ_LOW ; If R7 < 60 H
; . . . . . . . . ; R7 > 60 H
sets the carry flag and branches to the instruction at label NOT_EQ. By testing the
carry flag, this instruction determines whether R7 is greater or less than 60 H .
If the data being presented to port 1 is also 34 H , then the instruction
WAIT: CJNE A,P1,WAIT
clears the carry flag and continues with the next instruction in sequence, since the
accumulator does equal the data read from P1. (If some other value was input on
P1, the program will loop at this point until the P1 data changes to 34 H ).
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Instruction Set
CJNE A,direct,rel
Operation: (PC) ← (PC) + 3
if (A) < > (direct)
then (PC) ← (PC) + relative offset
if (A) < (direct)
then (C) ←1
else (C) ← 0
Bytes: 3
Cycles: 2
CJNE A, #data,rel
Operation: (PC) ← (PC) + 3
if (A) < > data
then (PC) ← (PC) + relative offset
if (A) ← data
then (C) ←1
else (C) ← 0
Bytes: 3
Cycles: 2
CJNE RN, #data, rel
Operation: (PC) ← (PC) + 3
if (Rn) < > data
then (PC) ← (PC) + relative offset
if (Rn) < data
then (C) ← 1
else (C) ← 0
Bytes: 3
Cycles: 2
Encoding: 1 0 1 1 0 1 0 1 direct address rel. address
Encoding: 1 0 1 1 0 1 0 0 immediate data rel. address
Encoding: 1 0 1 1 1 r r r immediate data rel. address
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Instruction Set
CJNE @Ri, #data,rel
Operation: (PC) ← (PC) + 3
if ((Ri)) < > data
then (PC) ← (PC) + relative offset
if ((Ri)) < data
then (C) ← 1
else (C) ← 0
Bytes: 3
Cycles: 2
Encoding: 1 0 1 1 0 1 1 i immediate data rel. address
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Instruction Set
CLR A
Function: Clear accumulator
Description: The accumulator is cleared (all bits set to zero). No flags are affected.
Example: The accumulator contains 5C H (01011100 B ). The instruction
CLR A
will leave the accumulator set to 00 H (00000000 B ).
Operation: CLR
(A) ← 0
Bytes: 1
Cycles: 1
Encoding: 1 1 1 0 0 1 0 0
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Instruction Set
CLR bit
Function: Clear bit
Description: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can
operate on the carry flag or any directly addressable bit.
Example: Port 1 has previously been written with 5D H (01011101 B ). The instruction
CLR P1.2
will leave the port set to 59 H (01011001 B ).
CLR C
Operation: CLR
(C) ← 0
Bytes: 1
Cycles: 1
CLR bit
Operation: CLR
(bit) ← 0
Bytes: 2
Cycles: 1
Encoding: 1 1 0 0 0 0 1 1
Encoding: 1 1 0 0 0 0 1 0 bit address
Semiconductor Group 193
Instruction Set
CPL A
Function: Complement accumulator
Description: Each bit of the accumulator is logically complemented (one’s complement). Bits
which previously contained a one are changed to zero and vice versa. No flags are
affected.
Example: The accumulator contains 5C H (01011100 B ). The instruction
CPL A
will leave the accumulator set to 0A3 H (10100011 B ).
Operation: CPL
(A) ← / (A)
Bytes: 1
Cycles: 1
Encoding: 1 1 1 1 0 1 0 0
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Instruction Set
CPL bit
Function: Complement bit
Description: The bit variable specified is complemented. A bit which had been a one is changed
to zero and vice versa. No other flags are affected. CPL can operate on the carry or
any directly addressable bit.
Note:
When this instruction is used to modify an output pin, the value used as the original
data will be read from the output data latch, not the input pin.
Example: Port 1 has previously been written with 5D H (01011101 B ). The instruction
sequence
CPL P1.1
CPL P1.2
will leave the port set to 5B H (01011011 B ).
CPL C
Operation: CPL
(bit) ← / (C)
Bytes: 1
Cycles: 1
CPL bit
Operation: CPL
(C) ← / (bit)
Bytes: 2
Cycles: 1
Encoding: 1 0 1 1 0 0 1 1
Encoding: 1 0 1 1 0 0 1 0 bit address
Semiconductor Group 195
Instruction Set
DA A
Function: Decimal adjust accumulator for addition
Description: DA A adjusts the eight-bit value in the accumulator resulting from the earlier
addition of two variables (each in packed BCD format), producing two four-bit digits.
Any ADD or ADDC instruction may have been used to perform the addition.
If accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag
is one, six is added to the accumulator producing the proper BCD digit in the low-
order nibble. This internal addition would set the carry flag if a carry-out of the low-
order four-bit field propagated through all high-order bits, but it would not clear the
carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-
1111xxxx), these high-order bits are incremented by six, producing the proper BCD
digit in the high-order nibble. Again, this would set the carry flag if there was a carry-
out of the high-order bits, but wouldn’t clear the carry. The carry flag thus indicates
if the sum of the original two BCD variables is greater than 100, allowing multiple
precision decimal addition. OV is not affected.
All of this occurs during the one instruction cycle. Essentially; this instruction
performs the decimal conversion by adding 00 H , 06 H , 60 H , or 66 H to the
accumulator, depending on initial accumulator and PSW conditions.
Note:
DA A cannot simply convert a hexadecimal number in the accumulator to BCD
notation, nor does DA A apply to decimal subtraction.
Example: The accumulator holds the value 56 H (01010110 B ) representing the packed BCD
digits of the decimal number 56. Register 3 contains the value 67 H (01100111 B )
representing the packed BCD digits of the decimal number 67. The carry flag is set.
The instruction sequence
ADDC A,R3
DA A
will first perform a standard two’s-complement binary addition, resulting in the value
0BE H (10111110 B ) in the accumulator. The carry and auxiliary carry flags will be
cleared.
The decimal adjust instruction will then alter the accumulator to the value 24 H
(00100100 B ), indicating the packed BCD digits of the decimal number 24, the low-
order two digits of the decimal sum of 56, 67, and the carry-in. The carry flag will be
set by the decimal adjust instruction, indicating that a decimal overflow occurred.
The true sum 56, 67, and 1 is 124.
Semiconductor Group 196
Instruction Set
BCD variables can be incremented or decremented by adding 01 H or 99 H . If the
accumulator initially holds 30 H (representing the digits of 30 decimal), then the
instruction sequence
ADD A, #99H
DA A
will leave the carry set and 29 H in the accumulator, since 30 + 99 = 129. The low-
order byte of the sum can be interpreted to mean 30 – 1 = 29.
Operation: DA
contents of accumulator are BCD
if [[(A3-0) > 9] ∨ [(AC) = 1]]
then (A3-0) ← (A3-0) + 6
and
if [[(A7-4) > 9] ∨ [(C) = 1]]
then (A7-4) ← (A7-4) + 6
Bytes: 1
Cycles: 1
Encoding: 1 1 0 1 0 1 0 0
Semiconductor Group 197
Instruction Set
DEC byte
Function: Decrement
Description: The variable indicated is decremented by 1. An original value of 00 H will underflow
to 0FF H . No flags are affected. Four operand addressing modes are allowed:
accumulator, register, direct, or register-indirect.
Note:
When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: Register 0 contains 7F H (01111111 B ). Internal RAM locations 7E H and 7F H
contain 00 H and 40 H , respectively. The instruction sequence
DEC @R0
DEC R0
DEC @R0
will leave register 0 set to 7E H and internal RAM locations 7E H and 7F H set to
0FF H and 3F H .
DEC A
Operation: DEC
(A) ← (A) – 1
Bytes: 1
Cycles: 1
DEC Rn
Operation: DEC
(Rn) ← (Rn) – 1
Bytes: 1
Cycles: 1
Encoding: 0 0 0 1 0 1 0 0
Encoding: 0 0 0 1 1 r r r
Semiconductor Group 198
Instruction Set
DEC direct
Operation: DEC
(direct) ← (direct) – 1
Bytes: 2
Cycles: 1
DEC @Ri
Operation: DEC
((Ri)) ← ((Ri)) – 1
Bytes: 1
Cycles: 1
Encoding: 0 0 0 1 0 1 0 1 direct address
Encoding: 0 0 0 1 0 1 1 i
Semiconductor Group 199
Instruction Set
DIV AB
Function: Divide
Description: DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned
eight-bit integer in register B. The accumulator receives the integer part of the
quotient; register B receives the integer remainder. The carry and OV flags will be
cleared.
Exception: If B had originally contained 00 H , the values returned in the accumulator
and B register will be undefined and the overflow flag will be set. The carry flag is
cleared in any case.
Example: The accumulator contains 251 (0FB H or 11111011 B ) and B contains 18 (12 H or
00010010 B ). The instruction
DIV AB
will leave 13 in the accumulator (0D H or 00001101 B ) and the value 17 (11 H or
00010001 B ) in B, since 251 = (13x18) + 17. Carry and OV will both be cleared.
Operation: DIV
(A15-8)
(B7-0)
Bytes: 1
Cycles: 4
Encoding: 1 0 0 0 0 1 0 0
← (A) / (B)
Semiconductor Group 200
Instruction Set
DJNZ <byte>, < rel-addr>
Function: Decrement and jump if not zero
Description: DJNZ decrements the location indicated by 1, and branches to the address
indicated by the second operand if the resulting value is not zero. An original value
of 00 H will underflow to 0FF H . No flags are affected. The branch destination would
be computed by adding the signed relative-displacement value in the last instruction
byte to the PC, after incrementing the PC to the first byte of the following instruction.
The location decremented may be a register or directly addressed byte.
Note:
When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: Internal RAM locations 40 H , 50 H , and 60 H contain the values, 01 H , 70 H , and 15 H ,
respectively. The instruction sequence
DJNZ 40H,LABEL_1
DJNZ 50H,LABEL_2
DJNZ 60H,LABEL_3
will cause a jump to the instruction at label LABEL_2 with the values 00 H , 6F H , and
15 H in the three RAM locations. The first jump was not taken because the result was
zero.
This instruction provides a simple way of executing a program loop a given number
of times, or for adding a moderate time delay (from 2 to 512 machine cycles) with a
single instruction. The instruction sequence
MOV R2, #8
TOGGLE: CPL P1.7
DJNZ R2,TOGGLE
will toggle P1.7 eight times, causing four output pulses to appear at bit 7 of output
port 1. Each pulse will last three machine cycles; two for DJNZ and one to alter the
pin.
Semiconductor Group 201
Instruction Set
DJNZ Rn,rel
Operation: DJNZ
(PC) ← (PC) + 2
(Rn) ← (Rn) – 1
if (Rn) > 0 or (Rn) < 0
then (PC) ← (PC) + rel
Bytes: 2
Cycles: 2
DJNZ direct,rel
Operation: DJNZ
(PC) ← (PC) + 2
(direct) ← (direct) – 1
if (direct) > 0 or (direct) < 0
then (PC) ← (PC) + rel
Bytes: 3
Cycles: 2
Encoding: 1 1 0 1 1 r r r rel. address
Encoding: 1 1 0 1 0 1 0 1 direct address rel. address
Semiconductor Group 202
Instruction Set
INC <byte>
Function: Increment
Description: INC increments the indicated variable by 1. An original value of 0FF H will overflow
to 00 H . No flags are affected. Three addressing modes are allowed: register, direct,
or register-indirect.
Note:
When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: Register 0 contains 7E H (01111110 B ). Internal RAM locations 7E H and 7F H
contain 0FF H and 40 H , respectively. The instruction sequence
INC @R0
INC R0
INC @R0
will leave register 0 set to 7F H and internal RAM locations 7E H and 7F H holding
(respectively) 00 H and 41 H .
INC A
Operation: INC
(A) ← (A) + 1
Bytes: 1
Cycles: 1
INC Rn
Operation: INC
(Rn) ← (Rn) + 1
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 1 0 0
Encoding: 0 0 0 0 1 r r r
Semiconductor Group 203
Instruction Set
INC direct
Operation: INC
(direct) ← (direct) + 1
Bytes: 2
Cycles: 1
INC @Ri
Operation: INC
((Ri)) ← ((Ri)) + 1
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 1 0 1 direct address
Encoding: 0 0 0 0 0 1 1 i
Semiconductor Group 204
Instruction Set
INC DPTR
Function: Increment data pointer
Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16 ) is performed;
an overflow of the low-order byte of the data pointer (DPL) from 0FF H to 00 H will
increment the high-order byte (DPH). No flags are affected.
This is the only 16-bit register which can be incremented.
Example: Registers DPH and DPL contain 12 H and 0FE H , respectively. The instruction
sequence
INC DPTR
INC DPTR
INC DPTR
will change DPH and DPL to 13 H and 01 H .
Operation: INC
(DPTR) ← (DPTR) + 1
Bytes: 1
Cycles: 2
Encoding: 1 0 1 0 0 0 1 1
Semiconductor Group 205
Instruction Set
JB bit,rel
Function: Jump if bit is set
Description: If the indicated bit is a one, jump to the address indicated; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed
relative-displacement in the third instruction byte to the PC, after incrementing the
PC to the first byte of the next instruction. The bit tested is not modified. No flags
are affected.
Example: The data present at input port 1 is 11001010 B . The accumulator holds 56
(01010110 B ). The instruction sequence
JB P1.2,LABEL1
JB ACC.2,LABEL2
will cause program execution to branch to the instruction at label LABEL2.
Operation: JB
(PC) ← (PC) + 3
if (bit) = 1
then (PC) ← (PC) + rel
Bytes: 3
Cycles: 2
Encoding: 0 0 1 0 0 0 0 0 bit address rel. address
Semiconductor Group 206
Instruction Set
JBC bit,rel
Function: Jump if bit is set and clear bit
Description: If the indicated bit is one, branch to the address indicated; otherwise proceed with
the next instruction. In either case, clear the designated bit. The branch destination
is computed by adding the signed relative displacement in the third instruction byte
to the PC, after incrementing the PC to the first byte of the next instruction. No flags
are affected.
Note:
When this instruction is used to test an output pin, the value used as the original
data will be read from the output data latch, not the input pin.
Example: The accumulator holds 56 H (01010110 B ). The instruction sequence
JBC ACC.3,LABEL1
JBC ACC.2,LABEL2
will cause program execution to continue at the instruction identified by the label
LABEL2, with the accumulator modified to 52 H (01010010 B ).
Operation: JBC
(PC) ← (PC) + 3
if (bit) = 1
then (bit) ← 0
(PC) ← (PC) + rel
Bytes: 3
Cycles: 2
Encoding: 0 0 0 1 0 0 0 0 bit address rel. address
Semiconductor Group 207
Instruction Set
JC rel
Function: Jump if carry is set
Description: If the carry flag is set, branch to the address indicated; otherwise proceed with the
next instruction. The branch destination is computed by adding the signed relative-
displacement in the second instruction byte to the PC, after incrementing the PC
twice. No flags are affected.
Example: The carry flag is cleared. The instruction sequence
JC LABEL1
CPL C
JC LABEL2
will set the carry and cause program execution to continue at the instruction
identified by the label LABEL2.
Operation: JC
(PC) ← (PC) + 2
if (C) = 1
then (PC) ← (PC) + rel
Bytes: 2
Cycles: 2
Encoding: 0 1 0 0 0 0 0 0 rel. address
Semiconductor Group 208
Instruction Set
JMP @A + DPTR
Function: Jump indirect
Description: Add the eight-bit unsigned contents of the accumulator with the sixteen-bit data
pointer, and load the resulting sum to the program counter. This will be the address
for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 2 16 ): a
carry-out from the low-order eight bits propagates through the higher-order bits.
Neither the accumulator nor the data pointer is altered. No flags are affected.
Example: An even number from 0 to 6 is in the accumulator. The following sequence of
instructions will branch to one of four AJMP instructions in a jump table starting at
JMP_TBL:
MOV DPTR, #JMP_TBL
JMP @A + DPTR
JMP_TBL: AJMP LABEL0
AJMP LABEL1
AJMP LABEL2
AJMP LABEL3
If the accumulator equals 04 H when starting this sequence, execution will jump to
label LABEL2. Remember that AJMP is a two-byte instruction, so the jump
instructions start at every other address.
Operation: JMP
(PC) ← (A) + (DPTR)
Bytes: 1
Cycles: 2
Encoding: 0 1 1 1 0 0 1 1
Semiconductor Group 209
Instruction Set
JNB bit,rel
Function: Jump if bit is not set
Description: If the indicated bit is a zero, branch to the indicated address; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed
relative-displacement in the third instruction byte to the PC, after incrementing the
PC to the first byte of the next instruction. The bit tested is not modified. No flags
are affected.
Example: The data present at input port 1 is 11001010 B . The accumulator holds 56 H
(01010110 B ). The instruction sequence
JNB P1.3,LABEL1
JNB ACC.3,LABEL2
will cause program execution to continue at the instruction at label LABEL2.
Operation: JNB
(PC) ← (PC) + 3
if (bit) = 0
then (PC) ← (PC) + rel.
Bytes: 3
Cycles: 2
Encoding: 0 0 1 1 0 0 0 0 bit address rel. address
Semiconductor Group 210
Instruction Set
JNC rel
Function: Jump if carry is not set
Description: If the carry flag is a zero, branch to the address indicated; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed
relative-displacement in the second instruction byte to the PC, after incrementing
the PC twice to point to the next instruction. The carry flag is not modified.
Example: The carry flag is set. The instruction sequence
JNC LABEL1
CPL C
JNC LABEL2
will clear the carry and cause program execution to continue at the instruction
identified by the label LABEL2.
Operation: JNC
(PC) ← (PC) + 2
if (C) = 0
then (PC) ← (PC) + rel
Bytes: 2
Cycles: 2
Encoding: 0 1 0 1 0 0 0 0 rel. address
Semiconductor Group 211
Instruction Set
JNZ rel
Function: Jump if accumulator is not zero
Description: If any bit of the accumulator is a one, branch to the indicated address; otherwise
proceed with the next instruction. The branch destination is computed by adding the
signed relative-displacement in the second instruction byte to the PC, after
incrementing the PC twice. The accumulator is not modified. No flags are affected.
Example: The accumulator originally holds 00 H . The instruction sequence
JNZ LABEL1
INC A
JNZ LABEL2
will set the accumulator to 01 H and continue at label LABEL2.
Operation: JNZ
(PC) ← (PC) + 2
if (A) ≠ 0
then (PC) ← (PC) + rel.
Bytes: 2
Cycles: 2
Encoding: 0 1 1 1 0 0 0 0 rel. address
Semiconductor Group 212
Instruction Set
JZ rel
Function: Jump if accumulator is zero
Description: If all bits of the accumulator are zero, branch to the address indicated; otherwise
proceed with the next instruction. The branch destination is computed by adding the
signed relative-displacement in the second instruction byte to the PC, after
incrementing the PC twice. The accumulator is not modified. No flags are affected.
Example: The accumulator originally contains 01 H . The instruction sequence
JZ LABEL1
DEC A
JZ LABEL2
will change the accumulator to 00 H and cause program execution to continue at the
instruction identified by the label LABEL2.
Operation: JZ
(PC) ← (PC) + 2
if (A) = 0
then (PC) ← (PC) + rel
Bytes: 2
Cycles: 2
Encoding: 0 1 1 0 0 0 0 0 rel. address
Semiconductor Group 213
Instruction Set
LCALL addr16
Function: Long call
Description: LCALL calls a subroutine located at the indicated address. The instruction adds
three to the program counter to generate the address of the next instruction and
then pushes the 16-bit result onto the stack (low byte first), incrementing the stack
pointer by two. The high-order and low-order bytes of the PC are then loaded,
respectively, with the second and third bytes of the LCALL instruction. Program
execution continues with the instruction at this address. The subroutine may
therefore begin anywhere in the full 64 Kbyte program memory address space. No
flags are affected.
Example: Initially the stack pointer equals 07 H . The label ”SUBRTN” is assigned to program
memory location 1234 H . After executing the instruction
LCALL SUBRTN
at location 0123 H , the stack pointer will contain 09 H , internal RAM locations 08 H
and 09 H will contain 26 H and 01 H , and the PC will contain 1234 H .
Operation: LCALL
(PC) ← (PC) + 3
(SP) ← (SP) + 1
((SP)) ← (PC7-0)
(SP) ← (SP) + 1
((SP)) ← (PC15-8)
(PC) ← addr15-0
Bytes: 3
Cycles: 2
Encoding: 0 0 0 1 0 0 1 0 addr15 . . addr8 addr7 . . addr0
Semiconductor Group 214
Instruction Set
LJMP addr16
Function: Long jump
Description: LJMP causes an unconditional branch to the indicated address, by loading the high-
order and low-order bytes of the PC (respectively) with the second and third
instruction bytes. The destination may therefore be anywhere in the full 64K
program memory address space. No flags are affected.
Example: The label ”JMPADR” is assigned to the instruction at program memory location
1234 H . The instruction
LJMP JMPADR
at location 0123 H will load the program counter with 1234 H .
Operation: LJMP
(PC) ← addr15-0
Bytes: 3
Cycles: 2
Encoding: 0 0 0 0 0 0 1 0 addr15 . . . addr8 addr7 . . . addr0
Semiconductor Group 215
Instruction Set
MOV <dest-byte>, <src-byte>
Function: Move byte variable
Description: The byte variable indicated by the second operand is copied into the location
specified by the first operand. The source byte is not affected. No other register or
flag is affected.
This is by far the most flexible operation. Fifteen combinations of source and
destination addressing modes are allowed.
Example: Internal RAM location 30 H holds 40 H . The value of RAM location 40 H is 10 H . The
data present at input port 1 is 11001010B (0CA H ).
MOV R0, #30H ; R0 < = 30H
MOV A, @R0 ; A < = 40H
MOV R1,A ; R1 < = 40H
MOV B, @R1 ; B < = 10 H
MOV @R1,P1 ; RAM (40H) < = 0CAH
MOV P2,P1 ; P2 < = 0CAH
leaves the value 30 H in register 0, 40 H in both the accumulator and register 1, 10 H
in register B, and 0CA H (11001010 B ) both in RAM location 40 H and output on
port 2.
MOV A,Rn
Operation: MOV
(A) ← (Rn)
Bytes: 1
Cycles: 1
MOV A,direct *)
Operation: MOV
(A) ← (direct)
Bytes: 2
Cycles: 1
*) MOV A,ACC is not a valid instruction. The content of the accumulator after the execution of this
instruction is undefined.
Encoding: 1 1 1 0 1 r r r
Encoding: 1 1 1 0 0 1 0 1 direct address
Semiconductor Group 216
Instruction Set
MOV A,@Ri
Operation: MOV
(A) ← ((Ri))
Bytes: 1
Cycles: 1
MOV A, #data
Operation: MOV
(A) ← #data
Bytes: 2
Cycles: 1
MOV Rn,A
Operation: MOV
(Rn) ← (A)
Bytes: 1
Cycles: 1
MOV Rn,direct
Operation: MOV
(Rn) ← (direct)
Bytes: 2
Cycles: 2
Encoding: 1 1 1 0 0 1 1 i
Encoding: 0 1 1 1 0 1 0 0 immediate data
Encoding: 1 1 1 1 1 r r r
Encoding: 1 0 1 0 1 r r r direct address
Semiconductor Group 217
Instruction Set
MOV Rn, #data
Operation: MOV
(Rn) ← #data
Bytes: 2
Cycles: 1
MOV direct,A
Operation: MOV
(direct) ← (A)
Bytes: 2
Cycles: 1
MOV direct,Rn
Operation: MOV
(direct) ← (Rn)
Bytes: 2
Cycles: 2
MOV direct,direct
Operation: MOV
(direct) ← (direct)
Bytes: 3
Cycles: 2
Encoding: 0 1 1 1 1 r r r immediate data
Encoding: 1 1 1 1 0 1 0 1 direct address
Encoding: 1 0 0 0 1 r r r direct address
Encoding: 1 0 0 0 0 1 0 1 dir.addr. (src) dir.addr. (dest)
Semiconductor Group 218
Instruction Set
MOV direct, @ Ri
Operation: MOV
(direct) ← ((Ri))
Bytes: 2
Cycles: 2
MOV direct, #data
Operation: MOV
(direct) ← #data
Bytes: 3
Cycles: 2
MOV @ Ri,A
Operation: MOV
((Ri)) ← (A)
Bytes: 1
Cycles: 1
MOV @ Ri,direct
Ooeration: MOV
((Ri)) ← (direct)
Bytes: 2
Cycles: 2
Encoding: 1 0 0 0 0 1 1 i direct address
Encoding: 0 1 1 1 0 1 0 1 direct address immediate data
Encoding: 1 1 1 1 0 1 1 i
Encoding: 1 0 1 0 0 1 1 i direct address
Semiconductor Group 219
Instruction Set
MOV @ Ri,#data
Operation: MOV
((Ri)) ← #data
Bytes: 2
Cycles: 1
Encoding: 0 1 1 1 0 1 1 i immediate data
Semiconductor Group 220
Instruction Set
MOV <dest-bit>, <src-bit>
Function: Move bit data
Description: The Boolean variable indicated by the second operand is copied into the location
specified by the first operand. One of the operands must be the carry flag; the other
may be any directly addressable bit. No other register or flag is affected.
Example: The carry flag is originally set. The data present at input port 3 is 11000101 B . The
data previously written to output port 1 is 35 H (00110101 B ).
MOV P1.3,C
MOV C,P3.3
MOV P1.2,C
will leave the carry cleared and change port 1 to 39 H (00111001 B ).
MOV C,bit
Operation: MOV
(C) ← (bit)
Bytes: 2
Cycles: 1
MOV bit,C
Operation: MOV
(bit) ← (C)
Bytes: 2
Cycles: 2
Encoding: 1 0 1 0 0 0 1 0 bit address
Encoding: 1 0 0 1 0 0 1 0 bit address
Semiconductor Group 221
Instruction Set
MOV DPTR, #data16
Function: Load data pointer with a 16-bit constant
Description: The data pointer is loaded with the 16-bit constant indicated. The 16 bit constant is
loaded into the second and third bytes of the instruction. The second byte (DPH) is
the high-order byte, while the third byte (DPL) holds the low-order byte. No flags are
affected.
This is the only instruction which moves 16 bits of data at once.
Example: The instruction
MOV DPTR, #1234H
will load the value 1234 H into the data pointer: DPH will hold 12 H and DPL will hold
34 H .
Operation: MOV
(DPTR) ← #data15-0
DPH DPL ← #data15-8 #data7-0
Bytes: 3
Cycles: 2
Encoding: 1 0 0 1 0 0 0 0 immed. data 15 . . . 8 immed. data 7 . . . 0
Semiconductor Group 222
Instruction Set
MOVC A, @A + <base-reg>
Function: Move code byte
Description: The MOVC instructions load the accumulator with a code byte, or constant from
program memory. The address of the byte fetched is the sum of the original
unsigned eight-bit accumulator contents and the contents of a sixteen-bit base
register, which may be either the data pointer or the PC. In the latter case, the PC
is incremented to the address of the following instruction before being added to the
accumulator; otherwise the base register is not altered. Sixteen-bit addition is
performed so a carry-out from the low-order eight bits may propagate through
higher-order bits. No flags are affected.
Example: A value between 0 and 3 is in the accumulator. The following instructions will
translate the value in the accumulator to one of four values defined by the DB
(define byte) directive.
REL_PC: INC A
MOVC A, @A + PC
RET
DB 66H
DB 77H
DB 88H
DB 99H
If the subroutine is called with the accumulator equal to 01 H , it will return with 77 H
in the accumulator. The INC A before the MOVC instruction is needed to ”get
around” the RET instruction above the table. If several bytes of code separated the
MOVC from the table, the corresponding number would be added to the
accumulator instead.
MOVC A, @A + DPTR
Operation: MOVC
(A) ← ((A) + (DPTR))
Bytes: 1
Cycles: 2
Encoding: 1 0 0 1 0 0 1 1
Semiconductor Group 223
Instruction Set
MOVC A, @A + PC
Operation: MOVC
(PC) ← (PC) + 1
(A) ← ((A) + (PC))
Bytes: 1
Cycles: 2
Encoding: 1 0 0 0 0 0 1 1
Semiconductor Group 224
Instruction Set
MOVX <dest-byte>, <src-byte>
Function: Move external
Description: The MOVX instructions transfer data between the accumulator and a byte of
external data memory, hence the ”X” appended to MOV. There are two types of
instructions, differing in whether they provide an eight bit or sixteen-bit indirect
address to the external data RAM.
In the first type, the contents of R0 or R1 in the current register bank provide an
eight-bit address multiplexed with data on P0. Eight bits are sufficient for external
l/O expansion decoding or a relatively small RAM array. For somewhat larger
arrays, any output port pins can be used to output higher-order address bits. These
pins would be controlled by an output instruction preceding the MOVX.
In the second type of MOVX instructions, the data pointer generates a sixteen-bit
address. P2 outputs the high-order eight address bits (the contents of DPH) while
P0 multiplexes the low-order eight bits (DPL) with data. The P2 special function
register retains its previous contents while the P2 output buffers are emining the
contents of DPH. This form is faster and more efficient when accessing very large
data arrays (up to 64 Kbyte), since no additional instructions are needed to set up
the output ports.
It is possible in some situations to mix the two MOVX types. A large RAM array with
its high-order address lines driven by P2 can be addressed via the data pointer, or
with code to output high-order address bits to P2 followed by a MOVX instruction
using R0 or R1.
Example: An external 256-byte RAM using multiplexed address/data lines (e.g. an SAB 8155
RAM/I/O/timer) is connected to the SAB 80(c)5XX port 0. Port 3 provides control
lines for the external RAM. Ports 1 and 2 are used for normal l/O. Registers 0 and
1 contain 12 H and 34 H . Location 34 H of the external RAM holds the value 56 H . The
instruction sequence
MOVX A, @R1
MOVX @R0,A
copies the value 56 H into both the accumulator and external RAM location 12 H .
Semiconductor Group 225
Instruction Set
MOVX A,@Ri
Operation: MOVX
(A) ← ((Ri))
Bytes: 1
Cycles: 2
MOVX A,@DPTR
Operation: MOVX
(A) ← ((DPTR))
Bytes: 1
Cycles: 2
MOVX @Ri,A
Operation: MOVX
((Ri)) ← (A)
Bytes: 1
Cycles: 2
MOVX @DPTR,A
Operation: MOVX
((DPTR)) (A)
Bytes: 1
Cycles: 2
Encoding: 1 1 1 0 0 0 1 i
Encoding: 1 1 1 0 0 0 0 0
Encoding: 1 1 1 1 0 0 1 i
Encoding: 1 1 1 1 0 0 0 0
Semiconductor Group 226
Instruction Set
MUL AB
Function: Multiply
Description: MUL AB multiplies the unsigned eight-bit integers in the accumulator and register
B. The low-order byte of the sixteen-bit product is left in the accumulator, and the
high-order byte in B. If the product is greater than 255 (0FF H ) the overflow flag is
set; otherwise it is cleared. The carry flag is always cleared.
Example: Originally the accumulator holds the value 80 (50 H ). Register B holds the value 160
(0A0 H ). The instruction
MUL AB
will give the product 12,800 (3200 H ), so B is changed to 32 H (00110010 B ) and the
accumulator is cleared. The overflow flag is set, carry is cleared.
Operation: MUL
(A7-0)
(B15-8)
Bytes: 1
Cycles: 4
Encoding: 1 0 1 0 0 1 0 0
← (A) x (B)
Semiconductor Group 227
Instruction Set
NOP
Function: No operation
Description: Execution continues at the following instruction. Other than the PC, no registers or
flags are affected.
Example: It is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly
5 cycles. A simple SETB/CLR sequence would generate a one-cycle pulse, so four
additional cycles must be inserted. This may be done (assuming no interrupts are
enabled) with the instruction sequence
CLR P2.7
NOP
NOP
NOP
NOP
SETB P2.7
Operation: NOP
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 0 0 0
Semiconductor Group 228
Instruction Set
ORL <dest-byte> <src-byte>
Function: Logical OR for byte variables
Description: ORL performs the bitwise logical OR operation between the indicated variables,
storing the results in the destination byte. No flags are affected .
The two operands allow six addressing mode combinations. When the destination
is the accumulator, the source can use register, direct, register-indirect, or
immediate addressing; when the destination is a direct address, the source can be
the accumulator or immediate data.
Note:
When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: If the accumulator holds 0C3 H (11000011 B ) and R0 holds 55 H (01010101 B ) then
the instruction
ORL A,R0
will leave the accumulator holding the value 0D7 H (11010111 B ).
When the destination is a directly addressed byte, the instruction can set
combinations of bits in any RAM location or hardware register. The pattern of bits
to be set is determined by a mask byte, which may be either a constant data value
in the instruction or a variable computed in the accumulator at run-time. The
instruction
ORL P1,#00110010 B
will set bits 5, 4, and 1 of output port 1.
ORL A,Rn
Operation: ORL
(A) ← (A) ∨ (Rn)
Bytes: 1
Cycles: 1
Encoding: 0 1 0 0 1 r r r
Semiconductor Group 229
Instruction Set
ORL A,direct
Operation: ORL
(A) ← (A) ∨ (direct)
Bytes: 2
Cycles: 1
ORL A,@Ri
Operation: ORL
(A) ← (A) ∨ ((Ri))
Bytes: 1
Cycles: 1
ORL A,#data
Operation: ORL
(A) ← (A) ∨ #data
Bytes: 2
Cycles: 1
ORL direct,A
Operation: ORL
(direct) ← (direct) ∨ (A)
Bytes: 2
Cycles: 1
Encoding: 0 1 0 0 0 1 0 1 direct address
Encoding: 0 1 0 0 0 1 1 i
Encoding: 0 1 0 0 0 1 0 0 immediate data
Encoding: 0 1 0 0 0 0 1 0 direct address
Semiconductor Group 230
Instruction Set
ORL direct, #data
Operation: ORL
(direct) ← (direct) ∨ #data
Bytes: 3
Cycles: 2
Encoding: 0 1 0 0 0 0 1 1 direct address immediate data
Semiconductor Group 231
Instruction Set
ORL C, <src-bit>
Function: Logical OR for bit variables
Description: Set the carry flag if the Boolean value is a logic 1; leave the carry in its current state
otherwise. A slash (”/”) preceding the operand in the assembly language indicates
that the logical complement of the addressed bit is used as the source value, but
the source bit itself is not affected. No other flags are affected.
Example: Set the carry flag if, and only if, P1.0 = 1, ACC.7 = 1, or OV = 0:
MOV C,P1.0 ; Load carry with input pin P1.0
ORL C,ACC.7 ; OR carry with the accumulator bit 7
ORL C,/OV ; OR carry with the inverse of OV
ORL C,bit
Operation: ORL
(C) ← (C) ∨ (bit)
Bytes: 2
Cycles: 2
ORL C,/bit
Operation: ORL
(C) ← (C) ∨ / (bit)
Bytes: 2
Cycles: 2
Encoding: 0 1 1 1 0 0 1 0 bit address
Encoding: 1 0 1 0 0 0 0 0 bit address
Semiconductor Group 232
Instruction Set
POP direct
Function: Pop from stack
Description: The contents of the internal RAM location addressed by the stack pointer is read,
and the stack pointer is decremented by one. The value read is the transfer to the
directly addressed byte indicated. No flags are affected.
Example: The stack pointer originally contains the value 32 H , and internal RAM locations 30 H
through 32 H contain the values 20 H , 23 H , and 01 H , respectively. The instruction
sequence
POP DPH
POP DPL
will leave the stack pointer equal to the value 30 H and the data pointer set to 0123 H .
At this point the instruction
POP SP
will leave the stack pointer set to 20 H . Note that in this special case the stack pointer
was decremented to 2F H before being loaded with the value popped (20 H ).
Operation: POP
(direct) ← ((SP))
(SP) ← (SP) – 1
Bytes: 2
Cycles: 2
Encoding: 1 1 0 1 0 0 0 0 direct address
Semiconductor Group 233
Instruction Set
PUSH direct
Function: Push onto stack
Description: The stack pointer is incremented by one. The contents of the indicated variable is
then copied into the internal RAM location addressed by the stack pointer.
Otherwise no flags are affected.
Example: On entering an interrupt routine the stack pointer contains 09 H . The data pointer
holds the value 0123 H . The instruction sequence
PUSH DPL
PUSH DPH
will leave the stack pointer set to 0B H and store 23 H and 01 H in internal RAM
locations 0A H and 0B H , respectively.
Operation: PUSH
(SP) ← (SP) + 1
((SP)) ← (direct)
Bytes: 2
Cycles: 2
Encoding: 1 1 0 0 0 0 0 0 direct address
Semiconductor Group 234
Instruction Set
RET
Function: Return from subroutine
Description: RET pops the high and low-order bytes of the PC successively from the stack,
decrementing the stack pointer by two. Program execution continues at the
resulting address, generally the instruction immediately following an ACALL or
LCALL. No flags are affected.
Example: The stack pointer originally contains the value 0B H . Internal RAM locations 0A H
and 0B H contain the values 23 H and 01 H , respectively. The instruction
RET
will leave the stack pointer equal to the value 09 H . Program execution will continue
at location 0123 H .
Operation: RET
(PC15-8) ← ((SP))
(SP) ← (SP) – 1
(PC7-0) ← ((SP))
(SP) ← (SP) – 1
Bytes: 1
Cycles: 2
Encoding: 0 0 1 0 0 0 1 0
Semiconductor Group 235
Instruction Set
RETI
Function: Return from interrupt
Description: RETI pops the high and low-order bytes of the PC successively from the stack, and
restores the interrupt logic to accept additional interrupts at the same priority level
as the one just processed. The stack pointer is left decremented by two. No other
registers are affected; the PSW is not automatically restored to its pre-interrupt
status. Program execution continues at the resulting address, which is generally the
instruction immediately after the point at which the interrupt request was detected.
If a lower or same-level interrupt is pending when the RETI instruction is executed,
that one instruction will be executed before the pending interrupt is processed.
Example: The stack pointer originally contains the value 0B H . An interrupt was detected
during the instruction ending at location 0122 H . Internal RAM locations 0A H and
0B H contain the values 23 H and 01 H , respectively. The instruction
RETI
will leave the stack pointer equal to 09 H and return program execution to location
0123 H .
Operation: RETI
(PC15-8) ← ((SP))
(SP) ← (SP) – 1
(PC7-0) ← ((SP))
(SP) ← (SP) – 1
Bytes: 1
Cycles: 2
Encoding: 0 0 1 1 0 0 1 0
Semiconductor Group 236
Instruction Set
RL A
Function: Rotate accumulator left
Description: The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into
the bit 0 position. No flags are affected.
Example: The accumulator holds the value 0C5 H (11000101 B ). The instruction
RL A
leaves the accumulator holding the value 8B H (10001011 B ) with the carry
unaffected.
Operation: RL
(An + 1) ← (An) n = 0-6
(A0) ← (A7)
Bytes: 1
Cycles: 1
Encoding: 0 0 1 0 0 0 1 1
Semiconductor Group 237
Instruction Set
RLC A
Function: Rotate accumulator left through carry flag
Description: The eight bits in the accumulator and the carry flag are together rotated one bit to
the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into
the bit 0 position. No other flags are affected.
Example: The accumulator holds the value 0C5 H (11000101 B ), and the carry is zero. The
instruction
RLC A
leaves the accumulator holding the value 8A H (10001010B) with the carry set.
Operation: RLC
(An + 1) ← (An) n = 0-6
(A0) ← (C)
(C) ← (A7)
Bytes: 1
Cycles: 1
Encoding: 0 0 1 1 0 0 1 1
Semiconductor Group 238
Instruction Set
RR A
Function: Rotate accumulator right
Description: The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into
the bit 7 position. No flags are affected.
Example: The accumulator holds the value 0C5 H (11000101 B ). The instruction
RR A
leaves the accumulator holding the value 0E2 H (11100010 B ) with the carry
unaffected.
Operation: RR
(An) ← (An + 1) n = 0-6
(A7) ← (A0)
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 0 1 1
Semiconductor Group 239
Instruction Set
RRC A
Function: Rotate accumulator right through carry flag
Description: The eight bits in the accumulator and the carry flag are together rotated one bit to
the right. Bit 0 moves into the carry flag; the original value of the carry flag moves
into the bit 7 position. No other flags are affected.
Example: The accumulator holds the value 0C5 H (11000101 B ), the carry is zero. The
instruction
RRC A
leaves the accumulator holding the value 62 H (01100010 B ) with the carry set.
Operation: RRC
(An) ← (An + 1) n=0-6
(A7) ← (C)
(C) ← (A0)
Bytes: 1
Cycles: 1
Encoding: 0 0 0 1 0 0 1 1
Semiconductor Group 240
Instruction Set
SETB <bit>
Function: Set bit
Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any
directiy addressable bit. No other flags are affected.
Example: The carry flag is cleared. Output port 1 has been written with the value 34 H
(00110100 B ). The instructions
SETB C
SETB P1.0
will leave the carry flag set to 1 and change the data output on port 1 to 35 H
(00110101 B ).
SETB C
Operation: SETB
(C) ← 1
Bytes: 1
Cycles: 1
SETB bit
Operation: SETB
(bit) ← 1
Bytes: 2
Cycles: 1
Encoding: 1 1 0 1 0 0 1 1
Encoding: 1 1 0 1 0 0 1 0 bit address
Semiconductor Group 241
Instruction Set
SJMP rel
Function: Short jump
Description: Program control branches unconditionally to the address indicated. The branch
destination is computed by adding the signed displacement in the second
instruction byte to the PC, after incrementing the PC twice. Therefore, the range of
destinations allowed is from 128 bytes preceding this instruction to 127 bytes
following it.
Example: The label ”RELADR” is assigned to an instruction at program memory location
0123 H . The instruction
SJMP RELADR
will assemble into location 0100 H . After the instruction is executed, the PC will
contain the value 0123 H .
Note:
Under the above conditions the instruction following SJMP will be at 102 H .
Therefore, the displacement byte of the instruction will be the relative offset (0123 H -
0102 H ) = 21 H . In other words, an SJMP with a displacement of 0FE H would be a
one-instruction infinite loop.
Operation: SJMP
(PC) ← (PC) + 2
(PC) ← (PC) + rel
Bytes: 2
Cycles: 2
Encoding: 1 0 0 0 0 0 0 0 rel. address
Semiconductor Group 242
Instruction Set
SUBB A, <src-byte>
Function: Subtract with borrow
Description: SUBB subtracts the indicated variable and the carry flag together from the
accumulator, leaving the result in the accumulator. SUBB sets the carry (borrow)
flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set before
executing a SUBB instruction, this indicates that a borrow was needed for the
previous step in a multiple precision subtraction, so the carry is subtracted from the
accumulator along with the source operand). AC is set if a borrow is needed for bit
3, and cleared otherwise. OV is set if a borrow is needed into bit 6 but not into bit 7,
or into bit 7 but not bit 6.
When subtracting signed integers OV indicates a negative number produced when
a negative value is subtracted from a positive value, or a positive result when a
positive number is subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register-
indirect, or immediate.
Example: The accumulator holds 0C9 H (11001001 B ), register 2 holds 54 H (01010100 B ), and
the carry flag is set. The instruction
SUBB A,R2
will leave the value 74 H (01110100 B ) in the accumulator, with the carry flag and AC
cleared but OV set.
Notice that 0C9 H minus 54 H is 75 H . The difference between this and the above
result is due to the (borrow) flag being set before the operation. If the state of the
carry is not known before starting a single or multiple-precision subtraction, it should
be explicitly cleared by a CLR C instruction.
SUBB A,Rn
Operation: SUBB
(A) ← (A) – (C) – (Rn)
Bytes: 1
Cycles: 1
Encoding: 1 0 0 1 1 r r r
Semiconductor Group 243
Instruction Set
SUBB A,direct
Operation: SUBB
(A) ← (A) – (C) – (direct)
Bytes: 2
Cycles: 1
SUBB A, @ Ri
Operation: SUBB
(A) ← (A) – (C) – ((Ri))
Bytes: 1
Cycles: 1
SUBB A, #data
Operation: SUBB
(A) ← (A) – (C) – #data
Bytes: 2
Cycles: 1
Encoding: 1 0 0 1 0 1 0 1 direct address
Encoding: 1 0 0 1 0 1 1 i
Encoding: 1 0 0 1 0 1 0 0 immediate data
Semiconductor Group 244
Instruction Set
SWAP A
Function: Swap nibbles within the accumulator
Description: SWAP A interchanges the low and high-order nibbles (four-bit fields) of the
accumulator (bits 3-0 and bits 7-4). The operation can also be thought of as a four-
bit rotate instruction. No flags are affected.
Example: The accumulator holds the value 0C5 H (11000101 B ). The instruction
SWAP A
leaves the accumulator holding the value 5C H (01011100 B ).
Operation: SWAP
(A3-0) (A7-4), (A7-4) ← (A3-0)
Bytes: 1
Cycles: 1
Encoding: 1 1 0 0 0 1 0 0
←
→
Semiconductor Group 245
Instruction Set
XCH A, <byte>
Function: Exchange accumulator with byte variable
Description: XCH loads the accumulator with the contents of the indicated variable, at the same
time writing the original accumulator contents to the indicated variable. The source/
destination operand can use register, direct, or register-indirect addressing.
Example: R0 contains the address 20 H . The accumulator holds the value 3F H (00111111 B ).
Internal RAM location 20 H holds the value 75 H (01110101 B ). The instruction
XCH A, @R0
will leave RAM location 20 H holding the value 3F H (00111111 B ) and 75 H
(01110101 B ) in the accumulator.
XCH A,Rn
Operation: XCH
(A) (Rn)
Bytes: 1
Cycles: 1
XCH A,direct
Operation: XCH
(A) (direct)
Bytes: 2
Cycles: 1
Encoding: 1 1 0 0 1 r r r
Encoding: 1 1 0 0 0 1 0 1 direct address
←
→
←
→
Semiconductor Group 246
Instruction Set
XCH A, @ Ri
Operation: XCH
(A) ((Ri))
Bytes: 1
Cycles: 1
Encoding: 1 1 0 0 0 1 1 i
←
→
Semiconductor Group 247
Instruction Set
XCHD A,@Ri
Function: Exchange digit
Description: XCHD exchanges the low-order nibble of the accumulator (bits 3-0, generally
representing a hexadecimal or BCD digit), with that of the internal RAM location
indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of
each register are not affected. No flags are affected.
Example: R0 contains the address 20 H . The accumulator holds the value 36 H (00110110 B ).
Internal RAM location 20 H holds the value 75 H (01110101 B ). The instruction
XCHD A, @ R0
will leave RAM location 20 H holding the value 76 H (01110110 B ) and 35 H
(00110101 B ) in the accumulator.
Operation: XCHD
(A3-0) ((Ri)3-0)
Bytes: 1
Cycles: 1
Encoding: 1 1 0 1 0 1 1 i
←
→

XRL <dest-byte>, <src-byte>

Function: Logical Exclusive OR for byte variables
Description: XRL performs the bitwise logical Exclusive OR operation between the indicated variables, storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or
immediate addressing; when the destination is a direct address, the source can be accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Example: If the accumulator holds 0C3 H (11000011 B ) and register 0 holds 0AA H (10101010B) then the instruction
XRL A,R0
will leave the accumulator holding the value 69 H (01101001 B ).
When the destination is a directly addressed byte, this instruction can complement combinations of bits in any RAM location or hardware register. The pattern of
bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the accumulator at run-time.
The instruction
XRL P1,#00110001B
will complement bits 5, 4, and 0 of output port 1.

XRL A,Rn
Operation: XRL2
(A) ← (A) (Rn)
Bytes: 1
Cycles: 1
Encoding: 01101rrr

XRL A,direct
Operation: XRL
(A) ← (A) (direct)
Bytes: 2
Cycles: 1
Encoding: 0 1 1 0 0 1 0 1 direct address

XRL A, @ Ri
Operation: XRL
(A) ← (A) ((Ri))
Bytes: 1
Cycles: 1
Encoding: 0110011I
XRL A, #data
Operation: XRL
(A) ← (A) #data
Bytes: 2
Cycles: 1
Encoding: 0 1 1 0 0 1 0 0 immediate data

XRL direct,A
Operation: XRL
(direct) ← (direct) (A)
Bytes: 2
Cycles: 1
Encoding: 0 1 1 0 0 0 1 0 direct address
v
v
v
v

XRL direct, #data

Operation: XRL
(direct) ← (direct) #data
Bytes: 3
Cycles: 2
Encoding: 0 1 1 0 0 0 1 1 direct address immediate data

Instruction Set Summary

Arithmetic Operations
Mnemonic Description Byte Cycle
ADD A,Rn Add register to accumulator 1 1
ADD A,direct Add direct byte to accumulator 2 1
ADD A, @Ri Add indirect RAM to accumulator 1 1
ADD A,#data Add immediate data to accumulator 2 1
ADDC A,Rn Add register to accumulator with carry flag 1 1
ADDC A,direct Add direct byte to A with carry flag 2 1
ADDC A, @Ri Add indirect RAM to A with carry flag 1 1
ADDC A, #data Add immediate data to A with carry flag 2 1
SUBB A,Rn Subtract register from A with borrow 1 1
SUBB A,direct Subtract direct byte from A with borrow 2 1
SUBB A,@Ri Subtract indirect RAM from A with borrow 1 1
SUBB A,#data Subtract immediate data from A with borrow 2 1
INC A Increment accumulator 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 1
INC @Ri Increment indirect RAM 1 1
DEC A Decrement accumulator 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 1
DEC @Ri Decrement indirect RAM 1 1
INC DPTR Increment data pointer 1 2
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 4
DA A Decimal adjust accumulator 1 1

Logic Operations
Mnemonic Description Byte Cycle
ANL A,Rn AND register to accumulator 1 1
ANL A,direct AND direct byte to accumulator 2 1
ANL A,@Ri AND indirect RAM to accumulator 1 1
ANL A,#data AND immediate data to accumulator 2 1
ANL direct,A AND accumulator to direct byte 2 1
ANL direct,#data AND immediate data to direct byte 3 2
ORL A,Rn OR register to accumulator 1 1
ORL A,direct OR direct byte to accumulator 2 1
ORL A,@Ri OR indirect RAM to accumulator 1 1
ORL A,#data OR immediate data to accumulator 2 1
ORL direct,A OR accumulator to direct byte 2 1
ORL direct,#data OR immediate data to direct byte 3 2
XRL A,Rn Exclusive OR register to accumulator 1 1
XRL A direct Exclusive OR direct byte to accumulator 2 1
XRL A,@Ri Exclusive OR indirect RAM to accumulator 1 1
XRL A,#data Exclusive OR immediate data to accumulator 2 1
XRL direct,A Exclusive OR accumulator to direct byte 2 1
XRL direct,#data Exclusive OR immediate data to direct byte 3 2
CLR A Clear accumulator 1 1
CPL A Complement accumulator 1 1
RL A Rotate accumulator left 1 1
RLC A Rotate accumulator left through carry 1 1
RR A Rotate accumulator right 1 1
RRC A Rotate accumulator right through carry 1 1
SWAP A Swap nibbles within the accumulator 1 1

Data Transfer
1) MOV A,ACC is not a valid instruction
Mnemonic Description Byte Cycle
MOV A,Rn Move register to accumulator 1 1
MOV A,direct 1) Move direct byte to accumulator 2 1
MOV A,@Ri Move indirect RAM to accumulator 1 1
MOV A,#data Move immediate data to accumulator 2 1
MOV Rn,A Move accumulator to register 1 1
MOV Rn,direct Move direct byte to register 2 2
MOV Rn,#data Move immediate data to register 2 1
MOV direct,A Move accumulator to direct byte 2 1
MOV direct,Rn Move register to direct byte 2 2
MOV direct,direct Move direct byte to direct byte 3 2
MOV direct,@Ri Move indirect RAM to direct byte 2 2
MOV direct,#data Move immediate data to direct byte 3 2
MOV @Ri,A Move accumulator to indirect RAM 1 1
MOV @Ri,direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate data to indirect RAM 2 1
MOV DPTR, #data16 Load data pointer with a 16-bit constant 3 2
MOVC A,@A + DPTR Move code byte relative to DPTR to accumulator 1 2
MOVC A,@A + PC Move code byte relative to PC to accumulator 1 2
MOVX A,@Ri Move external RAM (8-bit addr.) to A 1 2
MOVX A,@DPTR Move external RAM (16-bit addr.) to A 1 2
MOVX @Ri,A Move A to external RAM (8-bit addr.) 1 2
MOVX @DPTR,A Move A to external RAM (16-bit addr.) 1 2
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A,Rn Exchange register with accumulator 1 1
XCH A,direct Exchange direct byte with accumulator 2 1
XCH A,@Ri Exchange indirect RAM with accumulator 1 1
XCHD A,@Ri Exchange low-order nibble indir. RAM with A 1 1

Boolean Variable Manipulation

Mnemonic Description Byte Cycle
CLR C Clear carry flag 1 1
CLR bit Clear direct bit 2 1
SETB C Set carry flag 1 1
SETB bit Set direct bit 2 1
CPL C Complement carry flag 1 1
CPL bit Complement direct bit 2 1
ANL C,bit AND direct bit to carry flag 2 2
ANL C,/bit AND complement of direct bit to carry 2 2
ORL C,bit OR direct bit to carry flag 2 2
ORL C,/bit OR complement of direct bit to carry 2 2
MOV C,bit Move direct bit to carry flag 2 1
MOV bit,C Move carry flag to direct bit 2 2

Program and Machine Control

Mnemonic Description Byte Cycle
ACALL addr11 Absolute subroutine call 2 2
LCALL addr16 Long subroutine call 3 2
RET Return from subroutine 1 2
RETI Return from interrupt 1 2
AJMP addr11 Absolute jump 2 2
LJMP addr16 Long iump 3 2
SJMP rel Short jump (relative addr.) 2 2
JMP @A + DPTR Jump indirect relative to the DPTR 1 2
JZ rel Jump if accumulator is zero 2 2
JNZ rel Jump if accumulator is not zero 2 2
JC rel Jump if carry flag is set 2 2
JNC rel Jump if carry flag is not set 2 2
JB bit,rel Jump if direct bit is set 3 2
JNB bit,rel Jump if direct bit is not set 3 2
JBC bit,rel Jump if direct bit is set and clear bit 3 2
CJNE A,direct,rel Compare direct byte to A and jump if not equal 3 2
CJNE A,#data,rel Compare immediate to A and jump if not equal 3 2
CJNE Rn,#data rel Compare immed. to reg. and jump if not equal 3 2
CJNE @Ri,#data,rel Compare immed. to ind. and jump if not equal 3 2
DJNZ Rn,rel Decrement register and jump if not zero 2 2
DJNZ direct,rel Decrement direct byte and jump if not zero 3 2
NOP No operation 1 1