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Example For Blocking Statements

This document contains the code for a Verilog module called "blocking" that demonstrates blocking assignments. It initializes variables like x, y, z and registers reg_a and reg_b with blocking assignments. It also increments an integer counter with a blocking assignment and uses delays and monitoring to show the blocking behavior over time.

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J Venkatesh
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
20 views

Example For Blocking Statements

This document contains the code for a Verilog module called "blocking" that demonstrates blocking assignments. It initializes variables like x, y, z and registers reg_a and reg_b with blocking assignments. It also increments an integer counter with a blocking assignment and uses delays and monitoring to show the blocking behavior over time.

Uploaded by

J Venkatesh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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blocking.

v Thu Jul 28 20:17:22 2016


1 `timescale 1ns / 1ps
2 //////////////////////////////////////////////////////////////////////////////////
3 // Company:
4 // Engineer:
5 //
6 // Create Date: 07:24:56 07/28/2016
7 // Design Name:
8 // Module Name: blocking
9 // Project Name:
10 // Target Devices:
11 // Tool versions:
12 // Description:
13 //
14 // Dependencies:
15 //
16 // Revision:
17 // Revision 0.01 - File Created
18 // Additional Comments:
19 //
20 //////////////////////////////////////////////////////////////////////////////////
21 module blocking(
22 );
23 reg x, y, z;
24 reg [15:0] reg_a, reg_b;
25 integer count;
26 //All behavioral statements must be inside an initial or always block
27 initial
28 begin
29 x = 0; y = 1; z = 1; //Scalar assignments
30 count = 0; //Assignment to integer variables
31 reg_a = 16'b0; reg_b = reg_a; //initialize vectors
32 #15 reg_a[2] = 1'b1; //Bit select assignment with delay
33 #10 reg_b[15:13] = {x, y, z}; //Assign result of concatenation to part
select of a vector
34 count = count + 1; //Assignment to an integer (increment)
35 end
36 initial $monitor($time, " \t x=%b, y=%b, z=%b, reg_a=%b, reg_b=%b, count=%d \t", x,y,z
,reg_a, reg_b, count);
37 endmodule
38

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