Interrupts

Two type of interrupts:

1.Hardware interrupt: An external input

to the CPU that alters the Program
Sequence.
2.Software interrupt: caused by the
execution of special instructions that also
alter the Program Sequence.
Interrupts…
 Interrupts…

The Interrupt illustration diagram shows

that when an interrupt occurs the execution
of the main program is suspended, and an
Interrupt Service Routine (ISR) is called.
The main program execution resumes only
after the ISR has ended.
 Why Interrupts
1. Rare Events
 
Some events a CPU has to attend to occur very
rarely. In the absence of interrupts such events
would have to be attended through polling i.e.
checking for an event, a process that would
result in a 99.99% failure rate. Interrupts were
invented for the sake of avoiding polling in
order to enable the CPU operate more
efficiently. As such the CPU attends to an event
only when the event has indeed occurred.
 Why Interrupts..
2. Peripherals
Peripherals (i.e. printers, keyboards, storage disks
etc.) connected to a computer operate at a
much slower rate than the CPU (million times
slower). Letting a CPU send data to a
peripheral at its own rate would inevitably
cause a lot of data loss. As such these
peripherals are often handled through
interrupts. This ensures that data is only sent
to a peripheral when the peripheral is ready to
receive data, Or data is read only when the
peripheral has presented data.
Why Interrupts..
 Why Interrupts..
3. Counter/Timer Control
 
Letting a CPU enter into a Delay loop just to
wait for a time duration to expire is an
inefficient way of utilizing a CPU. The
solution to this is to use a timer. A CPU sets
the count on the timer/counter proportional
to the required time interval and proceeds to
do other tasks. The timer notifies the CPU
through an interrupt when the set time
interval expires.
Why Interrupts..
 General Interrupt System
- Special lines are provided on the CPU on
which interrupt signals can be applied.

- When a CPU has several interrupt lines, a

Priority Scheme is built in the system that
enables the CPU to determine which
interrupt is to be serviced first in case
more than 1 interrupt occur
simultaneously.
 General Interrupt System…
- Each interrupt has a reserved
memory location to where the CPU
automatically goes whenever the
interrupt occurs.

- Some interrupts can be enabled

and/or disabled.
 General Interrupt Processing
Procedure
The CPU checks for interrupt status towards
the end of the instruction cycle. When an
interrupt is detected the following procedure is
followed:

1. Complete current instruction

2.Disable further interrupts (to prevent one

interrupt interrupting another interrupt)
 General Interrupt Processing
Procedure..
3. Save the address of the next instruction
onto the stack.
4. Branch to the reserved address for the
interrupt from where it is directed to
the Interrupt Service Routine.
 General Interrupt Processing
Procedure..
5. When the ISR (Interrupt Service
Routine) ends the CPU returns to the
point it was interrupted using the return
address on the Stack. It is the
responsibility of the ISR programmer
to enable interrupts just before exiting
the ISR otherwise no further interrupts
would be recognized.
 Intel 8085 Hardware Interrupts

The CPU has got the following 5

hardware Interrupts given in order
of priority i.e. 1 Highest priority.
 Intel 8085 Hardware Interrupts…
Priority Interrupt Reserved Properties
Name Address

1. TRAP 4.5 x 8 = 24H - Non-maskable,

- Always enabled, and not
affected by Enable and Disable
Interrupt instructions
- Triggered by rising edge and
high level until sampled.

2. RST 7.5 7.5 x 8 = 3CH - Maskable,

- Can be enabled or disabled by
EI or DI instructions.
- Rising edge triggered
 Intel 8085 Hardware Interrupts…
Priority Interrupt Reserved Properties
Name Address

3. RST 6.5 6.5 x 8 = 34H - Maskable,

- Can be enabled or disabled
by EI or DI instructions
- High Level triggered

4. RST 5.5 5.5 x 8 = 2CH - Maskable,

- Can be enabled or disabled
by EI or DI instructions
- High Level triggered
 Intel 8085 Hardware Interrupts…
Priority Interrupt Reserved Properties
Name Address

5. INTR No Specific - Non-maskable;

address. - Can be enabled or disabled
Interrupting by EI or DI instructions
device has to - High Level triggered
provide
vectoring
information.
 Interrupt Masks

The SIM Register is used to mask

or unmask those interrupts
provided with a Mask. The SIM
Register is accessed through the
SIM Instruction that writes the
content of the Accumulator to the
SIM Register.
Intel 8085 SIM Register
 Masking/Unmasking Interrupts
For Maskable interrupts to be recognised the
Interrupt Mask has to be OFF and interrupts
have also got to be enabled. This is done by
writing a 0 to the bit for the respective
interrupt.

Example: Give a set of instructions that

makes sure that when Interrupt RST 6.5
Interrupt occurs it is recognised.
 Masking/Unmasking Interrupts
Refer to the bit definition of the SIM register.
The Mask for RST 6.5 is bit 1 which has to be
set to 0 (Off). To program the Masks SOE (bit
6) has to be set to 0 to disable Serial Output
and MSE (bit 3) has to be set to 1 to enable
interrupt masks programming.
With this in in mind the required bit pattern is
0DH (0000 1101).
 Masking/Unmasking Interrupts
The required instructions are:
MVI A,0DH ;Bit pattern to
SIM ;Unmask RST
;6.5 Interrupt
EI ;Enable Interrupts
 Masking/Unmasking Interrupts
Similarly more than 1 interrupt can be unmasked
simultaneously. For example to unmask both RST
7.5 and RST 5.5 interrupts the bit pattern is 0AH
(0000 1010)
MVI A,0AH ;Bit pattern to
SIM ;Unmask RST
;5.5 and RST 7.5
;Interrupts
EI ;Enable Interrupts
 Intel 8085 software Interrupts
There are 8 Software Interrupt instructions :
•RST 0
•RST 1
•RST 2
•RST 3
•RST 4
•RST 5
•RST 6
•RST 7
 The INTR Interrupt
Unlike other hardware interrupts that have got
a specific reserved address, the INTR has
none. Rather it expects an Interrupting device
to specify where to go. When it occurs the CPU
responds with an INTA (Interrupt
Acknowledge) signal and expects the
interrupting device to provide on the data bus a
code for an RST n instruction or a CALL
address instruction. In case an RST n
instruction is provided the CPU executes it
thereby eventually calling the relevant ISR.
 The INTR Interrupt…
The machine code instruction for the software
interrupt instructions RST 0 to RST 7 was
designed such that it is easier to generate a
software interrupt by hardware means. 5 of the 8
bits are at logic 1. Only 3 bits vary depending on
the instruction.
This makes it possible for the INTR line to
be used by 8 interrupting devices.
 RST n Machine Code
1 1 N N N 1 1 1

RST 0  NNN = 000  C7

RST 1  NNN = 001  CF
….
RST 7  NNN = 111  FF
Generating RST n Instruction by
Hardware Means
Generating RST n Instruction by
Hardware Means…
IRQ7 – IRQ0 Bit Pattern 8:3 Encoder Output
0000 0001 000
0000 0010 001
0000 0100 010
0000 1000 011
0001 0000 100
0010 0000 101
0100 0000 110
1000 0000 111
 Generating RST n Instruction by
Hardware Means…
With the remaining 5 bits hardwired to 5
Volts (logic 1) The circuit ensures the
buffer output represents a machine code for
an RST n instruction. Each device therefore
generates its own RST n instruction.
 Generating RST n Instruction by
Hardware Means…
The 8-input OR gate generates INTR signal
whenever an IRQ is active. The INTA from CPU
latches the Buffer output to the Data Bus from
where the CPU gets the required RST n instruction
to execute the ISR for the active IRQ.

The Disadvantage of this Circuit is it can not

handle more than 1 interrupt occurring
simultaneously. The comprehensive solution to
Interrupt Management is provided through the
Use of a Programmable Interrupt Controller.
Programmable Interrupt Controller
Generally there are Programmable Interrupt
Controller (PIC) chips like the Intel 8259
that are designed to mange interrupts.

The 8259 PIC has built-in registers that

help it manage interrupts. 8 interrupting
devices can be managed by this chip.
However several of them can be cascaded
to manage more interrupts.
The 8259A PIC
The 8259A PIC..
 PIC Registers
The 8259 built-in registers are:

IRR (Interrupt Request Register): This is an 8

bit register with each bit designated a specific
IRQ. When an interrupt occurs it is registered in
its respective bit. As such when several interrupts
occur simultaneously they are all registered. No
interrupt is missed.

IMR (Interrupt Mask Register) : This is an 8 bit

register with one bit for each IRQ. Used to mask
(disable) or enable IRQs.
 PIC Registers
ISR (In Service Register): Indicates which
interrupt is currently being serviced by the
CPU.

PRR (Priority Revolver Register) indicates

which interrupt is to be serviced next.

 
 The 8259 PIC
The PIC can operate in 2 modes i.e. The
Intel 8085 mode and Intel 80x86 mode.

In Intel 8085 mode, which we are interested

in, this PIC generates CALL instructions
and operates as follows with the Intel 8085
CPU.
 
 How the 8259 PIC Works with Intel
8085 CPU
- CPU first initializes the PIC with the
following :
 8085 mode
 Applicable Priority Scheme
 Applicable interrupt Masks Settings
 The gap in bytes (4 or 8) between
CALL addresses to be generated.
 The Uppermost 11 bits of the CALL
instruction addresses to be generated.
 How the 8259 PIC Works with Intel
8085 CPU…
- On getting an interrupt request the PIC
registers it in the Interrupt Request
Register. When there is no interrupt
being serviced the PIC generates an
Interrupt signal to the CPU which in
turn responds by asserting the Interrupt
Acknowledge Signal (INTA)
 
 How the 8259 PIC Works with Intel
8085 CPU…
- On receiving the INTA signal the PIC
responds by placing the machine code for the
CALL instruction onto the Data Bus. On
receiving the CALL machine code the CPU
responds by asserting the 2nd INTA signal to
which the PIC responds by placing the lower
byte of the relevant ISR address determined by
the preset 3 MSB bits and the remaining 5 bits
from the IRQ number and the preset memory
gap between interrupt call addresses.
 How the 8259 PIC Works with Intel
8085 CPU…

- After collecting the lower byte of the

ISR address, the CPU responds with
the 3rd INTA signal to which the PIC
places the predefined upper byte of
the ISR onto the Data Bus thereby
completing the CALL instruction.
 How the 8259 PIC Works with Intel
8085 CPU…

- On getting the upper byte of the ISR

address the CPU executes the CALL
instruction hence the ISR.
 How the 8259 PIC Works with Intel
8085 CPU…
- Just before the ISR completes the ISR
must send the End of Interrupt
Command that indicates to the PIC the
current Request has already been
serviced The PIC is then free to generate
another interrupt if more are pending,
and thus the above sequence is repeated.
The entire Interrupt System collapses if
the ISR does not send the End of
Interrupt command before exiting.