NCP1380

Quasi-Resonant
Current-Mode Controller for
High-Power Universal
Off-Line Supplies
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The NCP1380 hosts a high−performance circuitry aimed to
powering quasi−resonant converters. Capitalizing on a proprietary QUASI−RESONANT PWM
valley−lockout system, the controller shifts gears and reduces the
switching frequency as the power loading becomes lighter. This CONTROLLER FOR HIGH
results in a stable operation despite switching events always occurring POWER AC−DC WALL
in the drain−source valley. This system works down to the 4th valley ADAPTERS
and toggles to a variable frequency mode beyond, ensuring an
excellent standby power performance. MARKING
To improve the safety in overload situations, the controller includes DIAGRAMS
an Over Power Protection (OPP) circuit which clamps the delivered
8
power at high−line. Safety−wise, a fixed internal timer relies on the
SOIC−8 1380X
feedback voltage to detect a fault. Once the timer elapses, the 8 D SUFFIX ALYWX
controller stops and stays latched for option A and C or enters 1 CASE 751 G
auto−recovery mode for option B and D. 1
Particularly well suited for adapter applications, the controller
features a pin to implement either a combined overvoltage / 1380X = Specific Device Code
overtemperature protection (Version A and B) or a combined X = Device Option (A, B, C, or D)
brown−out/overvoltage protection (Version C and D). A = Assembly Location
L = Wafer Lot
Features Y = Year
• Quasi−Resonant Peak Current−Mode Control Operation W = Work Week
G = Pb−Free Package
• Valley Switching Operation with Valley−Lockout for Noise−Immune
Operation
• Frequency Foldback at Light Load to Improve the Light Load PIN CONNECTIONS
Efficiency
ZCD 1 8 CT
• Adjustable Over Power Protection
• Auto−Recovery or Latched Internal Output Short−Circuit Protection FB 2 7 FAULT
• Fixed Internal 80 ms Timer for Short−Circuit Protection
CS 3 6 VCC
• Combined Overvoltage and Overtemperature Protection (A and B
Versions) GND 4 5 DRV
• Combined Overvoltage Protection and Brown−Out (C and D
Versions)
• +500 mA / −800 mA Peak Current Source/Sink Capability
• Internal Temperature Shutdown ORDERING INFORMATION
See detailed ordering and shipping information in the package
• Direct Optocoupler Connection dimensions section on page 25 of this data sheet.
• Extended VCC Range Operation Up to 28 V
• Extremely Low No−Load Standby Power
• SO−8 Package
• These Devices are Pb−Free and are RoHS Compliant

Typical Applications
• High Power ac−dc Converters for TVs, Set−Top Boxes etc.
• Offline Adapters for Notebooks

© Semiconductor Components Industries, LLC, 2009 1 Publication Order Number:

December, 2009 − Rev. 1 NCP1380/D
 NCP1380

TYPICAL APPLICATION EXAMPLE

HV−Bulk

Vout

NCP1380 A/B GND

ZCD / OPP 1 8
2 7 OVP / OTP
3 6
4 5

GND
Figure 1. Typical Application Schematic for A and B Versions

HV−Bulk

Vout

NCP1380 C/D GND

ZCD / OPP1 8
2 7 BO / OVP
3 6
4 5

GND
Figure 2. Typical Application Schematic for C and D Versions

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 NCP1380

PIN FUNCTION DESCRIPTION

Pin N5 Pin Name Function Pin Description
1 ZCD Zero Crossing Detection Connected to the auxiliary winding, this pin detects the core
reset event.
Adjust the over power protection Also, injecting a negative voltage smaller than 0.3 V on this
pin will perform over power protection.
2 FB Feedback pin Hooking an optocoupler collector to this pin will allow
regulation.

3 CS Current sense This pin monitors the primary peak.

4 GND − The controller ground
5 DRV Driver output The driver’s output to an external MOSFET
6 VCC Supplies the controller This pin is connected to an external auxiliary voltage.
7 Fault Over voltage and Over temperature Pulling this pin down with an NTC or up with a zener diode
protection (A and B versions) allows to latch the controller.

Over−voltage and Brown−out This pin observes the HV rail and protects the circuit in
protection (C and D versions) case of low main conditions. It also offers a way to latch the
circuit in case of over voltage event.

8 CT Timing capacitor A capacitor connected to this pin acts as the timing

capacitor in foldback mode.

NCP1380 OPTIONS
Auto−Recovery Latched
Overcurrent Overcurrent
OTP OVP Brown−Out Protection Protection
NCP1380 / A Yes Yes Yes
NCP1380 / B Yes Yes Yes
NCP1380 / C Yes Yes Yes
NCP1380 / D Yes Yes Yes

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 NCP1380

INTERNAL CIRCUIT ARCHITECTURE

VDD

BO r eset aux

VCC
latch V CC management
VDD VDD

fa ul t VCCstop
Rpullup gr a nd
reset
FB

L OGI C BL OCK

VDD clamp

ICt DRV
Ct gr a nd
+ DRV reset ga te

Ct s e tpoi nt −

Q
Q
Ct S
Discharge Cs S top
ZCD
+ A: GN D
de ma g
l a tc he d
−
10 V
ESD Vth

S
DRV Q Up
3 ms blanking IpFlag
Q TIM ER
La ux
P W Mr eset Down
Reset
R
SS end 40 ms gr a nd
Ti me Out reset
/4
The 40 ms Time Out is active
only during s oft−s ta r t
VOVP
noi s e de l a y VDD VCC
5 ms −
SS end Ti me Out + IOTP(REF)
Ipeak(VCO) = 17.5% VILIMIT PWMreset
− Fa ul t
CS
LEB 1
+
IpFlag
Rsense noi s e de l a y
OPP
−
+

+ VOTP
VILIMIT
Soft-start −
SS end
Soft−s ta rt e nd ? the n 1
else 0 CsS top
SS end
LEB 2 +
−
LEB 2 is shorter than LEB 1
VC S(stop)

Figure 3. Internal Circuit Architecture for Versions A and B

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 NCP1380

VDD

BO reset aux

VCC
latch V CC management
VDD
VDD
fa ul t VCCstop
R pul l up gr a nd
reset
FB

LOGIC BLOCK

VDD clamp

ICt DRV
Ct DRV gr a nd
+ ga te
reset
Ct se tpoint −

Q
QS
Ct
discharge
ZCD
+ C: GN D
de ma g
l a tc he d
− CsS top
10 V
ESD Vth

S I pFl a g
DRV 3 ms blanking Q Up
Q TIMER
La ux
Down
SS end R Res et
40 ms P W Mreset
Time Out gr a nd
reset
/4 The 40 ms Time Out is active
only during s oft−s ta r t

5 ms nois e de la y
SS end + VCC HV
Time Out
−
Ipeak(VCO) = 17.5% VILIMIT P W Mreset
− VOVP
CS
LEB 1
+
IpFlag VDD
Rsense OVP/BO
OPP IBO

VBO
+ noi s e de l a y
VILIMIT +
Soft-start −
−
Soft−s ta r t e nd ? the n 1 Rclamp
else 0 BO r es et
CsS top
SS end
LEB 2 + Vclamp
−
LEB 2 is shorter than LEB 1
VCS ( st op)

Figure 4. Internal Circuit Architecture for Versions C and D

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 NCP1380

MAXIMUM RATINGS TABLE

Symbol Rating Value Unit
VCC(MAX) Maximum Power Supply voltage, VCC pin, continuous voltage −0.3 to 28 V
ICC(MAX) Maximum current for VCC pin $30 mA

VDRV(MAX) Maximum driver pin voltage, DRV pin, continuous voltage −0.3 to 20 V
IDRV(MAX) Maximum current for DRV pin $1000 mA

VMAX Maximum voltage on low power pins (except pins DRV and VCC) −0.3 to 10 V
IMAX Current range for low power pins (except pins ZCD, DRV and VCC) $10 mA

IZCD(MAX) Maximum current for ZCD pin +3 / −2 mA

RqJA Thermal Resistance Junction−to−Air 120 °C/W
TJ(MAX) Maximum Junction Temperature 150 °C
Operating Temperature Range −40 to +125 °C
Storage Temperature Range −60 to +150 °C
ESD Capability, HBM model (Note 1) 4 kV
ESD Capability, CDM model (Note 1) 2 kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.
Charged Device Model 2000 V per JEDEC Standard JESD22−C101D
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V,
VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)

Symbol Condition Min Typ Max Unit

SUPPLY SECTION − STARTUP AND SUPPLY CIRCUITS
Supply Voltage V
VCC(on) Startup Threshold VCC increasing 16 17 18
VCC(off) Minimum Operating Voltage VCC decreasing 8.3 9 9.4
VCC(HYS) Hysteresis VCC(on) − VCC(off) 7.2 8.0 9.2
VCC(latch) Clamped VCC when latched−off VCC decreasing, ICC = 30 mA 6.2 7.2 8.2
VCC(reset) Internal logic reset 6 7 8

tVCC(off) VCC(off) noise filter − 5 − ms

tVCC(reset) VCC(reset) noise filter − 20 −

ICC(start) Startup current FB pin open − 10 20 mA

VCC = VCC(on) − 0.5 V

ICC(disch) Current that discharges VCC when the controller VCC = 12 V 3.0 4.0 5.0 mA
gets latched

ICC(latch) Current into VCC that keeps the controller latched VCC = VCC(latch) 30 − − mA
(Note 3)

Supply Current mA
ICC1 Device Disabled/Fault (Note 3) B, C, and D only VCC > VCC(off) − 1.7 2.0
ICC2 Device Enabled/No output load on pin 5 Fsw = 10 kHz − 1.7 2.0
ICC3A Device Switching (FSW = 65 kHz) CDRV = 1 nF, FSW = 65 kHz − 2.65 3.0
ICC3B Device Switching VCO mode CDRV = 1 nF, VFB = 1.25 V − 2.0 −
CURRENT COMPARATOR − CURRENT SENSE
VILIM Current Sense Voltage Threshold VFB = 4 V, VCS increasing 0.76 0.8 0.84 V
tLEB Leading Edge Blanking Duration for VILIM Minimum on time minus tILIM 210 275 330 ns
Ibias Input Bias Current (Note 3) DRV high −2 − 2 mA
3. Guaranteed by design.
4. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst)
5. If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear
6. Minimum value for TJ = 125°C
7. NTC with R110 = 8.8 kW.

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 NCP1380

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V,
VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)

Symbol Condition Min Typ Max Unit

CURRENT COMPARATOR − CURRENT SENSE
tILIM Propagation Delay VCS > VILIM to DRV turn−off − 125 175 ns
Ipeak(VCO) Percentage of maximum peak current level at VFB = 0.4 V, VCS increasing 15.4 17.5 19.6 %
which VCO takes over (Note 4)

VOPP(MAX) Setpoint decrease for VZCD = −300 mV (Note 5) VZCD = −300 mV, VFB = 4 V, 35 37.5 40 %
VCS increasing

VCS(stop) Threshold for immediate fault protection activation 1.125 1.200 1.275 V
tBCS Leading Edge Blanking Duration for VCS(stop) − 120 − ns
DRIVE OUTPUT − GATE DRIVE
Drive Resistance W
RSNK DRV Sink VDRV = 10 V − 12.5 −
RSRC DRV Source VDRV = 2 V − 20 −
Drive current capability mA
ISNK DRV Sink VDRV = 10 V − 800 −
ISRC DRV Source VDRV = 2 V − 500 −
tr Rise Time (10% to 90%) CDRV = 1 nF, VDRV from 0 to − 40 75 ns
12 V

tf Fall Time (90% to 10%) CDRV = 1 nF, VDRV from 0 to − 25 60 ns

12 V

VDRV(low) DRV Low Voltage VCC = VCC(off) + 0.2 V 8.4 9.1 − V

CDRV = 1 nF, RDRV = 33 kW
VDRV(high) DRV High Voltage (Note 6) VCC = VCC(MAX) 10.5 13.0 15.5 V
CDRV = 1 nF

DEMAGNETIZATION INPUT − ZERO VOLTAGE DETECTION CIRCUIT

VZCD(TH) ZCD threshold voltage VZCD decreasing 35 55 90 mV
VZCD(HYS) ZCD hysteresis VZCD increasing 15 35 55 mV
Input clamp voltage V
VCH High state Ipin1 = 3.0 mA 8 10 12
VCL Low state Ipin1 = −2.0 mA −0.9 −0.7 −0.3
tDEM Propagation Delay VZCD decreasing from 4 V to − 150 250 ns
−0.3 V

CPAR Internal input capacitance − 10 − pF

tBLANK Blanking delay after on−time 2.30 3.15 4.00 ms
toutSS Timeout after last demag transition During soft−start 28 41 54 ms
tout After the end of soft−start 5.0 5.9 6.7

RZCD(pdown) Pulldown resistor (Note 3) 140 320 500 kW

TIMING CAPACITOR
VCT(MAX) Maximum voltage on CT pin VFB < VFB(TH) 5.15 5.40 5.65 V
ICT Source current VCT = 0 V 18 20 22 mA
VCT(MIN) Minimum voltage on CT pin, discharge switch − − 90 mV
activated

CT Recommended timing capacitor value 220 pF

3. Guaranteed by design.
4. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst)
5. If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear
6. Minimum value for TJ = 125°C
7. NTC with R110 = 8.8 kW.

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 NCP1380

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V,
VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)

Symbol Condition Min Typ Max Unit

FEEDBACK SECTION
RFB(pullup) Internal pullup resistor 15 18 22 kW
Iratio Pin FB to current setpoint division ratio 3.8 4.0 4.2
VFB(TH) FB pin threshold under which CT is clamped to 0.26 0.3 0.34 V
VCT(MAX)

Valley threshold V
VH2D FB voltage where 1st valley ends and 2nd valley VFB decreases 1.316 1.4 1.484
starts
VH3D FB voltage where 2nd valley ends and 3rd valley VFB decreases 1.128 1.2 1.272
starts
VH4D FB voltage where 3rd valley ends and 4th valley VFB decreases 0.846 0.9 0.954
starts
VHVCOD FB voltage where 4th valley ends and VCO starts VFB decreases 0.732 0.8 0.828

VHVCOI FB voltage where VCO ends and 4th valley starts VFB increases 1.316 1.4 1.484

VH4I FB voltage where 4th valley ends and 3rd valley VFB increases 1.504 1.6 1.696
starts
VH3I FB voltage where 3rd valley ends and 2nd valley VFB increases 1.692 1.8 1.908
starts
VH2I FB voltage where 2nd valley ends and 1st valley VFB increases 1.880 2.0 2.120
starts
FAULT PROTECTION (ALL VERSIONS)
TSHDN Thermal Shutdown Device switching (FSW 140 − 170 °C
around 65 kHz)

TSHDN(HYS) Thermal Shutdown Hysteresis − 40 − °C

tOVLD Overload Timer VFB = 4 V, VCS > VILIM 75 85 95 ms
tSSTART Soft−start duration VFB = 4 V, VCS ramping up, 2.8 3.8 4.8 ms
measured from 1st DRV
pulse to VCS(peak) = 90% of
VILIM
RFault(clamp) Clamp series resistor 1.3 1.55 1.8 kW
VOVP Fault detection level for OVP VFault increasing 2.35 2.5 2.65 V
tlatch(delay) Delay before latch confirmation 22.5 30 37.5 ms
FAULT PROTECTION A & B VERSIONS
IOTP(REF) Reference current for direct connection of an VFault = VOTP + 0.2 V 85 91 97 mA
NTC (Note 7)

VOTP Fault detection level for OTP VFault decreasing 0.744 0.8 0.856 V
VFault(clamp) Clamped voltage (Fault pin left open) Fault pin open 1.13 1.35 1.57 V
FAULT PROTECTION C & D VERSIONS
VBO Brown−Out level VFault decreasing 0.744 0.8 0.856 V
IBO Sourced hysteresis current VFault > VBO VFault = VBO + 0.2 V 9 10 11 mA
tBO(delay) Delay before entering and exiting Brown−out 22.5 30 37.5 ms
VFault(clamp) Clamped voltage (Fault pin left open) Fault pin open 1.0 1.2 1.4 V
3. Guaranteed by design.
4. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst)
5. If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear
6. Minimum value for TJ = 125°C
7. NTC with R110 = 8.8 kW.

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 NCP1380

17.30 9.00

17.25 8.95

17.20 8.90
VCC(on), (V)

VCC(off), (V)
17.15 8.85

17.10 8.80

17.05 8.75

17.00 8.70
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 5. VCC(on) vs. Junction Temperature Figure 6. VCC(off) vs. Junction Temperature

1.90 2.80

1.80 2.70

1.70 ICC3A, (mA) 2.60

ICC2, (mA)

1.60 2.50

1.50 2.40

1.40 2.30

1.30 2.20
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 7. ICC2 vs. Junction Temperature Figure 8. ICC3A vs. Junction Temperature

2.40 10.0

2.30 9.5

2.20 9.0

8.5
ICC(start), (mA)

2.10
ICC3B, (mA)

2.00 8.0

1.90 7.5

1.80 7.0

1.70 6.5

1.60 6.0
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 9. ICC3B vs. Junction Temperature Figure 10. ICC(start) vs. Junction Temperature

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 NCP1380

810 330

805 310

800 290
VILIM, (mV)

TLEB, (ns)
795 270

790 250

785 230

780 210
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 11. VILIM vs. Junction Temperature Figure 12. TLEB vs. Junction Temperature

1.265 39.0

1.245 38.5

1.225
38.0
VOPP(max), (%)
VCS(stop), (V)

1.205
37.5
1.185
37.0
1.165

1.145 36.5

1.125 36.0
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. VCS(stop) vs. Junction Temperature Figure 14. VOPP(MAX) vs. Junction Temperature

9.4 14.5

14.0
9.3
13.5
9.2
VDRV(high), (V)
VDRV(low), (V)

13.0

9.1 12.5

12.0
9.0
11.5
8.9
11.0

8.8 10.5
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 15. VDRV(low) vs. Junction Temperature Figure 16. VDRV(high) vs. Junction Temperature

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 NCP1380

85 55

50
75
45

40

VZCD(hys), (V)
VZCD(th), (V)

65
35
55 30

25
45
20

35 15
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 17. VZCD(th) vs. Junction Temperature Figure 18. VZCD(hys) vs. Junction Temperature

3.50 49.0

3.40 47.0

45.0
3.30
TBLANK, (ms)

ToutSS, (ms)

43.0
3.20
41.0
3.10
39.0

3.0 37.0

2.90 35.0
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 19. TBLANK vs. Junction Temperature Figure 20. ToutSS vs. Junction Temperature

6.6 810

6.4
805
6.2
800
6.0
VOTP, (mV)
Tout, (ms)

5.8 795

5.6
790
5.4
785
5.2

5.0 780
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Tout vs. Junction Temperature Figure 22. VOTP vs. Junction Temperature

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 NCP1380

92.0 810

91.0 805

90.0 800

VBO, (mV)
IOTP, (mA)

89.0 795

88.0 790

87.0 785

86.0 780
−40 −20 0 20 40 60 80 100 120 −40 −20 0 20 40 60 80 100 120
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 23. IOTP vs. Junction Temperature Figure 24. VBO vs. Junction Temperature

10.4

10.2

10.0
IBO, (mA)

9.8

9.6

9.4

9.2
−40 −20 0 20 40 60 80 100 120

TJ, JUNCTION TEMPERATURE (°C)

Figure 25. IBO vs. Junction Temperature

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 NCP1380

APPLICATION INFORMATION

The NCP1380 implements a standard current−mode • Fault input (A and B versions): By combining a dual
architecture operating in quasi−resonant mode. Due to a threshold on the Fault pin, the controller allows the
proprietary circuitry, the controller prevents direct connection of an NTC to ground plus a zener
valley−jumping instability and steadily locks out in selected diode to a monitored voltage. In case the pin is brought
valley as the power demand goes down. Once the fourth below the OTP threshold by the NTC or above the OVP
valley is reached, the controller continues to reduce the threshold by the zener diode, the circuit permanently
frequency further down, offering excellent efficiency over latches−off and VCC is clamped to 7.2 V.
a wide operating range. Thanks to a fault timer combined to • Fault input (C and D versions): The C and D versions
an OPP circuitry, the controller is able to efficiently limit the
of NCP1380 include a brown−out circuit which safely
output power at high−line.
stops the controller in case the input voltage is too low.
• Quasi−Resonance Current−mode operation: Restart occurs via a complete startup sequence (latch
implementing quasi−resonance operation in peak reset and soft−start). During normal operation, the
current−mode control, the NCP1380 optimizes the voltage on this pin is clamped to Vclamp to give enough
efficiency by switching in the valley of the MOSFET room for OVP detection. If the voltage on this pin
drain−source voltage. Thanks to a proprietary circuitry, increases above 2.5 V, the part latches−off.
the controller locks−out in a selected valley and • Short−circuit protection: Short−circuit and especially
remains locked until the output loading significantly
over−load protections are difficult to implement when a
changes. When the load becomes lighter, the controller
strong leakage inductance between auxiliary and power
jumps into the next valley. It can go down to the 4th
windings affects the transformer (where the auxiliary
valley if necessary. Beyond this point, the controller
winding level does not properly collapse in presence of
reduces its switching frequency by freezing the peak
an output short). Here, when the internal 0.8 V
current setpoint. During quasi−resonance operation, in
maximum peak current limit is activated, the timer
case of very damped valleys, a 5.5 ms timer emulates
starts counting up. If the fault disappears, the timer
the missing valleys.
counts down. If the timer reaches completion while the
• Frequency reduction in light−load conditions: when error flag is still present, the controller stops the pulses.
the 4th valley is left, the controller reduces the This protection is latched on A and C version (the user
switching frequency which naturally improves the must unplug and re−plug the power supply to restart the
standby power by a reduction of all switching losses. controller) and auto−recovery on B and D versions (if
• Overpower protection (OPP): When the voltage on the fault disappears, the SMPS automatically resumes
ZCD pin swings in flyback polarity, a direct image if operation). In addition, all versions feature a winding
the input voltage is applied on ZCD pin. We can thus short−circuit protection, that senses the CS signal and
reduce the peak current depending of VZCD during the stops the controller if VCS reaches 1.5 x VILIM (after a
on−time. reduced LEB of tBCS). This additional comparator is
• Internal soft−start: A soft−start precludes the main enabled only during the main LEB duration tLEB, for
power switch from being stressed upon startup. Its noise immunity reason.
duration is fixed and equal to 4 ms.

NCP1380 OPERATING MODES

NCP1380 has two operating mode: quasi−resonant power.

operation and VCO operation for the frequency foldback. During VCO mode, the peak current decreases down to
The operating mode is fixed by the FB voltage as 17.5% of its maximum value and is then frozen. The
portrayed by Figure 26: switching frequency is variable and decreases as the
• Quasi−resonant operation occurs for FB voltage higher output load decreases.
than 0.8 V (FB decreasing) or higher than 1.4 V (FB The switching frequency is set by the end of charge of
increasing) which correspond to high output power and the capacitor connected to the CT pin. This capacitor is
medium output power. The peak current is variable and charged with a constant current source and the
is set by the FB voltage divided by 4. capacitor voltage is compared to an internal threshold
• Frequency foldback or VCO mode occurs for FB fixed by FB voltage. When this capacitor voltage
voltage lower than 0.8 V (FB decreasing) or lower than reaches the threshold the capacitor is rapidly discharged
1.4 V (FB increasing). This corresponds to low output down to 0 V and a new period start.

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 NCP1380

Figure 26. Operating Valley According to FB Voltage

VALLEY DETECTION AND SELECTION

The valley detection is done by monitoring the detected, an internal counter is incremented. The
voltage of the auxiliary winding of the transformer. A operating valley (1st, 2nd, 3rd or 4th) is determined by
valley is detected when the voltage on pin 1 crosses the FB voltage as shown by Figure 26.
down the 55 mV internal threshold. When a valley is
VDD VDD

Rpullup

FB V FB

LOGIC BLOCK
V FBth
VDD

S DRV
ICt Q
Ct
Q
+

−
R
Ct setpoint

Tim e Out CS comparator

Ct
Discharge

ZCD
+
de m a g
−
10 V
ES D Vth leakage
blanking

3 us puls e
DRV

La ux

Figure 27. Valley Detection Circuit

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 NCP1380

As the output load decreases (FB voltage decreases), the necessary output power. This allows achieving very low
valleys are incremented from the first to the fourth. When standby power consumption.
the fourth valley is reached, if FB voltage further decreases The Figure 28 shows a simulation case where the output
below 0.8 V, the controller enters VCO mode. current of a 19 V, 60 W adapter decreases from 2.8 A to
During VCO operation, the peak current continues to 0.1 A. No instability is seen during the valley transitions
decrease until it reaches 17.5% of the maximum peak (Figures 29, 30, 31 and 32)
current: the switching frequency expands to deliver the

Figure 28. Output Load is Decreased from 2.8 A Down to 100 mA at 120 Vdc Input Voltage

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 NCP1380

Figure 29. Zoom 1: 1st to 2nd Valley Transition

Figure 30. Zoom 2: 2nd to 3rd Valley Transition

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 NCP1380

Figure 31. Zoom 3: 3rd to 4th Valley Transition

Figure 32. Zoom 4: 4th Valley to VCO Mode Transition

Time Out
In case of extremely damped free oscillations, the ZCD introduced by the Over Power Compensation diode
comparator can be unable to detect the valleys. To avoid (Figure 40), the voltage on the ZCD pin is very low and the
such situation, NCP1380 integrates a Time Out function that ZCD comparator might be unable to detect the valleys. In
acts as a substitute clock for the decimal counter inside the this condition, setting the DRV Latch with the 5.5 ms
logic bloc. The controller thus continues its normal time−out can lead to a continuous conduction mode
operation. To avoid having a too big step in frequency, the operation (CCM) at the beginning of the soft−start. This
time out duration is set to 5.5 ms. Figures 34 and 35 detail the CCM operation only last a few cycles until the voltage on
time out operation. ZCD pin becomes high enough to be detected by the ZCD
The NCP1380 also features an extended time out during comparator. To avoid this, the time−out duration is extended
the soft−start. to 40 ms during the soft−start in order to ensure that the
Indeed, at startup, the output voltage reflected on the transformer is fully demagnetized before the MOSFET is
auxiliary winding is low. Because of the voltage drop turned−on.

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 NCP1380

VDD
ZC D
+
demag
−
10 V LOGI C BL OCK
ES D Vth
leakage blanking

3 us pulse
DRV

TimeOut
SS e nd

5.5 us time out

SS e nd

40 us time out

Figure 33. Time Out Circuit

Figure 34. Time Out Case n51: the 3rd Valley is Missing

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 NCP1380

Figure 35. Time Out Case n52: the 3rd and 4th Valley are Missing

VCO MODE OR FREQUENCY FOLDBACK

VCO operation occurs for FB voltage lower than 0.8 V Figure 27). When this capacitor voltage reaches the
(FB decreasing), or lower than 1.4 V (FB increasing). This threshold, the capacitor is rapidly discharged down to 0 V
corresponds to low output power. and a new period start. The internal threshold is inversely
During VCO operation, the peak current is fixed to 17.5% proportional to FB voltage. The relationship between VFB
of his maximum value and the frequency is variable and and VFBth is given by Equation 1.
expands as the output power decreases. V FBth + 6.5 * (10ń3)V FB (eq. 1)
The frequency is set by the end of charge of the capacitor
connected to the CT pin. This capacitor is charged with a When VFB is lower than 0.3 V, VCT is clamped to
constant current source and its voltage is compared to an VCT(MAX) which is typically 5.5 V. Figure 36 shows the
internal threshold (VFBth) fixed by FB voltage (see VCO mode at works.

Figure 36. In VCO Mode, as the Power Output Decreases, the Frequency Expands

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 NCP1380

SHORT−CIRCUIT OR OVERLOAD MODE

Figure 37 shows the implementation of the fault timer.

S
Q DRV Vd d
Q au x

R
VCC
VCC
management

latch
VC C sto p
fau l t grand
reset
CS CsStop
LEB1 + PW Mr eset
R sen se −
FB/4 Down
Up TIMER
IpFlag
ZCD/OPP OPP Reset

+ A&C:
Latched
V IL IM IT −

Soft−start SS en d
Soft −s t art end ?
S
t hen 1 Q
Laux else 0
Q
LEB2 + CsStop
R
−
grand
V CS(stop) reset

Figure 37. Overload Detection Schematic

When the current in the MOSFET is higher than VILIM / On A and C versions, when the timers finishes counting
Rsense, “Max Ip” comparator trips and the digital timer starts 80 ms, the circuit goes in latch mode (Figure 39): the DRV
counting: the timer count is incremented each 10 ms. When pulses stop and VCC is pulled down to VCC(latch) which is
the current comes back within safe limits, “Max Ip” 7.2 V typically. The circuit un−latches when the current
comparator becomes silent and the timer count down: the circulating in VCC pin drops below ICC(latch).
timer count is decremented each 10 ms. In normal overload In parallel to the cycle−by−cycle sensing of the CS pin,
conditions the timer reaches its completion when it has another comparator with a reduced LEB (tBCS) and a
counted up 8 times 10 ms. threshold of 1.2 V is able to sense winding short−circuit and
On B and D version, when the timers reaches its immediately shut down the controller. Depending on the
completion, the circuit enter auto−recovery mode: the version, this additional protection is either latched or
circuit stops all operations and VCC decreases via the circuit auto−recovery, according to the overload protection
own consumption (ICC1). When VCC reaches VCC(off), the behavior.
circuit goes in startup mode and restart switching. (see
Figure 38) This ensures a low duty−cycle burst operation in
fault mode.

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 NCP1380

Figure 38. Auto−Recovery Short−Circuit Protection on B and D Versions

Figure 39. Latched Short−Circuit Protection on A and C Versions

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 NCP1380

OVER POWER COMPENSATION

The over power compensation is achieved by monitoring the input voltage. As the auxiliary winding is already
the signal on ZCD pin (pin 1). Indeed, a negative voltage connected to ZCD pin for the valley detection, by selecting
applied on this pin directly affects the internal voltage the right values for Ropu and Ropl, we can easily perform
reference setting the maximum peak current (Figure 40). over power compensation.
When the power MOSFET is turned−on, the auxiliary
winding voltage becomes a negative voltage proportional to

Rz cd

Ropu
CS
ZCD/OPP OPP IpFlag
1

ESD
Ropl protection V IL IMIT
Au x

Demag
−
Vt h
leakage blanking

Tblank
DRV

Figure 40. Over Power Compensation Circuit

To ensure optimal zero−crossing detection, a diode is Design example:

needed to bypass Ropu during the off−time. Vaux = 18 V
If we apply the resistor divider law on the pin 1 during the Vd = 0.6 V
on−time, we obtain the following relationship: Np,aux = 0.18
R ZCD ) R opu N p,auxV in * V OPP If we want at least 8 V on ZCD pin, we have:
+* (eq. 2)
R opl V OPP R ZCD V aux * V d * V ZCD
+
R opl V ZCD
Where: (eq. 5)
Np,aux is the auxiliary to primary turn ration: Np,aux = Naux 18 * 0.6 * 8
+ [ 1.2
/ Np 8
Vin is the DC input voltage We can choose: RZCD = 1 kW and Ropl = 1 kW.
VOPP is the negative OPP voltage For the over power compensation, we need to decrease the
By selecting a value for Ropl, we can easily deduce Ropu peak current by 37.5% at high line (370 Vdc). The
using Equation 2. While selecting the value for Ropl, we corresponding OPP voltage is:
must be careful not choosing a too low value for this resistor
in order to have enough voltage for zero−crossing detection V OPP + 0.375 V ILIM + −300 mV (eq. 6)
during the off−time. We recommend having at least 8 V on Using Equation 2, we have:
ZCD pin, the maximum voltage being 10 V.
R ZCD ) R opu N p,auxV lin * V OPP
During the off−time, ZCD pin voltage can be expressed as +*
follows: R opt V OPP
(eq. 7)
R opl −0.18 370 * (−0.3)
ǒV aux * V dǓ (eq. 3) + + 221
V ZCD + (−0.3)
R ZCD ) R opl
We can thus deduce the relationship between Ropl and Thus,
RZCD: R opu + 221 Ropl * R ZCD + 221 1k * 1k + 220 kW
R ZCD V aux * V d * V ZCD (eq. 8)
+ (eq. 4)
R opl V ZCD

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 NCP1380

OVERVOLTAGE / OVERTEMPERATURE DETECTION (A AND B VERSIONS)

Overvoltage and overtemperature detection is achieved

by reading the voltage on pin 7 (See Figure 41).

VCC V OVP
VDD

nois e de lay
−
Dz
I OTP(REF) +

OVPcomp
Fa ult

7 S
Q Latch
nois e de lay
Rc l a mp −
Q
Clamp

+
NTC
OT Pc o mp R
Vclam p V OTP
grand
reset
SS end

Figure 41. OVP/OTP Circuitry

The IOTP(REF) current (91 mA typ.) biases the Negative In case of overvoltage, the zener diode starts to conduct
Temperature Coefficient sensor (NTC), naturally imposing and inject current inside the internal clamp resistor Rclamp
a dc voltage on the OTP pin. An internal clamp limit the thus causing the pin 7 voltage to increase. When this voltage
pin 7 voltage to 1.2 V when the NTC resistance is high (For reaches the OVP threshold (2.5 V typ), the controller is
example, at 25°C, RNTC > 100 kW). When the temperature latched−off: all the DRV pulses stops and VCC is
increases, the NTC’s resistance reduces bringing the pin 7 pulled−down to VCC(latch) (7.2 V typ). The circuit
voltage down until it reaches a typical value of 0.8 V: the un−latches when the current circulating in VCC pin drops
comparator trips and latches−off the controller (see below ICC(latch), thus the user must unplug and replug the
Figure 42). power supply.

Figure 42. Overvoltage and Overtemperature Chronograms

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 NCP1380

OVERVOLTAGE PROTECTION / BROWN−OUT (C AND D VERSIONS)

The C and D versions of NCP1380 combine brown−out

and overvoltage detection on pin 7.

HV−Bulk VCC noi s e de l a y

+
S DRV
− Q
Dz S
Q
VOVP Q La tc h
Rbou

OVP/BO Q
R
7 VDD
IBO R
gr a nd
Rbol reset
noi s e de l a y
−

Rc l a mp +
CS c omp
Clamp

BO reset
Vclamp
VBO

Figure 43. Brown−out and Overvoltage Protection

In order to protect the power supply against low input when VCC reaches VCC(on) (Figure 44): this ensures a clean
voltage condition, the pin 7 permanently monitors a fraction startup sequence with soft−start. The hysteresis for the
of the bulk voltage through a voltage divider. When this brown−out function is implemented with a high side current
image of bulk voltage is below the VBO threshold, the source sinking 10 mA when the brown−out comparator is
controller stops switching. When the bulk voltage comes high (Vbulk > Vbulk(on))
back within safe limits, the circuit will restart pulsing only

Figure 44. Brown−out Operating Chronograms

In order to avoid having a too high voltage on pin 7 if the Rclamp thus causing pin 7 voltage to increase. When this
bulk voltage is high, an internal clamp limits the voltage. voltage reaches VOVP, the controller latches−off and stays
In case of overvoltage, the zener diode will start to latched until the user cycles down the power supply
conduct and inject current inside the internal clamp resistor (Figure 45).

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 NCP1380

Figure 45. Operating Chronograms in Case of Overvoltage

The following equations show how to calculate the

brownout resistors.
ǒ
V BO V bulk(on) * V bulkǒoffǓ Ǔ
R bol + (eq. 9)
First of all, select the bulk voltage value at which the I BOǒV bulk(on) * V BOǓ
controller must start switching (Vbulk(on)) and the bulk
voltage for shutdown (Vbulk(off)). Then use the following R bolǒV bulk(on) * V BOǓ
equation to calculate Rbou and Rbol. R bou + (eq. 10)
V BO

ORDERING INFORMATION
Device Package Shipping†
NCP1380ADR2G SOIC−8 2500 / Tape & Reel
(Pb−Free)

NCP1380BDR2G SOIC−8 2500 / Tape & Reel

(Pb−Free)

NCP1380CDR2G SOIC−8 2500 / Tape & Reel

(Pb−Free)

NCP1380DDR2G SOIC−8 2500 / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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 NCP1380

PACKAGE DIMENSIONS

SOIC−8 NB
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
The products described herein (NCP1380), may be covered by one or more of the following U.S. patents; 6,362,067; 5,073,850. There may be other patents
pending.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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