ELEN E6316:

Analog Systems in VLSI

Nyquist-Rate: Flash ADCs

Columbia University
Spring 2020

Tod Dickson, Ph.D.

[email protected]
Research Staff Member, IBM T.J. Watson Research Center
Adjunct Professor, Columbia University

T. Dickson © 2020
 Flash Converter
Kelvin divider (resistive DAC)
generates 2N-1 levels.
O

binary
bit
2N-1 comparators simultaneously
compare the sampled input with all
= o b the levels generated by the DAC.
I

Output of all the comparators

produces a thermometer code,
I which in most cases needs to be
VR
Vr(2) decoded to a binary word.
going 1

up Vr(1)
High speed – all bits generated in a
All the a
single clock cycle.
zits cycle
← Typical resolution for straight flash
Resistive is up to 6b.
ladder T. Dickson © 2020
Flash ADC - Resistor Reference
small
make

gerdts
Kelvin divider DAC generates reference To the
voltages for the 2N-1 (or 2N) comparators. givestime
inputword to

pareto non -

i
'
g

Top and bottom resistors are half the other com deC
one
unit resistors (remember that ADC
a
:
transistions are offset by 0.5LSBs).
O
Edging
,
- -

i
Reference voltage at position i (from the O
l
bottom) given by l l
l
 i − 0 .5 
l i

Vr (i ) = Vref − + (Vref + − Vref − ) N 

I
2 -

 2 −1
'
-

firein
-

.
Toss set
-

(i = 1, 2, …, 2N-1)
Vr(2)
Process gradients have the same impact on I

INL as with the resistive divider DAC. Vr(1)

Only 1 comparator sees a “small-signal”

input (less than 0.5 LSB). This comparator +
decoding logic is usually what limits the flash
speed. Other comparators have large signal
differential input.
T. Dickson © 2020
 back
Flash ADC - Kickback redye shriek the

Joe
@
of
Also referred to as “flashback”
resistors
expenses
power

e.g., CLK and VIN+ are coupled

through CGD9 in series with CGS1

Exact mechanism depends on comparator

topology, but is usually the result of capacitive
coupling from clocks to the comparator inputs.
Strongly influenced by layout parasitics.

Comparator evaluation phase: S/H enters hold Will also get kickback onto the reference
mode (high impedance). Kickback charge from ladder. This can be alleviated by reducing
all comparators will get dumped onto the hold the ladder impedance (i.e., using smaller
capacitor. resistors), at the expense of power.

T. Dickson © 2020
 -Hi÷÷:¥÷
of
Thermometer-to-Binary Decoder :* .

Thermometer code from flash

And b2 b1 b0
0 0 comparators input to AND gates.

AND gates find the transition point in

0 0 the thermometer code, generate a 1-
out-of-N code.

Transit
0 1
1-of-N code drives a look-up table.
1 Selected row enables n-FET pull-down
0 devices, which generate the output
binary code.
1 0
Inversion at one input of the AND gate
1 0 comes for free if comparators have
differential outputs (i.e. Q and QB).
1
0 Top comparator not required for flash
architecture - used as an overflow/out-
of-range detect (logic not shown).
1
Kloof
1-of-N code up
table
T. Dickson © 2020
Bubble Errors (Sparkle Codes)
b2 b1 b0
3b thermometer code should be
0 0 00001111, but flash output could be
00001011 due to noise, comparator
0 0 metastability, or comparator offset.

0 0 Correct output code b2b1b0 should be

100, but is decoded as 110!
0 1
‘Bubble’ alludes to old mercury
thermometers, where a bubble in the
1 0
middle of the liquid can potentially form.

0 1 These kind of errors were called ‘sparkle’

codes in 70s video applications, as they
1 caused white dots to appear on TV
0
screens under certain conditions.
1
1-of-N code
T. Dickson © 2020
 Improved Decoder – AND3
0 b2 b1 b0
0

0 0
Improvement – Look at the output
0 0 of three adjacent comparators with
a three-input AND.
0 1 This can protect against a single
bubble error.
-

T
-

1 i 0
,

/
I
Disadvantage – higher loading on
0 0 comparator output nodes (you
'

y
! . could add extra buffers if you can
I
1
.
'

0
tolerate the added delay).
-

s T. Dickson © 2020
we cant have
O
above
 Comparator Offset Example
Comparator offsets will shift the ADC transition points, potentially
resulting in errors

Numerical example: A 6b flash with VFS =1V is being designed in a

65nm CMOS technology that has a threshold variance of AVT = 5mV ⋅ µm

Considering only threshold voltage mismatch, if the offset must be

less than 0.25LSBs, how large should the differential pair in a
comparator be if the design is to have 99.7% (3 sigma) yield?
VI 2
I LSB 12 AVT  12 ⋅ 5mV ⋅ µm 
-
2
-

2N
A 1 VFS 2
3 VT < WL >   =  = 14. 7456 µm
 VLSB   15.625mV 
N
WL 4 2
-36LSB 0.25

yield 14.7456µm 2 Huge comparator

threshold
variance
W=
0.065µm
= 227 µm →

will never
The flash
(The 3 sigma offset voltage is about 3.9mV) be fast

T. Dickson © 2020
Offset Calibration w/ DAC
As discussed earlier this semester, we can compensate latch offsets
using a DAC. How much resolution does the offset compensation DAC
need? Suppose the comparator input devices are 1µm wide.
Considering the previous example…

Maximum (3 sigma) offset voltage is

AVT 5mV ⋅ µm This should be the maximum
3 =3 = 59mV
WL 1µm × 0.065µm DAC output.
The DAC should bring the offset to within 0.25LSBs.
1 VFS 1V This is the maximum offset we can
⇐ N
= = 3.9mV
42 4 × 64 tolerate. Our DAC step size should
be this fine.
The DAC resolution is then the ratio of the full-scale to the step size.
59mV We need a 4b DAC for offset
← = 15
compensation.
-

Off 3.9mV
f
-
" on

Een
sa

T. Dickson © 2020
Conversion
step
Interpolation
2N buffers
l
2N aitches Pre-amplifiers required, which have
-

linear response in the region near zero

differential input. This results in finite
output slope. We can then interpolate
between the output of two adjacent
preamps.

Does not reduce the number of latches

as compared with straight flash ADC, but
input loading is reduced so S/H is faster.

Interpolation resistor string can limit

signal path bandwidth.

Interpolation > 2 can be used, but pre-

amp nonlinearities can result in uneven
step sizes (latch zero-crossings).
T. Dickson © 2020
 Folding ADC Architecture

Idea: Have two parallel ADCs process the MSBs and the LSBs. The fine ADC that
processes the LSBs needs a “folding” amplifier to reduce the signal range.

Advantage: Significant hardware reduction. A 6b ADC with M=3, N=3 requires 16

comparators plus folding amplifier. 6b flash would need 64 comparators.
-

T. Dickson © 2020
 Folding Amplifier Operation
The maximum output amplitude
from the folding amplifier is
capped at the LSB voltage
dictated by the folding resolution
-

(i.e., VFS/2M)
-

Output of folding amplifier can

be amplified to ease noise
requirements on the ‘fine’ N-bit
Vout ADC.
Vout
without
folding

2b folding 3b folding
(1/4th amplitude) (1/8th amplitude)

Vin Vin
0 1 2 3 0 1 2 3 4 5 6 7
M M
T. Dickson © 2020
 Folding Amplifier Implementation
CMOS implementation of a folding amplifier. Linearity is very important.

Down VR1 < VR2 < VR3 < VR4

up
For a given Vin, one
differential pair is in the
linear region. The others
are saturated.

1st folded 2nd folded 3rd folded 4th folded Offsets in the linear
sector sector sector sector transconductors will result
(polarity (polarity in DNL/INL. his is a concern
flip) flip) ft (non linear behavior
saturated ou put)
4x

Response of
single cell
Overall response
T. Dickson © 2020
Gain = RL 19312)
TR
 Folding Amplifier Nonlinearity
Rounding from Unfolded
folding amplifier equivalent
(even-order
nonlinearity)

Solution: Use two folding

amplifiers, whose transfer
characteristics are
staggered.

The “bad” regions of one

amplifier are not used – the
other amplifier is linear in
those regions.

T. Dickson © 2020
© 2020 T. Dickson
For student use in ELEN E6316
Unauthorized distribution is prohibited

T. Dickson © 2020