STLD LAB

DEPARTMENT
OF

ELECTRONICS AND COMMUNICATION

ENGINEERING

NAME OF THE LABORATORY : STLD LAB

YEAR AND SEMESTER : II – I

REGULATIONS : R19
NAME OF THE STUDENT :
SECTION :
ROLL NO :

DIGITAL IC APPLICATIONS LAB

OBSERVATION
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Vision and Mission of the Institute

Vision: To emerge as a Premier Institution for Technical Education in the Country through Academic
Excellence and to be recognized as a Centre for Excellence in Research & Development, catering to
the needs of our Country

Mission: To realize a strong Institution by consistently maintaining State – of – Art – infrastructure,

build a cohesive, World Class Team and provide need based Technical Education, Research and
Development through enhanced Industry Interaction

Vision and Mission of the Department

Vision: To be an acknowledged Leader in providing quality education, training and research in area
of Electronics and Communication Engineering to meet the industrial and Societal needs

Mission:
M1: To facilitate students with a state-of-the-art infrastructure, learning environment and value-based
education to improve technical knowledge and skills for continuous learning process.

M2: To impart high quality education with well qualified faculty and enable students to meet the
challenges of the industry at global level

M3: To promote innovation and active industry institute interaction by facilitating the students to
improve their leadership and entrepreneurship skills with ethical values.

Program Educational Objectives

PEO 1: To prepare Graduates with sound foundation in fundamentals of mathematics, science and
engineering to assist them exhibit strong, independent learning, analytical &problem-solving skills in
Electronics and Communication Engineering domain.

PEO 2: To facilitate learning in the core field with effective use of modern equipment and
programming tools to solve real life, multi-disciplinary problems with professional, ethical attitude and
also to make them aware of their social responsibilities.

PEO 3: To assist and enable individuals to imbibe lifelong learning in thrust areas related to research
& innovation to have Progressive Careers or Entrepreneurs.

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Program Outcomes

Engineering Knowledge: Apply the knowledge of mathematics, science, engineering

PO1 fundamentals and an engineering specialization to the solution of complex engineering
problems
Problem Analysis: Identify, formulate, review research literature, and analyze complex
PO2 engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
Design / Development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specified needs with
PO3
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
Conduct investigations of complex problems: Use research-based knowledge and
PO4 research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
Modern tool usage: Create, select, and apply appropriate techniques, resources, and
PO5 modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
The engineer and society: Apply reasoning informed by the contextual knowledge to
PO6 assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
Environment and sustainability: Understand the impact of the professional engineering
PO7 solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
Ethics: Apply ethical principles and commit to professional ethics and responsibilities
PO8
and norms of the engineering practice.
Individual and team work: Function effectively as an individual and as a member or
PO9
leader in diverse teams, and in multidisciplinary settings.
Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
PO10
write effective reports and design documentation, make effective presentations, and
give and receive clear instructions.

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Project management and finance: Demonstrate knowledge and understanding of the

PO11 engineering management principles and apply these to one‟s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.
Life-long learning: Recognize the need for and have the preparation and ability to
PO12 engage in independent and lifelong learning in the broadest context of technological
change.

Program Specific Outcomes

Ability to apply concepts in electronics and communication engineering, to design and

PSO1 implement complex systems in the areas related to analog and digital electronics ,
communication, signal processing ,VLSI& ES

Ability to provide discerning solutions based on their expertise in electronics and

PSO2 communication courses in competitive examinations for successful employment, higher
studies and research.

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COURSE OUTCOME

Objective
The student will verify the function of
1.The concepts of Logic gates
2.Concepts of combinational circuits
3.Sequential circuits by learning flip-flops and their applications
Requirements:
➢ Digital IC trainer kits with various gates, flip-flop, built-in clock with variable frequencies, 7-segment display
Spare Parts:
➢ Patch chords, Digital IC‘s-7490, 7493, 74121, 74151, 74138, 7474, 7495, 74117

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SWTICHING THEORY AND

LOGIC DESIGN (R19)
II Year-I Semester
List of Experiments:

1. Verification of truth tables of Logic gates

2. Design of combinational circuit with with minimal SOP expression
3. 3 to 8 Decoder -74138
4. 8 x 1 Multiplexer-74151
5. Design of Full Adder
6. Verification of JK,Master JK and D flip flop
7. Design a four bit ring counter using D Flip – Flops / JK Flip Flop
8. Design a four bit Johnson‘s counter using D Flip-Flops / JK Flip Flops
9. (a) Design Four bit buffer register using D Flip – Flops / JK Flip-Flops
(b) Design four bit shift right register using D Flip-Flops / JK Flip-Flops.
10. Design MOD-8 ripple counter using T flip flop

Add-on Experiments:
1. Design MOD – 8 synchronous counter using T Flip-Flop
2. (a) Draw the circuit diagram of a single bit comparator
(b) Testing of 7 segment Display with common cathode.

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Date:
EXPERIMENT – 1
Aim: Verification of truth tables of Logic gates.
Two input: (i) OR (ii) AND (iii) NOR (iv) NAND (v) Exclusive OR (vi) Exclusive NOR
vii) NOT
Apparatus: Digital Trainer Kit, IC- 7408, 7432, 7404, 7400, 7402, 7486, patch cards
Theory:
Logic gates are the physical devices for implementing the Boolean function, which it performs a
logical operation on more than one input and produces single output .The logic gates are
classified of three types:
1. Basic gates(AND,OR,NOT)
2. Universal gates(NAND,NOR)
3. Special gates(Ex-OR, Ex-NOR)
BASIC GATES:
AND Gate: AND gate performs multiplication operation and the gate gets the output high
when both inputs are high in reaming cases the output will be low. The following truth table will
justifies the statement,
INPUTS OUTPUTS
A B Y=A.B
0 0 0
1 0 0
0 1 0
1 1 1
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Figure.1.Pin Diagram of AND Gate

OR Gate: OR gate performs addition operation and the gate gets the output low when both
inputs are low in reaming cases the output will be high. The following truth table will justifies
the statement,
INPUTS OUTPUTS
A B Y=A+B
0 0 0
1 0 1
0 1 1
1 1 1

Figure.2.Pin Diagram of OR Gate

NOT Gate: It acts as invertor .they will be given only two inputs as shown in the truth table,
INPUTS OUTPUTS
A A′
0 1
1 0
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Figure.3.Pin Diagram of NOT Gate

UNIVERSAL GATES:
NAND Gate: NAND gate performs reverse operation of AND gate and the gate gets the output
low when both inputs are high in reaming cases the output will be low. The following truth table
will justifies the statement,
INPUTS OUTPUTS
A B Y=
0 0 1
1 0 1
0 1 1
1 1 0

Figure.4.Pin Diagram of NAND Gate

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NOR Gate: NAND gate performs reverse operation of AND gate and the gate gets the output
low when both inputs are high in reaming cases the output will be low. The following truth table
will justifies the statement,
INPUTS OUTPUTS
A B Y=A′ + B′
0 0 1
1 0 0
0 1 0
1 1 0

Figure.5.Pin Diagram of NOR Gate

SPECIAL GATES:
EX-OR Gate: The gate output will be high when the inputs are different and the output will be
low when the inputs are same as shown in the truth table
INPUTS OUTPUTS
A B Y=A′B + AB′
0 0 0
1 0 1
0 1 1
1 1 0
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Figure.6.Pin Diagram of Ex-OR Gate

EX-OR Gate: The gate output will be high when the inputs are same and the output will be low
when the inputs are different as shown in the truth table
INPUTS OUTPUTS
A B Y= + AB
0 0 1
1 0 0
0 1 0
1 1 1

Figure.6.Pin Diagram of Ex-NOR Gate

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PROCEDURE:
1. Place the trainer kit gently on the table.
2. Connect the patch cards into the holes of the particular logic gate, for checking the output of
the particular gate, connect the output of the particular logic gate in to the indicator.
3. While checking the output of the particular gate using the indicator we should know the truth
table of the particular gate which we are going to verify.
4. Switch on the power supply
5. At logic inputs based on the truth table on varying of the inputs If the led glows it indicates
as the inputs are high , if not glowing it indicates as low and at the logic indicator id the led
glows it indicates that the output is true if not false
PRECAUTIONS:
1. Digital lab kits and the IC’s should be handled with care.
2. While making connections main voltage should be kept switched off.
RESULT:
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EXPERIMENT – 2
AIM: Design a simple combinational circuit with three variables with minimal SOP expression.
Apparatus: Digital trainer Kit, patch cards
Theory:
SOP: It is the Sum of Product form, which is used for representing the simplified expression .In
K-maps the SOP is considered with the summation symbol (∑)
Consider
Y= A′B + C
The logic diagram of the expression:-

The truth table of the SOP expression is

A B C A′ A′B Y
0 0 0 1 0 0
0 0 1 1 0 1
0 1 0 1 1 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 1 0 0 1
1 1 0 0 0 0
1 1 1 0 0 1

PROCEDURE:
1. Place the Digital trainer kit gentle on the observation table
2. Consider the AND gate ,NOT gate and OR gate on the trainer kit ,based on the SOP
expression
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3. Connect the NOT gate IC with input of A and the output of the NOT gate(
A′) is connected to the input of the AND gate IC and consider B as another input given to
the AND gate IC on the trainer kit
4. The output of the AND gate IC is given as input for the OR gate IC and C is given as
another input for the OR gate IC, the output of the OR gate IC is connected to the
indicator to check the output.
5. Switch on the power supply
6. At logic inputs based on the truth table on varying of the inputs If the led glows it
indicates as the inputs are high , if not glowing it indicates as low and at the logic
indicator id the led glows it indicates that the output is true if not false .
PRECAUTIONS:
1. Digital lab kits and the IC’s should be handled with care.
2. While making connections main voltage should be kept switched off.
RESULT:
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EXPERIMENT – 3
AIM: To Implement and verify of 3 to 8 line decoder.
Apparatus: Digital Trainer kit, IC-74ls138
Theory:
DECODER: in decoder it transfer the data for the multiple outputs based on the combination of
the inputs, which is based on the activation of the enable input

Fig.i.Circut diagram of 3 to 8 decoder

The truth table of the 3 to 8 decoder is shown

EN A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0
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1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0

Pin diagram of 74ls138 is shown below

Figure.1. Pin diagram of 74LS138

PROCEDURE:
1. Connections are made as per pin diagram
2. Verify the truth table
3. Connect Always Vcc, ground and then perform the experiment
PRECAUTIONS:
1. IC should be checked before the experiment.
2. All connection should be tight.
3. Always connect the ground first and then connect Vcc
4. The kit should be off before change the connections.
RESULT:
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EXPERIMENT – 4
AIM To Implement and verify 8 to 1 multiplexer
Apparatus: Digital Trainer kit, IC-74ls151
Theory:
MUTIPLXER: A multiplexer also known as a data selector, is a device that selects between
several analog or digital input signals and forwards the selected input to a single output line. The
selection is directed a separate set of digital inputs known as select lines.

Fig.ii. Circuit diagram of 8 to 1 Multiplexer

EN A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 X
0 X X X 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1 1
1 0 0 1 0 0 0 0 0 0 1 0 1
1 0 1 0 0 0 0 0 0 1 0 0 1
1 0 1 1 0 0 0 0 1 0 0 0 1
1 1 0 0 0 0 0 1 0 0 0 0 1
1 1 0 1 0 0 1 0 0 0 0 0 1
1 1 1 0 0 1 0 0 0 0 0 0 1
1 1 1 1 1 0 0 0 0 0 0 0 1
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Pin diagram of 74LS151 is shown below

PROCEDURE:
4. Connections are made as per pin diagram
5. Verify the truth table
6. Connect Always Vcc, ground and then perform the experiment
PRECAUTIONS:
5. IC should be checked before the experiment.
6. All connection should be tight.
7. Always connect the ground first and then connect Vcc
8. The kit should be off before change the connections.
RESULT:
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EXPERIMENT – 5
AIM: To Implement and verify full adder
Apparatus: Digital trainer kit, IC-7486, 7408, 7432
Theory:
Full adder performs addition operations between 3 inputs.

The truth table of the full adder is shown below:

A B C S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
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PROCEDURE:
1. Place the Digital trainer kit gentle on the observation table
2. Consider the AND gate, NOT gate, Ex-OR and OR gate on the trainer kit, based on the sum
and carry expressions.
3. For the Sum expression connect the inputs A,B to the Ex-OR gate IC ,the output of the Ex-
OR gate(IC1) is connected to another Ex-OR gate (IC2) and third input C is connected to
the IC2 and the output of the second Ex-OR gate is connected to the indicator to check the
output (which is SUM).
4. For the carry expression connect the inputs AB,AC and AC to AND gate IC and the output
of the AB,AC are connected to the OR gate IC1,then the output of the OR gate IC1 is
connected as input to the OR gate IC2 and the BC term input is connected to the OR gate
IC2.The output of the OR gate IC2 is connected to the indicator (for checking the carry).
5. Switch on the power supply
6. At logic inputs based on the truth table on varying of the inputs If the led glows it indicates
as the inputs are high , if not glowing it indicates as low and at the logic indicator id the led
glows it indicates that the output is true if not false .
PRECAUTIONS:
1. Digital lab kits and the IC’s should be handled with care.
2. While making connections main voltage should be kept switched off.
RESULT:
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EXPERIMENT – 6
AIM: To Implement and verify the working of the
(i) J K Edge triggered Flip – Flop (ii) J K Master Slave Flip – Flop (iii)D Flip – Flop

Apparatus: Digital trainer kit, IC-7404, 7476, 7473

Theory:
A flip flop is an electronic circuit with two stable states that can be used to store binary data.
The stored data can be changed by applying varying inputs. Flip-flops and latches are
fundamental building blocks of digital electronics
a.D Flip Flop- The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data
input from the flip flop's latching circuitry. When the clock input is set to true, the D input
condition is only copied to the output Q. This forms the basis of another sequential device
referred to as D Flip Flop.

Fig.Symbol of D Flip Flop

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Fig.Pin Diagram of D Flip

Flop

Pin Number Description

1 Clear 1 Input
2 D1 Input
3 Clock 1 Input
4 Preset 1 Input
5 Q1 Output
6 Complement Q1 Output
7 Ground
8 Complement Q2 Output
9 Q2 Output
10 Preset 2 Input
11 Clock 2 Input
12 D2 Input
13 Clear 2 Input
14 Positive Supply
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Fig. Circuit Diagram of D Flip Flop

Truth Table-
CLK D Q Qbar
0 x 0 0
1 0 0 1
1 1 1 0

b.JK Flip Flop- The JK flip flop work in the same way as the SR flip flop work. The JK flip
flop has 'J' and 'K' flip flop instead of 'S' and 'R'. The only difference between JK flip flop and
SR flip flop is that when both inputs of SR flip flop is set to 1, the circuit produces the invalid
states as outputs, but in case of JK flip flop, there are no invalid states even if both 'J' and 'K' flip
flops are set to 1.

The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry. The
invalid or illegal output condition occurs when both of the inputs are set to 1 and are prevented
by the addition of a clock input circuit. So, the JK flip-flop has four possible input
combinations, i.e., 1, 0, "no change" and "toggle".

Fig.Symbol of JK Flip Flop

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Fig. Circuit Diagram of JK Flip Flop

Truth Table-

CLK J K Q Qbar
0 x x 0 0
1 0 0 0 1(M.S)
1 0 1 0 1
1 1 0 1 0
1 1 1 0 1(toggling)

Fig .Pin Diagram of JK Flip Flop

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Pin Description
Pin Number Description
1 Clock 1 Input
2 Preset 1 Input
3 Clear 1 Input
4 J1 Input
5 Vcc - Positive Power Supply
6 Clock 2 Input
7 Preset 1 Input
8 Clear 2 Input
9 J2 Input
10 Complement Q2 Output
11 Q2 Output
12 K2 Input
13 Ground
14 Complement Q1 Output
15 Q1 Output
16 K1 Input

c.Master Slave JK Flip Flop- Master-slave flip flop is designed using two separate flip flops.
Out of these, one acts as the master and the other as a slave as shown in the figure. The output
of the master J-K flip flop is fed to the input of the slave J-K flip flop. The output of the slave J-
K flip flop is given as a feedback to the input of the master J-K flip flop. The clock pulse [Clk]
is given to the master J-K flip flop and it is sent through a NOT Gate and thus inverted before
passing it to the slave J-K flip flop.

Fig. Symbol of Master Slave JK Flip Flop

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Fig. Circuit diagram of Master Slave JK Flip Flop

Fig. Pin diagram of Master Slave JK Flip Flop

Pin Description
Pin Number Description
1 Clock 1 Input
2 Clear 1 Input
3 K1 Input
4 Vcc - Positive Supply
5 Clock 2 Input
6 Clear 2 Input
7 J2 Input
8 Complement Q2 Output
9 Q2 Output
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10 K2 Input
11 Ground
12 Q1 Output
13 Complement Q1 Output
14 K1 Input

PROCEDURE:
1. Connections are made as per pin diagram
2. Verify the truth table
3. Connect Always Vcc, ground and then perform the experiment

PRECAUTIONS:
1. Digital lab kits and the IC’s should be handled with care.
2. While making connections main voltage should be kept switched off.
RESULT:
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EXPERIMENT – 7
AIM: To Implement and verify a four bit ring counter using D Flip – Flops/JK Flip flop
Apparatus: Digital trainer kit, IC-7474, 7476
Theory:
A ring counter is a special type of application of the Serial IN Serial OUT Shift register. The only
difference between the shift register and the ring counter is that the last flip flop outcome is taken as
the output in the shift register. But in the ring counter, this outcome is passed to the first flip flop as
an input.

Fig.Circut Diagram

Truth table-
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PROCEDURE:
1. Connections are made as per pin diagram
2. Verify the truth table
3. Connect alwaysVcc, ground and then perform the experiment

PRECAUTIONS:
3. Digital lab kits and the IC’s should be handled with care.
4. While making connections main voltage should be kept switched off.
RESULT:
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EXPERIMENT – 8
AIM: To Implement and verify four bit Johnson‘s counter using D Flip-Flops/JK Flip flop
Apparatus: Digital trainer kit, IC-7474, 7476
Theory:
The Johnson counter is similar to the Ring counter. The only difference between the Johnson
counter and the ring counter is that the outcome of the last flip flop is passed to the first flip flop
as an input. But in Johnson counter, the inverted outcome Q' of the last flip flop is passed as an
input. The remaining work of the Johnson counter is the same as a ring counter. The Johnson
counter is also referred to as the Creeping counter.

Fig. Circuit Diagram

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Truth Table-
CLK Q0′ Q3 Q2 Q1 Q0
0 - 0 0 0 0
1 1 1 0 0 0
2 1 1 1 0 0
3 1 1 1 1 0
4 1 1 1 1 1
5 0 0 1 1 1
6 0 0 0 1 1
7 0 0 0 0 1
8 0 0 0 0 0

PROCEDURE:
1. Connections are made as per pin diagram
2. Verify the truth table
3. Connect alwaysVcc, ground and then perform the experiment

PRECAUTIONS:
1. Digital lab kits and the IC’s should be handled with care.
2. While making connections main voltage should be kept switched off.
RESULT:
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EXPERIMENT – 9
AIM: To Implement and verify four bit shift right register using D Flip-Flop
Apparatus: Digital trainer kit, IC-7474
Theory:

Fig. a. Circuit Diagram

The shift register, which allows serial input (one bit after the other through a single data line) and
produces a serial output is known as Serial-In Serial-Out shift register. Since there is only one output,
the data leaves the shift register one bit at a time in a serial pattern, thus the name Serial-In Serial-
Out Shift Register.
Truth Table:
Consider the bits 1001 for shifting the data
CLK Data In Q3 Q2 Q1 Q0
0 - 0 0 0 0
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 0
4 1 1 0 0 1
Stored Data 1 0 0 1
5 0 0 1 0 0
6 0 0 0 1 0
7 0 0 0 0 1
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PROCEDURE:
1. Connections are made as per pin diagram
2. Verify the truth table
3. Connect alwaysVcc, ground and then perform the experiment

PRECAUTIONS:
1. Digital lab kits and the IC’s should be handled with care.
2. While making connections main voltage should be kept switched off.
RESULT:
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EXPERIMENT – 10
AIM: To Implement and verify MOD – 8 ripple counter using T Flip-Flop
Apparatus: Digital trainer kit, IC-7476
Theory:

An Asynchronous counter can have 2n-1 possible counting states ,for example
consider MOD-8 for a 3-bit counter, (0-7 making it ideal for use in Frequency Division
applications. But it is also possible to use the basic asynchronous counter configuration
to construct special counters with counting states less than their maximum output
number.
This is achieved by forcing the counter to reset itself to zero at a pre-determined value
producing a type of asynchronous counter that has truncated sequences. Then an n- bit
counter that counts up to its maximum modulus ( 2 n ) is called a full sequence counter and
a n-bit counter whose modulus is less than the maximum possible is called a
truncated counter.

Fig.a. Circuit diagram using T Flip flop

Clock QC QB QA
1 0 0 0
2 0 0 1
3 0 1 0
4 0 1 1
5 1 0 0
6 1 0 1
7 1 1 0
8 1 1 1
9 Counter Resets its Outputs back to Zero
Fig.b. Truth Table
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PROCEDURE:
1. Connections are made as per pin diagram
2. Verify the truth table
3. Connect alwaysVcc, ground and then perform the experiment

PRECAUTIONS:
1. Digital lab kits and the IC’s should be handled with care.
2. While making connections main voltage should be kept switched off.
RESULT:
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EXPERIMENT – 11
AIM: To Implement and verify MOD – 8 synchronous counter using T Flip-Flop
Apparatus: Digital trainer kit, IC-7476
Theory:

Fig. a. Circuit Diagram

The 3-bit Synchronous binary down counter contains three T flip-flops & one 2-input AND gate.
All these flip-flops are negative edge triggered and the outputs of flip-flops change
affect synchronously. The T inputs of first, second and third flip-flops are
′
1, Q′0 & Q 1respectively.
The output of first T flip-flop toggles for every negative edge of clock signal. The output of
second T flip-flop toggles for every negative edge of clock signal if Q′0 is 1. The output of third
T flip-flop toggles for every negative edge of clock signal if both, Q′0 & Q′ 1are 1.
Truth Table:
Consider the state diagram of the 3 bit synchronous counter
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Present State Next State Required excitations

CLK Q2 Q1 Q0 Q2 Q1 Q0 T2 T1 T0
1 0 0 0 0 0 1 0 0 1
2 0 0 1 0 1 0 0 1 1
3 0 1 0 0 1 1 0 0 1
4 0 1 1 1 0 0 1 1 1
5 1 0 0 1 0 1 0 1 0
6 1 0 1 1 1 0 0 1 1
7 1 1 0 1 1 1 0 0 0
8 1 1 1 0 0 0 1 1 1

PROCEDURE:
1. Connections are made as per pin diagram
2. Verify the truth table
3. Connect alwaysVcc, ground and then perform the experiment

PRECAUTIONS:
1. Digital lab kits and the IC’s should be handled with care.
2. While making connections main voltage should be kept switched off.
RESULT:
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EXPERIMENT – 12
(A)
AIM: To Implement and verify a single bit comparator
Apparatus: Digital trainer kit, IC-7476
Theory:
A comparator used to compare two bits, i.e., two numbers each of single bit is called a single bit
comparator. It consists of two inputs for allowing two single bit numbers and three outputs to
generate less than, equal and greater than comparison outputs.

The figure below shows the block diagram of a single bit magnitude comparator. This comparator
compares the two bits and produces one of the 3 outputs as L (A<B), E (A=B) and G (A>B).

Fig.a. logic symbol of single bit comparator

Fig.b. Truth Table

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Fig.c. Circuit diagram

PROCEDURE:
1. Connections are made as per pin diagram
2. Verify the truth table
3. Connect alwaysVcc, ground and then perform the experiment

PRECAUTIONS:
3. Digital lab kits and the IC’s should be handled with care.
4. While making connections main voltage should be kept switched off.
RESULT:
STLD LAB

(B)
AIM: To Implement and verify a 7 segment Display with common cathode.
Apparatus: Digital trainer kit, IC-7476
Theory:
The seven segment display is the most common display device used in many gadgets, and
electronic appliances like digital meters, digital clocks, microwave oven and electric stove, etc.
These displays consist of seven segments of LEDs and that is assembled into a structure like
numeral 8. Actually seven segment displays contain about 8-segments wherein an extra 8th
segment is used to display dot. This segment is useful while displaying non integer number.
Seven segments are indicated as A-G and the eighth segment is indicated as H. These segments
are arranged in the form of 8 which is shown in the seven segment display circuit diagram.

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Fig.Truth table

PROCEDURE:
1. Connections are made as per pin diagram
2. Verify the truth table
3. Connect alwaysVcc, ground and then perform the experiment

PRECAUTIONS:
1. Digital lab kits and the IC’s should be handled with care.
2. While making connections main voltage should be kept switched off.
RESULT:

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