A Procedure To Verify and Validate An FPGA Level Testing As Per DO-254
A Procedure To Verify and Validate An FPGA Level Testing As Per DO-254
A Procedure To Verify and Validate An FPGA Level Testing As Per DO-254
Abstract:-This paper describes the how advanced verification Configuration Management Process
like constrained random verification or directed tests which Certification Liaison Process
improves the system performance in FPGA level testing or
hardware target level testing which outcomes safety analysis and Integral processes are parallel processes that shall be adopted
performance based scenarios. Basically recent avionics throughout the lifecycle of the project. While traversing in the
industries facing while testing the hardware design using FPGA standard hardware lifecycle processes, the transition criteria
level mode of testing in to different feeded inputs, capturing with shall be met before transiting to next process in the sequence.
different techniques, which will improves the system verification Means that, before start of next process the previous process’s
on random based approach methods. Finally this paper tells
output must be available as an input. So transition criteria
about to improve the hardware design data (HDD) needs to
trace the hardware requirement document (HRD) accurately shall define the minimum data/outcome of any process to start
using the randomization methods as carried out by constrained next process [2].
random verification.
Planning Development Process
Keywords: DO-254, FPGA, directed tests, verification PLANNING REQUIREMENTS DESIGN
IMPLEMENTATION
/INTEGRATION
Integral Processes
I. INTRODUCTION
Detailed
Conceptual
Hardware Planning Requirement Design Implementation
V
Design Process
alidation and Verification Process conducts the hardware Process Capture Process
[High-Level]
Process
[Low-Level]
Process
www.rsisinternational.org Page 48
International Journal of Research and Innovation in Applied Science (IJRIAS) | Volume III, Issue VI, June 2018|ISSN 2454-6194
Hardware Design Processes Planned Activities Identification of evidence reports to be produced out
and Reviews
of verification and validation independently
Define Transition Criteria
among processes Identification of analysis/test tools and equipment to
Define Development & be used to meet verification and validation process
Testing Environment and objectives.
assisting tools
Define Means of Compliances Describes the means of independence to ensure
of hardware design assurance verification purpose for those objectives requiring
objectives for certification independence.
authority
Define problem reporting and
Identification of organizational responsibilities for
tracking resolution implementing independent verification process
mechanisms
Define/Document system's II. DETAILED DESIGN PROCESS
allocated and derived
requirements for hardware The Detailed Design Process produces detailed design data
item
Requirement
Define/Document design using the hardware item requirements and conceptual design
Capture Process data as the basis for the detailed design such as HDL/RTL.
constraints
Traceability to be maintained Hardware Design Standard shall be followed during the
across the different levels of Detailed Design phase of development lifecycle [4].
requirements
Design Hardware items
architecture
A. Detail Design Process Objectives
Define functional blocks and
Design
Conceptual Design
its interfaces etc.,
Detailed design is developed from the hardware item
Process requirements and conceptual design data
Process Define Electrical interface
characteristics between design Trace Data: Derived requirements are fed back to the
blocks conceptual design process or other appropriate
Design HDL code from
hardware item requirements processes.
Detailed Design and conceptual design data Trace Data: Requirement omissions or errors are
Process Develop test methods and provided to the appropriate processes for resolution.
interface data for verification
of design B. Detail Design Process Inputs and Outputs
Perform simulation and
Implementation synthesis Fig. 2. Shows the inputs and outputs of detail design process
Process Capture design constraints
Perform target timing analysis
Generate compliances with INPUTS OUTPUTS
respect to design requirements
and Design assurance level. Hardware Design
Description HDL /RTL
Generate design deviation
report (if any) and raise & Hardware Block
Design
track the problem till it gets Diagram
Detailed Constraints
www.rsisinternational.org Page 49
International Journal of Research and Innovation in Applied Science (IJRIAS) | Volume III, Issue VI, June 2018|ISSN 2454-6194
Requirement omissions and errors discovered during Validation and Verification Process ensures that the test cases,
the detailed design process should be provided to the methods, procedures, pass/fail criteria and results/coverage
appropriate process for resolution are reviewed to determine whether the developed test cases,
methods, procedures, pass/fail criteria satisfy the objectives of
III. TESTING PROCESS RTCA/DO-254.
The Mentor Graphics Questa Sim shall be used for following Verification of the implementation is the verification (e.g.
testing purpose and same is represented in Fig. 3. post layout simulations) of the detailed design after place and
route and of the device itself.
RTL Behavioral Simulation
Post Synthesis Simulation B. Reviews and Analysis
Post Place & Route Simulation The entry criteria to perform the review of test cases,
methods, procedures, pass/fail criteria and results/coverage
INPUTS OUTPUTS are release of initial version of those data items and other
Questa Tool supporting hardware verification data will be under
Design VHDL Verification
Code & Test RTL Behavioural Results/Coverage
configuration control as appropriate. Designers will perform
Simulation
Bench Reports the review of these test cases, methods, procedures & pass/fail
criteria and provide the feedback to the testing team.
Questa Tool
www.rsisinternational.org Page 50
International Journal of Research and Innovation in Applied Science (IJRIAS) | Volume III, Issue VI, June 2018|ISSN 2454-6194
www.rsisinternational.org Page 51
International Journal of Research and Innovation in Applied Science (IJRIAS) | Volume III, Issue VI, June 2018|ISSN 2454-6194
variable result :integer; Hardware design data includes plans, standards, design,
variable tmp_real:real; procedures, methods and results/analysis produced in project
begin lifecycle. Hardware lifecycle data should follow some
assert(lower_value<(2**busWidth)) characteristics as listed below:
report"RANDOM_NUM_GEN():lower_value RANGE is
exceeded" Unambiguous
severity failure; Complete
assert(upper_value<(2**busWidth)) Verifiable
report"RANDOM_NUM_GEN():upper_value RANGE is Consistent
exceeded" Modifiable
severity failure; Traceable
uniform (seed1,seed2,tmp_real); VII. RESULTS
result:=integer( trunc ((tmp_real*real(upper_value-
lower_value))+real(lower_value))); A. Trace Data Objective Evidence of Compliance
return result;
Traceability connects between two or more elements in a
project such as functions, requirements, concept, design,
end RANDOM_NUM_GEN;
verification data and test results shall be prepared across all
traceable data. The outputs of all traceability activities are the
end func_pkg;
traceability reports showing the correlation between the
project elements. Traceability reports are reviewed for
2) Check the syntax of the code.(if there are correctness internally within organizations, and audited by
modifications to the range) certification authorities.
3) To use the given code in a test bench
Tracing hardware lifecycle data right from requirements till
EXAMPLE: the test results shall be carried out using COTS tools
(ReqTracer). Hierarchy of the traceability for different
Inside the architecture block (after the begin statement) a artifacts is shown in Fig. 4.
process is added. Say A,B are input buses of std_logic_vector
System
(7 downto 0) to operate a random number for each buses ,call Requirements
the function RANDOM_NUM_GEN() and then call
conv_std_logic_vector() to convert it to bit vector stream. Hardware
That is: Requirements
www.rsisinternational.org Page 52
International Journal of Research and Innovation in Applied Science (IJRIAS) | Volume III, Issue VI, June 2018|ISSN 2454-6194
During the implementation phase, the actual system is [4]. T. J. Foster D. L. Lastor P. Singh "First silicon functional
validation and debug of multicore microprocessors" IEEE Trans.
implemented. In the case of programmable logic, the design is
Very Large Scale Integr. (VLSI) Syst. vol. 15 no. 5 pp. 495-504
synthesized, place-and-route completed, and Bitstream is May 2007.
generated. Errors or omissions detected in the earlier steps is [5]. J. Rose J. Luu C. W. Yu O. Densmore J. Goeders A. Somverville
fed back to the requirements document. K. B. Kent P. Jamieson J. Anderson "The VTR project:
Architecture and CAD for FPGAs from Verilog to routing" Proc.
ACM/SIGDA Int. Symp. Field-Programmable Gate Arrays pp. 77-
REFERENCES 86 2012.
[6]. S. Tasiran K. Keutzer "Coverage metrics for functional validation
[1]. X. Y. Chen W. J. Xu X. Yang Y. W. Xia "SystemVerilog
of hardware designs" IEEE Design Test Comput. vol. 18 no. 4 pp.
assertions and its application" China Integrated Circult vol. 16 no.
36-45 Jul./Aug. 2001.
19 pp. 19-24 2007.
[7]. M. Karimibiuki K. Balston A. J. Hu A. Ivanov "Post-silicon code
[2]. Y. W. Xia Verilog Digital System Design Tutorial Beijing:Press
coverage evaluation with reduced area overhead for functional
Of Beihang University 2003.
verification of SoC" Proc. IEEE Int. High Level Design Validation
[3]. X. Jin W. Y. Ding C. Yan "Verification and testing of IP core with
Test Workshop pp. 92-97 2011.
a RISC architecture inside" Semiconductor Technology vol. 28 no.
11 pp. 32-35 2003.
www.rsisinternational.org Page 53