CENG 5133: Computer Architecture Design

Introduction
 Circuits:
 Combinational Circuit
 Sequential Circuit

 Sequential Machine (Circuit)

 Mealy Machine
Sequential Circuits  Moore Machine

CENG 5133

[Lecture slides are partially adapted from Fundamentals of Logic Design,

Enhanced 7th Edition, Roth & Kinney, 2021, Cengage Learning]
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General Models for Sequential Circuits General Model for Mealy Circuits
 General Form:
 A sequential circuit can be divided conveniently into two parts
- the flip-flops (which serve as memory) and combinational
logic which realizes the input and output functions.
 The combinational logic may be implemented with gates, with
a ROM, or with a PLA.

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 The combinational circuit realizes the n output functions and the k  Determining Minimum Clock Period:
next-state functions, which serve as inputs to the D flip-flops:  The minimum clock period is:

assuming X inputs are stable after tc+tsu.

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General Models for Moore Circuits

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Main Steps in Sequential Machine Design 1. Design of a Sequence Detector

1. State Graph  To illustrate the design of a clocked Mealy sequential
 Draw partial graph that generates ‘1’ output circuit, we will design a sequence detector.
 Complete the graph  The circuit is of the form:
2. State Table
3. State Reduction if needed
4. State Assignments
5. Transition Table
6. Excitation Table
7. Derive Equations for Circuit Outputs and Next States (Flip-
flop inputs) using K-Maps

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 Design the sequence detector so that any input  First, we will draw the state graph based on problem
sequence ending in 101 will produce an output Z=1. description
 The circuit does not reset when a 1 output occurs. A
typical input sequence and the corresponding output  Initially, we do not know how many flip-flops will be
sequence are: required.
 So we will designate the circuit states as S0, S1, etc.
 We will start with a reset state (initial state) designated as
X= 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0
S 0.
Z= 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 (14-1)
(time: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

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 If X=0, the circuit stays in S0 because the input sequence  When in state S1, if X=0, the circuit must change to a new
does not start with a 0. state (S2) to remember that the first two inputs of the
 If X=1, the circuit must go to a new state (S1) to desired sequence (101) have been received.
“remember” that the first input in the desired sequence
has been received.

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 If X=1 in state S2, the desired input sequence (101) is  If X=1 in state S1, we can stay in S1
complete and the output should be 1.  The sequence is simply restarted
 Since the last 1 in a sequence can also be the first 1 in a  If X=0 in state S2, reset the circuit to S0
new sequence, we should return to S1.  Two 0’s in a row are received and 00 is not part of ‘101’

 Where to go from S2?

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 We can then convert our state graph to a state table:  Now we convert our state table into a transition table:

 How many flip-flops are needed for this design?

 Since there are 3 states, we only need 2 flip-flops for the circuit
(2 memory bits).
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 From the transition table, we can plot  Now we can draw the circuit corresponding to the
 The next-state maps for the flip-flops and equations:
 The map for the output function Z

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Moore Machine Example

 The procedure for a Moore machine is similar to the one  The output is written with the state.
used for a Mealy machine.  S0  initial state
 S1  ‘1’
 S2  ’10’
 Rework the previous example as a Moore machine:
 The circuit should produce an output of 1 only if an input sequence
ending in 101 has occurred.

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 When the machine is in S2 and input is 1, the output must  Completed graph is below:
become 1; therefore, it cannot go S1 and we need a new  The sequence 100 resets the circuit to S0.
state S3 with a 1 output:  A sequence 1010 takes the circuit back to S2 because another 1
input should cause Z to become 1 again.

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More Complex Design Problems

 State Table from State Graph:  The output Z should be 1 if the input sequence ends in
either 010 or 1001, and Z should be 0 otherwise.
Any difference
between Mealy  Example Sequence:
and Moore ?

 Transition Table from State Table:

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Mealy Example
 We will start construction of the state graph by working  First Sequence: “010”
with the two sequences which lead to a 1 output.
 Then, we will later add arrows and states as required to
make sure that the output is correct for other cases.

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 Next, we construct the part of the graph corresponding to  Now we fill in the missing arcs
the sequence 1001, starting from the reset state S0.  With each arc, we first ask if we can go back to one of the
previous states or do we have to create a new state?

state sequence ends in state sequence ends in

S0 reset S0 reset
S1 0 (but not 10) S1 0 (but not 10)
S2 01 S2 01
S3 10 S3 10
S4 1 (but not 01) S4 1 (but not 01)
S5 100 S5 100
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Moore Example
 Design a Moore sequential circuit with one input X and
one output Z.
 The output Z is to be 1 if the total number of 1’s received
is odd and at least two consecutive 0’s have been
received.

 A typical input and output sequence is:

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state input sequences

state sequence received S0 reset or even 1's
S0 reset or even 1's S1 odd 1's
S1 odd 1's S2 even 1's and ends in 0
S3 even 1's and 00 has occurred
S2 even 1's and ends in 0 S4 odd 1's and 00 has occurred
S3 even 1's and 00 has occurred S5 odd 1's and ends in 0
S4 00 has occurred and odd 1's

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3. Guideless for Construction of State Graphs

 No specific procedure for every problem, but the 4. Another way to get started is to determine what
following guidelines are helpful: sequences or groups of sequences must be
1. First, construct some sample input and output remembered by the circuit and set up states accordingly.
sequences to make sure that you understand the 5. Each time you add an arrow to the state graph,
problem statement. determine whether it can go to one of the previously
2. Determine under what conditions, if any, the circuit defined states or whether a new state must be added.
should reset to its initial state. 6. Check your graph to make sure there is one and only
3. If only one or two sequences lead to a nonzero one path leaving each state for each combination of
output, a good way to start is to construct a partial values of the input variables.
state graph for those sequences. 7. When your graph is complete, test it by applying the
input sequences formulated in part 1 and making sure
the output sequences are correct.

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Example 1 (Mealy Machine)

 A sequential circuit has one input (X) and one output (Z). 2. Determine under what conditions, if any, the circuit
The circuit examines groups of four consecutive inputs should reset to its initial state.
 Z = 1 if the input sequence 0101 or 1001 occurs
 The circuit resets after every four inputs.  Since the circuit examines groups of four consecutive
inputs and resets after each group of four, the circuit
should reset to S0 after every fourth input is received.

1. First, construct some sample input and output sequences.

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4. Another way to get started is to determine what 6. Check your graph to make sure there is one and only
sequences or groups of sequences must be one path leaving each state for each combination of
remembered by the circuit and set up states accordingly. values of the input variables.

state sequence received

S0 reset
state sequence received S1 0
S0 reset S2 1
S3 01 or 10
S1 0 S4 010 or 100
S2 1 S5 2 inputs received, no 1 output is possible
S6 3 inputs received, no 1 output is possible
S3 01 or 10
S4 010 or 100
Complete State Graph
Partial State Graph
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Example 2 (Mealy Machine)

 A sequential circuit with one input (X) and two outputs(Z1
and Z2).
 Z1 = 1 occurs every time the input sequence 100 is
completed, provided that the sequence 010 has never
occurred.
 Z2 = 1 occurs every time the input sequence 010 is
completed.
 Note that once a Z2 = 1 output has occurred, Z1 = 1 can never occur
but not vice versa.
 A typical sequence of inputs and outputs is:

Partial Graphs for Example 2

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 Keeping track of what is remembered by each state will

help us make the correct state graph.

 State Descriptions for Example 2:

State Description
S0 No progress on 100 No progress on 010
S1 Progress of 1 on 100 No progress on 010
S2 Progress of 10 on 100 Progress of 0 on 010 010 has never occurred
S3 No progress on 100 Progress of 0 on 010
S4 Progress of 1 on 100 Progress of 01 on 010
S5 Progress of 0 on 010
S6 Progress of 01 on 010 010 has occurred
S7 No progress on 010
State Graphs for Example 2
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Finding FF inputs (Sect.12.6 Summary)

State Table for Example 2.  Given Q (present state) and Q+ (next state), find the required
Present Next State Output (Z1Z2) inputs for FFs.
State X=0 X=1 X =0 X=1  D FF: Input is the same as next state
S0 S3 S1 00 00  T FF: Input is 1 whenever state change is required
S1 S2 S1 00 00  S-R FF:
S2 S3 S4 10 00  S=1 whenever FF must be set to 1; R=1 whenever FF must be reset to 0;
S3 S3 S4 00 00
 S=‘-’ if state is 1 and must remain 1; R=‘-’ if state is 0 and must remain 0.
S4 S5 S1 01 00
S5 S5 S6 00 00  J-K FF:
S6 S5 S7 01 00  Same as SR except when one input is one and other input is ‘-’
S7 S5 S7 00 00  Because S=R=1 is not allowed, but J=K=1 causes a state change

 Before applying these rules, copy any ‘-’ from next state maps
into FF input maps

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15.1 – Elimination of Redundant States

 You can use following table to find FF input values  What if we have extra states in the state graph/table?
 Complete the table then eliminate the redundant states

 Advantage of reducing the number of states?

 Number of flip-flops
 Amount of logic required
 At the flip-flop inputs
 More “don’t care”s, larger groups in K-map

 How to read this table:

 For D FF: if Q=0 and desired Q+=0, input must be 0 (D=0)
 For J-K FF: if Q=0 and desired Q+=1, J=1 and K=X
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 Rework a previous example  The first solution with minimum number of states:

state sequence received

 Circuit has one input (X) and one output (Z). It examines S0 reset
S1 0
groups of four consecutive inputs S2 1
S3 01 or 10
 Z = 1 if the input sequence 0101 or 1001 occurs S4 010 or 100
S5 2 inputs received,
 The circuit resets after every four inputs. no 1 output is possible
S6 3 inputs received,
no 1 output is possible

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 Now, lets set up enough states to “remember” first three bits  State table for sequence detector:
of every possible input sequence.
 After fourth input, machine goes to reset state
 States:
State Input Sequence
A Reset
B 0
C 1
D 00
… …
G 11
H 000
… …
P 111
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 States H, I, K, M, N, P ?  State table after replacing and deleting states

 Next states and the outputs are the same
 These states are equivalent
 H≡I≡ K≡M≡N≡P
 Replace I, K, N, M, P with H and delete corresponding rows

 Similarly, states J and L are equivalent (J ≡ L)

 Replace L with J and delete row L

 Resulting table is shown

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 After making these changes, in the new table  Reduced State Table:
 States D and G are identical (D ≡ G)
 States E and F are identical (E ≡ F)
 So, eliminate F and G

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 Reduced State Graph  The technique used in the example is called row matching
 Row matching is not sufficient to find all equivalent states
 Except in the special case where the circuit resets to the starting state
after receiving a fixed number of inputs

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15.2 – Equivalent States

 Two states are equivalent if there is no way of telling them apart  Two sequential circuits N1& N2
through observation of the circuit inputs and outputs  Feed an input sequence X into both circuits and observe the output
sequences Z1 & Z2
 Then, reset the circuits to states p & q and feed another input sequence
 Consider two sequential circuits (not necessarily different) X; and observe Z1 & Z2 again
 N1 starting in state p and  Do this for every possible input sequence X (i.e., 1-bit input sequences
 N2 starting in state q (0, 1), 2-bit sequences (00, 01, 10, 11), and so on)
 Equivalence of two states?
 If Z1 & Z2 are equal for every X, two states are equivalent
 If any of Z1 & Z2 are different, two states are not equivalent
 This is not practical!

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 Definition 15.1:  Theorem: Two states p and q of a sequential circuit are equivalent
 Let N1 and N2 be sequential circuits (not necessarily different). Let X iff for every single input X, the outputs are the same and the next
represent a sequence of inputs of arbitrary length.Then, state p in N1 is states are equivalent, that is,
equivalent to state q in N2 iff λ1(p, X) = λ 2(q, X) for every possible input
sequence X.
 λ(p, X) is the output given the present state p and input X
 λ(p, X) is the output given the present state p and input X
 δ(p, X) is the next state given the present state p and input X

 Note that the next states do not have to be equal, just equivalent.

 This is practical!

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15.3 – Determination of State Equivalence

 The implication table method of determining state 3. Go through the table square-by-square. If square i-j contains
equivalence can be summarized as follows: the implied pair m-n, and square m-n contains an X, then i j,
and an X should be placed in square i-j.
1. Construct a chart which contains a square for each pair of
states. 4. If any X’s were added in step 3, repeat step 3 until no more
X’s are added.
2. Compare each pair of rows in the state table.
 If the outputs associated with states i and j are different, place an X 5. For each square i-j which does not contain an X, i ≡ j.
in square i-j to indicate that i j.
 If the outputs are the same, place the implied pairs in square i-j.
 If the next states of i and j are m and n for some input x, then m-n is an
implied pair.
 If the outputs and next states are the same (or if i-j only implies
itself), place a check (√) in square i-j to indicate that i ≡ j.

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Example Implication chart

 Eliminate the redundant states in the following state table

 Can State a and State b equivalent?

 a ≡ b iff d ≡ f and c ≡ h
 d-f and c-h are called implied pairs
 How about State a and State c?
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Implication chart after first pass Implication chart after second pass

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15.8 – Guidelines for State Assignments

 After replacing d with a and e with c, eliminate rows d & e.  The cost of logic strongly depends on the way state
assignments are made.
 Reduced Table with six rows:  Making state assignments is a challenge in design
 Trail-and-error method is useful for a machine with small
number of states
 3 states  2 FF  4 possibilities for S1, 3 for S2, and 2 for S3
 4×3×2 =24 possibilities (some assignments are equivalent)
 This is not practical for machines with large number of states
 Guideline method produces good solutions for some
problems, but sometimes it is not satisfactory

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 The following guidelines are useful in making assignments:  How to use these guidelines,
 This will place 1’s together (or 0’s) on the next-state maps:  First, write down the sets of states which should be adjacent
1. States which have the same next state for a given input should be given  Then, using K-maps try to satisfy as many adjacencies as possible
adjacent assignments  A fair amount of trial-and-error may be required
2. States which are the next states of the same state should be given
adjacent assignments
3. States which have the same output for a given input should be given
adjacent assignments
 Place 1’s together on the output maps

 Assignments for two states are said to be adjacent if they

differ in only one variable
 Ex: 010 and 011 are adjacent; 010 and 001 are not adjacent

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Example
 When filling the map,  Guideline 1:
 Assign the starting state to ‘0’ square on the map  S0, S2, S4, S6 be adjacent
 Simplifies the initialization of the circuit  S1 is next state when X=0
 Adjacency conditions from Guide 1 and 2 that are required 2 or 3 times  S3 and S5
should be satisfied first S5 is next state when X=0
 When 3 or 4 states are required to be adjacent, these states should be  S 0 , S1 , S 3 , S5
placed within a group of four adjacent squares  S2 is next state when X=1
 If output table is considered, then Guide 3 should be considered  S4 and S6
 Guide 3 has less priority than Guide 1 and 2 if there is single output S6 is next state when X=1
 Guideline 2: 
 If there are 2 or more outputs, Guide 3 may have higher priority
 S1, S2 (next states of S0)
 *Guideline 3 is not considered in this
 S2, S3 (next states of S1) example
 S 1 , S4
 S2, S5 (two times: S3 & S5)
 S1, S6 (two times: S4 & S6)
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15.9 – Using One-Hot State Assignment

 Guide 1: (S0, S2, S4, S6), (S3, S5), (S0, S1, S3, S5), (S4, S6)  When designing with CLPDs or FPGAs, each logic cell
 Guide 2: (S1, S2), (S2, S3), (S1, S4), 2×(S2, S5), 2×(S1, S6) contains one or more FFs
 These FFs are there whether we use them or not
 Instead of number of FF, try to reduce number of logic cells used and the
interconnections between them
 Cost of realizing D FF input
equations:  Because the propagation delay typically depends on number of cell used
• 6 gates, 13 inputs  One-hot state assignment may help to accomplish this
 If straight binary assignment
 The one-hot assignment uses one flip-flop for each state
were used, cost:  So, a state machine with N states requires N flip-flops
• 10 gates, 39 inputs  Exactly one of the flip-flops is set to 1 in each state

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Example
 Partial graph is given  How to write next-state equations?
 4 states (S0, S1, S2, S3)  There are 4 arcs leading into S3
 4 FFs (Q0, Q1, Q2, Q3)  So, 4 conditions under which next state is S3
 State Assignment  PS=S0 and X1=1
 S0 = 1000 (Q0Q1Q2Q3)  PS=S1 and X2=1
 S1 = 0100  PS=S2 and X3=1
 S2 = 0010  PS=S3 and X4=1
 S3 = 0001
 Next state of Q3 =1 under these conditions; otherwise, Q3=0
  Q3+= X1(Q0Q1’Q2’Q3’) + X2(Q0’Q1Q2’Q3’) + X3(Q0’Q1’Q2Q3’) +
X4(Q0’Q1’Q2’Q3)
 Next-state and output equations can be written by  Q0 = 1 implies that Q1=Q2=Q3= 0
inspecting the state graph   Q3+= X1Q0 + X2Q1 + X3Q2+ X4Q3
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 How to write output equations?  What if the FFs used do not have a preset input?
 Z1=1 when PS=S0 and X1=1 & when PS=S2 and X3=1  That is, Q0 can not be set to 1 for initial state
  Z1 = X1Q0 + X3Q2  Replace Q0 with Q0’ throughout

 Similarly, Z2 = X2Q1 + X4Q3  State assignments for the previous example:

 S0=0000, S1=0100, S2=0010, S3=0001

 Modified Equations:
 In general, each term in next-state equation contains exactly  Q3+= X1Q0’ + X2Q1 + X3Q2+ X4Q3
one state variable
 Z1 = X1Q0’ + X3Q2
 Similarly, each term in output equation contains exactly one
 Z2 = X2Q1 + X4Q3
state variable
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Example 2
 A sequential circuit that controls a binary multiplier  Next state equation for Q0+:
 3 inputs: St, M, K  2 arcs leading to S0  2 terms in the equation
 4 outputs: Load, Ad, Sh, Done  Q0+ = Q0St′ + Q3

 Starting in S0
 Next state equation for Q1+:
 3 arcs leading to S0  3 terms
 Q1+ = Q0St + Q1K′M′ + Q2K′
 How many FFs?
 4 states  4 FFs
 S0=1000  Output equation for Sh:
 S1=0100  Sh appears in 4 places
 S2=0010  Sh=1 in S1 if K’M’=1 or KM’=1; also in S2 if K’=1 or K=1
 S3=0001   Sh = Q1(K′M′ + KM′) + Q2(K′ + K) = Q1M′ + Q2

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5. Alphanumeric State Graph Notation

 When designing with CPLDs or FPGAs, try both an  When a state sequential circuit has several inputs, it is
assignment with minimum number of state variables and a often convenient to label the state graph arcs with
one-hot state assignment alphanumeric input variable names instead of 0’s and 1’s.
 If area is the concern, choose one with minimum number of logic cells
 If speed is the concern, choose the fastest one
State Graphs with Variable Names on Arc Labels:

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Property Specified State Graphs

 State Table:  In general, a completely specified state graph has the
following properties:
1. When we OR together all input labels on arcs emanating from a
PS NS Output state, the result reduces to 1.
FR=00 01 10 11 Z1Z2Z3 2. When we AND together any pair of input labels on arcs
S0 S0 S2 S1 S1 1 0 0 emanating from a state, the result is 0.
S1 S1 S0 S2 S2 0 1 0
S2 S2 S1 S0 S0 0 0 1

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 XiXj / ZpZq means if inputs Xi and Xj are 1 (we don’t care

what the other input values are), the outputs Zp and Zq
are 1 (and the other outputs are 0).

 Example: For a circuit with four inputs (X1, X2, X3, and X4)
and four outputs (Z1, Z2, Z3, and Z4),
X1X4′ / Z2Z3 ------> 1--0 / 0110.

 This type of notation is very useful for large sequential

circuits with many inputs and outputs.
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