9.

LOW-LEVEL DESIGN ENTRY
 The purpose of design entry is to describe a microelectronic system to a set of electronic-
design automation ( EDA ) tools.**

 Electronic systems used to be, and many still are, constructed from off-the-shelf
components, such as TTL ICs.( Transistor-transistor logic) **

 Design entry for these systems now usually consists of drawing a picture, a schematic**.
The schematic shows how all the components are connected together, the connectivity of
an ASIC. This type of design-entry process is called schematic entry, or schematic
capture . A circuit schematic describes an ASIC in the same way an architect’s plan
describes a building.

 The circuit schematic is a picture, an easy format for us to understand and use, but
computers need to work with an ASCII or binary version of the schematic that we call
a netlist . The output of a schematic-entry tool is thus a netlist file that contains a
description of all the components in a design and their interconnections.

 Not all the design information may be conveyed in a circuit schematic or netlist, because
not all of the functions of an ASIC are described by the connectivity information. For
example, suppose we use a programmable ASIC for some random logic functions. Part of
the ASIC might be designed using a text language. In this case design entry also includes
writing the code. What if an ASIC in our system contains a programmable memory
(PROM)? Is the PROM microcode, the '1's and '0's, part of design entry? The operation
of our system is certainly dependent on the correct programming of the PROM. So
perhaps the PROM code ought to be considered part of design entry. On the other hand
nobody would consider the operating-system code that is loaded into a RAM on an ASIC
to be a part of design entry. Obviously, then, there are several different forms of design
entry. In each case it is important to make sure that you have completely specified the
system—not only so that it can be correctly constructed, but so that someone else can
understand how the system is put together. Design entry is thus an important part
of documentation .

 Until recently most ASIC design entry used schematic entry. As ASICs have become
more complex, other design-entry methods are becoming common. Alternative design-
entry methods can use graphical methods, such as a schematic, or text files, such as a
programming language. Using a hardware description language ( HDL ) for design entry
allows us to generate netlists directly using logic synthesis . We will concentrate on low-
level design-entry methods together with their advantages and disadvantages in this
chapter.

** Explanations of terms used in notes **

1. What are EDA tools and how do they work?

  The tools work together in a design flow that chip designers use to design and
analyze entire semiconductor chips. Since a modern semiconductor chip can have
billions of components, EDA tools are essential for their design.

 Electronic Design Automation, or EDA, is a market segment consisting of

software, hardware, and services with the collective goal of assisting in the
definition, planning, design, implementation, verification, and subsequent
manufacturing of semiconductor devices, or chips.

 Some of the EDA Tools in VLSI are:

1) Synopsys

2) Cadence

3) Siemens EDA

4) ANSYS Inc.

5) Keysight Technologies Inc

6) Agnisys Inc.

7) Aldec Inc.

8) Lauterbach GmbH

9) Zuken Ltd.

10) Alliance

11) Electric

2. What is this TTL?

 Transistor-Transistor Logic or TTL is a family of logic circuits used in electronics

invented in the 1960s.

 Before jumping on Transistor To Transistor logic, let’s briefly recapitulate what is a

transistor. In order to understand how transistors work, think of them as electronic
switches, which can turn the current on and off. The most common transistor is the
Bipolar Junction Transistor, which consists of three main parts: Base, Collector, Emitter.
This simple structure allows current to flow from the collector to emitter if it is possible
at first for 0.7V current to flow from Base to the emitter. Transistors most commonly are
integrated into circuits, which allows them to cooperate
  TTL is a digital logic design where transistors act on DC pulses. Some TTL logic gates
are fabricated onto an integrated circuit (IC). TTL ICs commonly bear 4 digit numbers
beginning with 74 or 54. Like 7490 counter.

 TTL family is made with bipolar transistor technology and tending to disappear because
of their high energy consumption (compared to CMOS circuits). TTL technology is
standardized to a supply voltage of 5 V. A TTL signal is defined as a low logic level
between 0 and 1.4 V, and as a high logic level between 2.4 V and 5 V.

 TTL is characterized by high switching speed, and some immunity to noise. Main
drawback is the fact that circuits using TTL tend to draw more current than equivalent
circuits using metal oxide semiconductor (MOS) logic.

 TTL stands for Transistor-transistor Logic. It is a logic family made up of bipolar

junction transistors (BJTs). Here, both the functions (logic and amplifying) are performed
by the transistors; therefore, it is named as the Transistor-Transistor Logic. An ideal
example of TTL logic IC would be Logic Gate ICs like the 7400 NAND or the 7402
NOR Gate.

TTL ICs

 TTL is the short form of transistor-transistor logic. TTL logic uses multiple transistors
having multiple emitters and multiple inputs.

 TTL logic gates are made up of the Bipolar junction transistors and resistors. There
are many variants of TTL developed for various particular purposes like the radiation-
hardened TTL packages for space applications and Low power Schottky diodes that can
provide an excellent combination of speed and lesser power consumption.

Advantages

 This family of components combines good switching speed with low transfer time.
 The immunity is good provided that the power supply is decoupled from each circuit by a
filtering capacitor.
 The air intakes, with no fixed state, are in logic state “1” by default (they only discharge a
significant current if they are set to zero and they are almost equivalent to resistances
towards Vcc = 5 V ) .
Disadvantages

 The TTL power supply must be accurate: +5 V ± 5%, compared to CMOS circuits which
have a much larger supply voltage range (+3 to +18 V ). In case of non-compliance with
this requirement, there is a risk, at best, erratic operation of the circuit, and at worst, a
partial or complete destruction of the circuit.
 The bipolar technique is great consumer of electric current; TTL memories are certainly
fast, but can hardly be rescued for a long time in case of power failure.
 The signals transmitted by the TTL circuits can not be transmitted without additional
transmission circuits over long distances without loss: maximum length approximately 15
m.

3. what is schematic?

 (of a diagram or other representation) symbolic and simplified.

 (in technical contexts) a schematic diagram, in particular of an electric or electronic
circuit.

9.1  Schematic Entry(Graphical rep.)

 Schematic entry is the most common method of design entry for ASICs and is likely to be
useful in one form or another for some time.
 HDLs are replacing conventional gate-level schematic entry, but new graphical tools based
on schematic entry are now being used to create large amounts of HDL code.(hardware
description languages).
 Circuit schematics are drawn on schematic sheets . Standard schematic sheet sizes
( Table 9.1 ) are ANSI A–E (more common in the United States) and ISO A4–A0 (more
common in Europe). Usually a frame or border is drawn around the schematic containing
boxes that list the name and number of the schematic page, the designer, the date of the
drawing, and a list of any modifications or changes.

TABLE 9.1  ANSI (American National Standards Institute) and ISO (International

Standards Organization) schematic sheet sizes.
ANSI sheet Size (inches) ISO sheet Size (cm)
A 8.5 ¥ 11 A5 21.0 ¥ 14.8
B 11 ¥ 17 A4 29.7 ¥ 21.0
C 17 ¥ 22 A3 42.0 ¥ 29.7
D 22 ¥ 34 A2 59.4 ¥ 42.0
E 34 ¥ 44 A1 84.0 ¥ 59.4
    A0 118.9 ¥ 84.0
 Figure 9.1 shows the “ spades” and “ shovels,” the recognized symbols for AND, NAND,
OR, and NOR gates. One of the problems with these recommendations is that the corner
points of the shapes do not always lie on a grid point (using a reasonable grid size).

 FIGURE 9.1  IEEE-recommended dimensions and their construction for logic-gate symbols.

(a) NAND gate (b) exclusive-OR gate (an OR gate is a subset).
 Figure 9.2 shows some pictorial definitions of objects you can use in a simple schematic.
We shall discuss the different types of objects that might appear in an ASIC schematic first
and then discuss the different types of connections.

FIGURE 9.2  Terms used in circuit schematics.

 Schematic-entry tools for ASIC design are similar to those for printed-circuit board (PCB)
design. The basic object on a PCB schematic is a component or device —a TTL IC or
resistor, for example.

 There may be several hundred components on a typical PCB. If we think of a logic gate
on an ASIC as being equivalent to a component on a PCB, then a large ASIC contains
hundreds of thousands of components. We can normally draw every component on a few
schematic sheets for a PCB, but drawing every component on an ASIC schematic is
impractical.
9.1.1 Hierarchical Design

 Hierarchy reduces the size and complexity of a schematic.

 Suppose a building has 10 floors and contains several hundred offices but only three
different basic office plans. Furthermore, suppose each of the floors above the ground
floor that contains the lobby is identical. Then the plans for the whole building need only
show detailed plans for the ground floor and one of the upper floors. The plans for the
upper floor need only show the locations of each office and the office type. We can then
use a separate set of three detailed plans for each of the different office types. All these
different plans together form a nested structure that is a hierarchical design . The plan for
the whole building is the top-level plan. The plans for the individual offices are the lowest
level. To clarify the relationship between different levels of hierarchy we say that
a subschematic (an office) is a child of the parent schematic (the floor containing offices).

 An electrical schematic can contain subschematics. The subschematic, in turn, may

contain other subschematics. Figure 9.3 illustrates the principles of schematic hierarchical
design.

FIGURE 9.3  Schematic example showing hierarchical design. (a) The schematic of a half-adder, the subschematic
of cell HADD. (b) A schematic symbol for the half adder. (c) A schematic that uses the half-adder cell. (d) The
hierarchy of cell HADD.
 The alternative to hierarchical design is to draw all of the ASIC components on one giant
schematic, with no hierarchy, in a flat design . For a modern ASIC containing thousands
or more logic gates using a flat design or a flat schematic would be hopelessly
impractical. Sometimes we do use flat netlists though.
9.1.2 The Cell Library

 Components in an ASIC schematic are chosen from a library of cells.

 Library elements for all types of ASICs are sometimes also known as modules.
Unfortunately the term module will have a very specific meaning when we come to
discuss hardware description languages. To avoid any chance of confusion we use the
term cell to mean either a cell, a module, a macro, or a book from an ASIC library.

 Library cells are equivalent to the offices in our office building.

 Most ASIC companies provide a schematic library of primitive gates to be used for
schematic entry.

 The first problem with ASIC schematic libraries is that there are no naming conventions.
For example, a primitive two-input NAND gate in a Xilinx FPGA library does not have
the same name as the two-input NAND gate in an LSI Logic gate-array library. This
means that you cannot take a schematic that you used to create a prototype product using
a Xilinx FPGA and use that schematic to create an LSI Logic gate array for production
(something you might very likely want to do). As soon as you start entering a schematic
using a library from an ASIC vendor, you are, to some extent, making a commitment to
use that vendor’s ASIC. Most ASIC designers are much happier maintaining a large
degree of vendor independence.

 A second problem with ASIC schematic libraries is that there are no standards for cell
behavior. For example, a two-input MUX in an Actel library operates so that the input
labeled A is selected when the MUX select input S = '0'. A two-input MUX in a VLSI
Technology library operates in the reverse fashion, so that the input labeled B is selected
when S = '0'. These types of differences can cause hard-to-find problems when trying to
convert a schematic from one vendor to another by hand. These problems make changing
or retargeting schematics from one vendor to another difficult. This process is sometimes
known as porting a design.

 Library cells that represent basic logic gates, such as a NAND gate, are known
as primitive cells, usually referred to just as cells.

 In a hierarchical ASIC design a cell may be a NAND gate, a flip-flop, a multiplier, or

even a microprocessor, for example. To use the office building analogy again, each of the
three basic office types is a primitive cell. However, the plan for the second floor is also a
cell. The second-floor cell is a subschematic of the schematic for the whole building.

 Now we see why the commonly accepted use of the term cell in schematic entry can be so
confusing. The term cell is used to represent both primitive cells and subschematics.
These are two different, but closely related, things.
  There are two types of macros for MGAs and programmable ASICs.

 The most common type of macro is a hard macro that includes placement information. A
hard macro can change in position and orientation, but the relative location of the
transistors, other layout, and wiring inside the macro is fixed.

 A soft macro contains only connection information (between transistors for a gate array or
between logic cells for a programmable ASIC). Thus the placement and wiring for a soft
macro can vary. This means that the timing parameters for a soft macro can only be
determined after you complete the place-and-route step.

 For this reason the basic library elements for MGAs and programmable ASICs, such as
NAND gates, flip-flops, and so on, are hard macros.

 A standard cell contains layout information on all mask levels. An MGA hard macro
contains layout information on just the metal, contact, and via layers.

 An MGA soft macro or programmable ASIC macro does not contain any layout
information at all, just the details of connections to be made inside the macro.

 We can stretch the office building analogy to explain the difference between hard and soft
macros. A hard macro would be an office with fixed walls in which you are not allowed to
move the furniture. A soft macro would be an office with partitions in which you can
move the furniture around and you can also change the shape of your office by moving
the partitions.

9.1.3 Names

 Each of the cells, primitive or not, that you place on an ASIC schematic has a cell name.
Each use of a cell is a different instance of that cell, and we give each instance a
unique instance name. A cell instance is somewhere between a copy and a reference to a
cell in a library. An analogy would be the pictures of hamburgers on the wall in a fast-
food restaurant. The pictures are somewhere between a copy and a reference to a real
hamburger.

 We represent each cell instance by a picture or icon, also known as a symbol. We can
represent primitive cells, such as NAND and NOR gates, with familiar icons that look like
spades and shovels. Some schematic editors offer the option of switching between these
familiar icons and using the rectangular IEEE standard symbols for logic gates.
Unfortunately the term icon is also often used to refer to any of the pictures on a
schematic, including those that represent subschematics. There is no accepted way to
differentiate between an icon that represents a primitive cell and one that represents a
subschematic that may be in turn a collection of primitive cells. In fact, there is usually no
easy way to tell by looking at a schematic which icons represent primitive cells and which
 represent subschematics.

 We will have three different icons for each of the three different primitive offices in the
imaginary office building example of Section 9.1.1 . We also will have icons to represent
the ground floor and the plan for the other floors. We shall call the common plan for the
second through tenth floors, Floor. Then we say that the second floor is an instance of the
cell name Floor. The third through tenth floors are also instances of the cell name Floor.
The same icon will be used to represent the second through tenth floors, but each will
have a unique instance name. We shall give them instance
names: FloorTwo , FloorThree , ... , FloorTen . We say
that FloorTwo through FloorTen are unique instance names of the cell name Floor .

 At the risk of further confusion I should point out that, strictly speaking, the definition of
a primitive cell depends on the type of library being used. Schematic-entry libraries for
the ASIC designer stop at the level of NAND gates and other similar low-level logic
gates. Then, as far as the ASIC designer is concerned, the primitive cells are these logic
gates. However, from the view of the library designer there is another level of hierarchy
below the level of logic gates. The library designer needs to work with libraries that
contain schematics of the gates themselves, and so at this level the primitive cells are
transistors.

 Let us look at the building analogy again to understand the subtleties of primitive cells. A
building contractor need only concern himself with the plans for our office building down
to the level of the offices. To the building contractor the primitive cells are the offices.
Suppose that the first of the three different office types is a corner office, the second office
type has a window, and a third office type is without a window. We shall call these office
cells: CornerOffice , WindowOffice , and NoWindowOffice . These cells are primitive
cells as far as the contractor is concerned. However, when discussing the plans with a
client, the architect of our building will also need to see how each offices is furnished.
The architect needs to see a level of detail of each office that is more complicated than
needed by the building contractor. The architect needs to see the cells that represent the
tables, chairs, and desks that make up each type of office. To the architect the primitive
cells are a library containing cells such as chair , table , and desk .

** Explanations of terms used in notes **

1. {¥ : The yen (Japanese: symbol: ¥) is the official currency of Japan}

 2. Spades and Shovels: Shovel is a generic term for a variety of tools that include
numerous broad-bottomed versions for moving loose materials, such as a "coal shovel",
"snow shovel", "grain shovel", etc., whereas spades tend to have a sharpened edge,
curved profile, and pointed end better designed for digging.

9.2  Low-Level Design Languages( Text rep.)

 Schematics can be a very effective way to convey design information because
pictures are such a powerful medium. There are two major problems with
schematic entry, however.
 The first problem is that making changes to a schematic can be difficult. When
you need to include an extra few gates in the middle of a schematic sheet, you
may have to redraw the whole sheet.
 The second problem is that for many years there were no standards on how
symbols should be drawn or how the schematic information should be stored in a
netlist.
 These problems led to the development of design-entry tools based on text rather
than graphics. As TTL gave way to PLDs, these text-based design tools became
increasingly popular as de facto standards began to emerge for the format of the
design files.
 PLDs are closely related to FPGAs. The major advantage of PLD tools is their
low cost, their ease of use, and the tremendous amount of knowledge and number
of designs, application notes, textbooks, and examples that have been built up
over years of their use. It is natural then that designers would want to use PLD
development systems and languages to design FPGAs and other ASICs. For
example, there is a tremendous amount of PLD design expertise and working
designs that can be reused.
 In the case of ASIC design it is important to use the right tool for the job. This
may mean that you need to convert from a low-level design medium you have
used for PLD design to one more appropriate for ASIC design. Often this is
because you are merging several PLDs into a single, much larger, ASIC. The
reason for covering the PLD design languages here is not to try and teach you
how to use them, but to allow you to read and understand a PLD language and, if
necessary, convert it to a form that you can use in another ASIC design system.

9.2.1 ABEL (Advanced Boolean Equation Language)

ABEL is a PLD programming language from Data I/O. Table 9.2 shows some examples of the ABEL statements. The following example code describes a
4:1 MUX (equivalent to the LS153 TTL part):

TABLE 9.2  ABEL.
Statement Example Comment
Module module MyModule You can have multiple modules.
Title title 'Title in a String' A string is a character series between quotes.
MYDEV is Device ID for documentation.
Device MYDEV device '22V10' ;
22V10 is checked by the compiler.
Comment "comments go between double quotes" The end of a line signifies the end of a comment; there is no need for an end quote.
 "end of line is end of comment
@ALTERNATE @ALTERNATE "use alternate symbols operator alternate default
AND * &

OR + #

    NOT / !

XOR :+: $

XNOR :*: !$
Pin 22 is the IO for input on pin 2 for a 22V10.
MYINPUT pin 2; I3, I4 pin 3, 4 ;
Pin declaration MYOUTPUT is active-low at the chip pin.
/MYOUTPUT pin 22; IO3,IO4 pin 21,20 ;
Signal names must start with a letter.
Equations equations Defines combinational logic.
  IO4 = HELPER ; HELPER = /I4 ; Two-pass logic
Assignments MYOUTPUT = /MYINPUT ; Equals '=' is unlocked assignment.
  IO3 := I4 ; Clocked assignment operator (registered IO)
D = [D0, D1, D2, D3] ;
Signal sets A signal set, an ABEL bus
Q = [Q0, Q1, Q2, Q3];
  Q := D ; 4-bit-wide register
Suffix MYOUTPUT.RE = CLR ; Register reset
  MYOUTPUT.PR = PRE ; Register preset
COUNT = [D0, D1, D2]; Can’t use @ALTERNATE
Addition
COUNT := COUNT + 1; if you use '+' to add.
ENABLE IO3 = IO2; Three-state enable (ENABLE is a keyword).
Enable
IO3 = MYINPUT; IO3 must be a three-state pin.
Constants K = [1, 0, 1] ; K is 5.
Relational IO# = D == K5 ; Operators: ==    !=   <    >    <=    >=
End end MyModule Last statement in module

Example:
module MUX4

title '4:1 MUX'

MyDevice device 'P16L8' ;

@ALTERNATE

"inputs

A, B, /P1G1, /P1G2 pin 17,18,1,6 "LS153 pins 14,2,1,15

P1C0, P1C1, P1C2, P1C3 pin 2,3,4,5 "LS153 pins 6,5,4,3

P2C0, P2C1, P2C2, P2C3 pin 7,8,9,11 "LS153 pins 10,11,12,13

"outputs

P1Y, P2Y pin 19, 12 "LS153 pins 7,9

equations

P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3);

P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3);

end MUX4

9.2.2 CUPL
CUPL is a PLD design language from Logical Devices. We shall review the CUPL 4.0 language here. The following code is a simple CUPL example
describing sequential logic:

Example:

SEQUENCE BayBridgeTollPlaza {

PRESENT red

IF car NEXT green OUT go; /* conditional synchronous output */

DEFAULT NEXT red; /* default next state */

PRESENT green

NEXT red; } /* unconditional next state */

This code describes a state machine with two states. Table 9.3 shows the different state machine assignment statements.

TABLE 9.3  CUPL statements for state-machine entry.

Statement Description
IF NEXT   Conditional next state transition
IF NEXT OUT Conditional next state transition with synchronous output
  NEXT   Unconditional next state transition
  NEXT OUT Unconditional next state transition with asynchronous output
    OUT Unconditional asynchronous output
IF   OUT Conditional asynchronous output
DEFAULT NEXT   Default next state transition
DEFAULT   OUT Default asynchronous output
DEFAULT NEXT OUT Default next state transition with synchronous output

 You may also encode state machines as truth tables in CUPL. Here is another simple example:

FIELD input = [in1..0];

FIELD output = [out3..0];

TABLE input => output {00 => 01; 01 => 02; 10 => 04; 11 => 08; }

 CUPL file for a 4-bit counter (for an ATMEL PLD) that illustrates
extensions:

Name 4BIT; Device V2500B;

/* inputs */
pin 1 = CLK; pin 3 = LD_; pin 17 = RST_;
pin [18,19,20,21] = [I0,I1,I2,I3];
/* outputs */
pin [4,5,6,7] = [Q0,Q1,Q2,Q3];
field CNT = [Q3,Q2,Q1,Q0];
/* equations */
Q3.T = (!Q2 & !Q1 & !Q0) & LD_ & RST_ /* count down */
# Q3 & !RST_ /* ReSeT */
# (Q3 $ I3) & !LD_; /* LoaD*/
Q2.T = (!Q1 & !Q0) & LD_ & RST_ # Q2 & !RST_ # (Q2 $ I2) & !LD_;
Q1.T = !Q0 & LD_ & RST_ # Q1 & !RST_ # (Q1 $ I1) & !LD_;
Q0.T = LD_ & RST_ # Q0 & !RST_ # (Q0 $ I0) & !LD_;

CNT.CK = CLK; CNT.OE = 'h'F; CNT.AR = 'h'0; CNT.SP = 'h'0;

CUPL extensions guide the logic fitter, for example:

output.ext = (Boolean expression);
.OE is output enable
.CK marks the clock
.T configures sequential logic as T flip-flops
.OE (wired high) is an output enable
.AR (wired low) is an asynchronous reset

.SP (wired low) is an synchronous preset

TABLE 9.5  CUPL 4.0 extensions.

Extension 1   Explanation   Extension   Explanation
D register feedback of
D L D input to a D register   DFB R
combinational output
Latched feedback of
L L L input to a latch   LFB R
combinational output
T register feedback of
J, K L J-K-input to a J-K register   TFB R
combinational output
S, R L S-R input to an S-R register   INT R Internal feedback
T L T input to a T register   IO R Pin feedback of registered output
DQ R D output of an input D register   IOD/T R D/T register on pin feedback path selection
Latch on pin feedback path
LQ R Q output of an input latch   IOL R
selection
Asynchronous preset/reset of
AP, AR L Asynchronous preset/reset   IOAP, IOAR L
register on feedback path
Synchronous preset/reset of
SP, SR L Synchronous preset/reset   IOSP, IOSR L
register on feedback path
CK L Product clock term (async.)   IOCK L Clock for pin feedback register
Asynchronous preset/reset
OE L Product-term output enable   APMUX, ARMUX L
multiplexor selection
CA L Complement array   CKMUX L Clock multiplexor selector
PR L Programmable preload   LEMUX L Latch enable multiplexor selector
Output enable multiplexor
CE L CE input of a D-CE register   OEMUX L
selector
LE L Product-term latch enable   IMUX L Input multiplexor selector of
 two pins
OBS L Programmable observability of buried nodes   TEC L Technology-dependent fuse selection
BYP L Programmable register bypass   T1 L T1 input of 2-T register

9.2.3 PALASM
PALASM is a PLD design language from AMD/MMI. Table 9.7 shows the format of PALASM statements. The following simple example (a video shift
register) shows the most basic features of the PALASM 2 language:

TABLE 9.7  PALASM 2.
Statement Example Comment
Chip CHIP abc 22V10 Specific PAL type
  CHIP xyz USER Free-form equation entry
Pinlist CLK /LD D0 D1 D2 D3 D4 GND NC Q4 Q3 Q2 Q1 Q0 /RST VCC Part of CHIP statement; PAL pins in numerical order starting with pin 1
String STRING string_name 'text' Before EQUATIONS statement
Equations EQUATIONS After CHIP statement
  A = /B Logical negation
  A=B*C Logical AND
  A=B+C Logical OR
  A = B :+: C Logical exclusive-OR
  A = B :*: C Logical exclusive-NOR
Polarity inversion /A = /(B + C) Same as A = B + C
Assignment A=B+C Combinational assignment
  A := B + C Registered assignment
Comment A = B + C ; comment Comment
Functional equation name.TRST Output enable control
  name.CLKF Register clock control
  name.RSTF Register reset control
  name.SETF Register set control

Example:
TITLE video ; shift register

CHIP video PAL20X8

CK /LD D0 D1 D2 D3 D4 D5 D6 D7 CURS GND NC REV Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 /RST VCC

STRING Load 'LD*/REV*/CURS*RST' ; load data

STRING LoadInv 'LD*REV*/CURS*RST' ; load inverted of data

STRING Shift '/LD*/CURS*/RST' ; shift data from MSB to LSB

EQUATIONS

/Q0 := /D0*Load+D0*LoadInv:+:/Q1*Shift+RST

/Q1 := /D1*Load+D1*LoadInv:+:/Q2*Shift+RST

/Q2 := /D2*Load+D2*LoadInv:+:/Q3*Shift+RST

/Q3 := /D3*Load+D3*LoadInv:+:/Q4*Shift+RST

/Q4 := /D4*Load+D4*LoadInv:+:/Q5*Shift+RST

/Q5 := /D5*Load+D5*LoadInv:+:/Q6*Shift+RST

/Q6 := /D6*Load+D6*LoadInv:+:/Q7*Shift+RST

/Q7 := /D7*Load+D7*LoadInv:+:Shift+RST;

9.3  PLA Tools
 Developed at UC Berkeley
 eqntott :input format
 espresso :logic-minimization program
 widely used tools in the 1980s
 important stepping stones to modern logic synthesis software
9.4  EDIF

 An ASIC designer spends an increasing amount of time forcing different tools to

communicate. One standard for exchanging information between EDA (Electronic
Design Automation) tools is the electronic design interchange format ( EDIF ).
 Some versions of EDIF are EDIF version 2 0 0, EDIF 3 0 0, EDIF 4 0 0.
 The most important features added in EDIF 3 0 0 were to handle buses, bus rippers, and
buses across schematic pages.
 EDIF 4 0 0 includes new extensions for PCB and multichip module (MCM) data.
The Library of Parameterized Modules ( LPM ) standard is also based on EDIF.
 The newer versions of EDIF have a richer feature set, but the ASIC industry seems to
have standardized on EDIF 2 0 0. Most EDA companies now support EDIF. The FPGA
 companies Altera and Actel use EDIF as their netlist format, and Xilinx has announced
its intention to switch from its own XNF format to EDIF.
 A complete description of the EDIF standard is contained in the Electronic Industries
Association ( EIA ) publication, Electronic Design Interchange Format Version 2 0 0
( ANSI/EIA Standard 548-1988) [ EDIF, 1988].

9.4.1 EDIF Syntax

 The structure of EDIF is similar to the Lisp programming language or the Postscript

printer language. This makes EDIF a very hard language to read and almost impossible to
write by hand.

 EDIF is intended as an exchange format between tools, not as a design-entry language.

Since EDIF is so flexible each company reads and writes different “flavors” of EDIF.

 Inevitably EDIF from one company does not quite work when we try and use it with a
tool from another company, though this situation is improving with the gradual adoption
of EDIF 3 0 0. We need to know just enough about EDIF to be able to fix these problems.

FIGURE 9.8  The hierarchical nature of an EDIF file.

  

 Figure 9.8 illustrates the hierarchy of the EDIF file.

 Within an EDIF file are one or more libraries of cell descriptions. Each library contains
technology information that is used in describing the characteristics of the cells it
contains. Each cell description contains one or more user-named views of the cell. Each
view is defined as a particular viewType and contains an interface description that
identifies where the cell may be connected to and, possibly, a contents description that
identifies the components and related interconnections that make up the cell.

 The EDIF syntax consists of a series of statements in the following format:

(keywordName {form})
  A left parenthesis (round bracket) is always followed by a keyword name , followed by
one or more EDIF forms (a form is a sequence of identifiers, primitive data, symbolic
constants, or EDIF statements), ending with a right parenthesis. EDIF uses a “define it
before you use it” approach.

 The semantics of EDIF are defined by the EDIF keywords. Keywords are the only types
of name that can immediately follow a left parenthesis. Case is not significant in
keywords.

 An EDIF identifier represents the name of an object or group of data. Identifiers are used
for name definition, name reference, keywords, and symbolic constants. Valid EDIF
identifiers consist of alphanumeric or underscore characters and must be preceded by an
ampersand ( &) if the first character is not alphabetic. The ampersand is not considered
part of the name. The length of an identifier is from 1 to 255 characters and case is not
significant. Thus &clock , Clock , and clock all represent the same EDIF name (very
confusing).

 Numbers in EDIF are 32-bit signed integers. Real numbers use a special EDIF format.
For example, the real number 1.4 is represented as (e 14 -1) . The e form requires a
mantissa ( 14 ) and an exponent ( -1 ). Reals are restricted to the range ± 1 ¥ 10 ± 35 .
Numbers in EDIF are dimensionless and the units are determined according to where the
number occurs in the file. Coordinates and line widths are units of distance and must be
related to meters. Each coordinate value is converted to meters by applying a scale
factor . Each EDIF library has a technology section that contains a
required numberDefinition . The scale keyword is used with the numberDefinition to
relate EDIF numbers to physical units.

 Valid EDIF strings consist of sequences of ASCII characters enclosed in double quotes.

Any alphanumeric character is allowed as well as any of the following characters: ! # $ &
' () * + , -   . / : ; < = > ? @ [ \ ] ^ _ ` { | } ~ . Special characters, such as " and % are
entered as escape sequences: %number% , where number is the integer value of the
ASCII character.

 The rename keyword can be used to create a new EDIF identifier as follows: (cell

(rename TEST_1 "test$1") ...

 In this example the EDIF string contains the original name, test$1, and a new
name, TEST_1 , is created as an EDIF identifier.

9.4.2 An EDIF Netlist Example

TABLE 9.11  EDIF file for the halfgate netlist
9.4.3 An EDIF Schematic Icon

9.4.4 An EDIF Example

EDIF file for a standard-cell schematic icon
An overview of VHDL and verilog
VHDL and Verilog, both are the hardware description languages. Both are considered general-purpose digital design
languages, each with subtle differences and advantages over the other.

Hardware Description Languages (HDLs)

 HDLs are indeed similar to programming languages but not exactly the same. We utilize a programming language to
build or create software, whereas we use a hardware description language to describe or express the behavioral
characteristics of digital logic circuits.

 We utilize HDLs for designing processors, motherboards, CPUs (i.e., computer chips), as well as various other digital
circuitry.

VHDL

 Very High-Speed Integrated Circuit Hardware Description Language (VHDL) is a

description language used to describe hardware.

 It is utilized in electronic design automation to express mixed-signal and digital

systems, such as ICs (integrated circuits) and FPGA (field-programmable gate arrays).
We can also use VHDL as a general-purpose parallel programming language.

 We utilize VHDL to write text models that describe or express logic circuits. If the text
model is part of the logic design, the model is processed by a synthesis program. The next
 step in the process incorporates a simulation program to test the logic design. During this
step, we utilize the simulation models to characterize the logic circuits that interface to
the design. We refer to this collection of simulation models as a testbench.

 Typically, a VHDL simulator is an event-driven simulator which means that we add each
transaction to an event queue for a particular scheduled time. For example, if a signal
assignment occurs after one nanosecond, we add the event to the queue as time + 1ns.

 The VHDL design is mostly dependent on the IEEE standard 1164 and also refers to the
Math and Numeric packages in order to make the utility of language more enhanced. 

Verilog
 The Verilog is actually derived from the C programming languages and Hilo which is an
old hardware description language. It is a very limited and weakly typed language that
has all the predefined data types in it. The datatypes are represented in bit-level. Other
data types like strings can be mixed with the Verilog.
 There is very ambiguous simulation semantics in Verilog as compared to VHDLs. As a
result of this, the developers find Verilog very flexible but there is a drawback of the
resulting race conditions due to ambiguity if guidelines are not followed while coding. It
is very difficult to provide the reusability function of packages because of the limited
scope of language and incapable packaging capability.
 There is a provision of basic simulation control commands in Verilog which help to do
the system tasks. Command-line or batch simulations are used by the Verilog developers
because of predefined system tasks and simple data types and debugging can be done by
seeing waveforms from the simulation.
 Verilog HDL is an IEEE standard (IEEE 1364). It received its first publication in 1995,
with a subsequent revision in 2001. SystemVerilog, which is the 2005 revision of
Verilog, is the latest publication of the standard. We call the IEEE Verilog standard
document the LRM (Language Reference Manual). Currently, the IEEE 1364 standard
defines the PLI (Programming Language Interface).

Note: The PLI is a collective of software routines that allows a bidirectional interface between
other languages such as C and Verilog.

Comparison Table of Verilog vs VHDL

The following table demonstrates the detailed comparison between the Verilog and VHDL in detail –

Verilog VHDL

Verilog is weakly typed language with It is strongly typed language.

datatypes like bit, bit-vector, wire, reg,
unsigned, signed, integer, real and
sometimes strings too.

User-defined datatypes are not supported User-defined data types are supported in
in Verilog. VHDL.

No support for dynamic memory Dynamic memory allocation is supported

allocation. in VHDL with the help of pointers.

Named events can be used. We cannot use the named events in

VHDL.

Associative and sparse arrays cannot be We can model the access types partially by
used. using associative and sparse arrays.

We can use the bit and integer Standard packages can be used for
equivalence in Verilog. supporting the bit/vector integer
equivalence partially.

No support for other hierarchies. Other hierarchies can be added by using

separate entities and using the architecture
of interface and implementation.

Partial support for binding and Complete support for configuration and
configuration by controlling the instance binding by having the control over the
to module binding. components and instance binding to the
created entities.

Conditional statements can be We can implement the conditional

implemented by using if, if-else and case statement by using the if and iterative
statements while iterative behavior is statements by using the for loop.
achieved by using the for loop.