Microprocessor Architecture

and Overview
ARM Microprocessor Architecture
 What we will learn in this section:

 ARM REGISTER
 ARM GENERAL PURPOSE REGISTERS (GPRs)
 Current Program Status Register (CPSR )
 Memory Map System
3
Basic Elements of a Central Processing Unit

Address Bus

Program Counter

Instruction Register

Flags ALU
Instruction decoder, Control Bus
timing, and control
Data Bus

Internal Buses Register A

Register B

Register C

Register D
 ARM REGISTERS
 In the CPU, registers are used to store information temporarily
and most of the operations, such as arithmetic and logic
operations, involve the registers
That information could be a piece of data to be
processed or an address pointing to the data to be
fetched
 To program in assembly language, we must understand the
registers of a given CPU and the role they play in processing
data
 ARM General Purpose Registers (GPRs)
 All of ARM registers are 32-bit wide. The 32 bits of a register are shown in Figure 2-1.
 These range from the MSB (most-significant bit) D31 to the LSB (least-significant bit) D0.
 With a 32-bit data type, any data larger than 32 bits must be broken into 32-bit chunks
before it is processed.

Figure 2- 1: ARM Registers Data Size

 32-bit data size is referred as word.
 16-bit data is referred to as half-word.
 8-bit data size is referred as “byte”

 ARM supports byte, half-word (two byte),

and word (four bytes) data types.
 ARM Registers
 In ARM there are 13 general purpose registers.
They are R0–R12(same as the accumulator)
 All of these registers are 32 bits wide.
 The ARM core has three special
function registers (R13, R14 & R15)
 R13 : Stack Pointer (SP):
points to the top of the stack; section of RAM that store
information temporarily.

 R14 : Link Register (LR) : holds the return address

when the CPU calls a subroutine

 R15 : Program Counter (PC) : holds Figure 2- 2: ARM Registers

address of next instruction
ARM ALU ARM Registers
 Figure 2-3 shows the general purpose registers (GPRs) & the ALU in ARM
 Table 2-1 shows some of the ARM ALU instructions

Figure 2- 3: ARM Registers and ALU

Table 2- 1: ALU Instructions Using GPRs

 Current Program Status Register (CPSR)
CPSR (Current Program Status Register)
 the status register is a 32-bit register (Figure 2-4)
 bits N, Z, C, and V are called conditional flags that indicate conditions
that resulted after an instruction is executed.
indicate arithmetic conditions such as a carry, negative, zero etc.
can be used to perform a conditional execution

Figure 2-4 : CPSR (Current Program Status Register)

Flag bits of CPSR

 N, the negative flag

The negative flag reflects the result of an arithmetic operation
Binary representation of signed numbers uses D31 as the sign
bit.
If the D31 bit of the result is zero, then N = 0 and the result is
positive.
 If the D31 bit is one, then N = 1 and the result is negative.
The N flag bit is used for the signed number arithmetic
operations
Flag bits of CPSR (cont…)

Z, the zero flag

The zero flag reflects the result of an arithmetic or
logic operation.
If the result is zero, then Z = 1.
If the result is not zero, Z = 0.
The Z flag can be used in loops
Flag bits of CPSR (cont…)

 C, the carry flag

C flag is set whenever there is a carry out from the D31 bit.
C flag bit is affected after a 32-bit addition or subtraction.
 C flag is used to detect errors in unsigned arithmetic
operations
 V, the overflow flag
V flag is set whenever the result of a signed number
operation is too large, causing the high-order bit to
overflow into the sign bit.
V flag is used to detect errors in signed arithmetic
operations.
 The C and V flag bits are used for signed number arithmetic
operations
Flag bits of CPSR (cont…)
 T flag
used to indicate the ARM is in Thumb state
 I and F flags
used to enable or disable the interrupt (See the ARM
manual)
 I : IRQ Mask Bit , F : FIRQ Mask Bit
 M0-M4 flags
 Mode field
18
Current Program Status Registers
CPSR is a 32-bit register

T flag indicates the ARM is in

I & F flags enables & Thumb state
disable interrupt
V - Overflow flag
• V=1 when the result of
signed number
operation is too large

C - Carry flag
N- negative flag • C=1 when there is a
• N=0 when the D31 bit of the carry out from bit D31
result is 0 which means the • It is affected by
result is +ve Z - zero flag
• Z=1 when the result addition or subtraction
• N=1 when the D31 bit of the
result is 1 which means the is zero
result is -ve • Z=0 when the result
• It is used for the signed is non-zero
number arithmetic operations • It is used in loops
 ARM Instruction Format
 uses the “tri-part” instruction format (most common format)
instruction destination, source1, source2

 where
source1, source2 can be a register, immediate (constant)
value, or memory
destination is often a register or read/write memory
ARM instructions operate on the data in the registers with the
exception of load and store instructions, which move the
data between registers and memory
 MOV instruction
 Uses to copies data into register or from register to register.
MOV Rn,Op2 ;load Rn register with Op2 (Operand2)
;Op2 can be immediate
 Op2 can be an immediate (constant) number #K which is
an 8-bit value that can be 0–255 in decimal, (00–FF in hex).
 Op2 can also be a register Rm. Rn or Rm are any of the
registers R0 to R15.
 MOV instruction (Immediate Values)

 MOV R2,#0x25 ;load R2 with 0x25 (R2 = 0x25)

 MOV R1,#0x87 ;copy 0x87 into R1 (R1 = 0x87)
 MOV R1,#87 ;copy decimal value of 87 into R1
 MOV R5,R7 ;copy contents of R7 into R5 (R5 = R7)
 ADD instruction
 format: ADD Rd, Rn, Op2

 tells the CPU to add the value of Op2 to Rn and put

the result into the Rd (destination) register.

Op2 (Operand2) can be an immediate value or it

can be a register Rm
Rd, Rn and Rm can be any of the registers R0 to R15
 ADD instruction (cont…)

 Example: To add two numbers such as 0x25 and 0x34, one can do either:

MOV R1, #0x25 ; copy 0x25 into R1 (R1 = 0x25)

MOV R7, #0x34 ; copy 0x34 into R7 (R7 = 0x34)
ADD R5, R1, R7 ; add value R7 to R1 and put it in R5 (R5 = R1 + R7) (old FORMAT)

or
MOV R1, #0x25 ; load (copy) 0x25 into R1 (R1 = 0x25)
ADD R5, R1, #0x34 ; add 0x34 to R1 and put it in R5 (R5 = R1 + 0x34)
Example 2-1
Show the status of the C and Z flags after the addition of
0x0000009C and 0xFFFFFF64 in the following instruction:
; assume R1 = 0x0000009C and R2 = 0xFFFFFF64
ADDS R3, R1, R2 ; add R1 to R2 and place the result in R3

0000 0000 0000 0000 0000 0000 1001 1100 (0x0000009C)

+ 1111 1111 1111 1111 1111 1111 0110 0100 (0xFFFFFF64)
1 0000 0000 0000 0000 0000 0000 0000 0000 (0x00000000)

 C = 1 because there is a carry beyond the D31 bit

 Z = 1 because the R2 (the result) has value 0 in it after the
addition
Example 2-2
Show the status of the C and Z flags after the addition of
0x0000009C and 0xFFFFFF69 in the following instruction:
; assume R1 = 0x0000009C and R2 = 0xFFFFFF69
ADDS R2, R1, R2 ; add R1 to R2 and place the result in R2

0000 0000 0000 0000 0000 0000 1001 1100 (0x0000009C)

+ 1111 1111 1111 1111 1111 1111 0110 1001 (0xFFFFFF69)
1 0000 0000 0000 0000 0000 0000 0000 0101 (0x00000005)

 C = 1 because there is a carry beyond the D31 bit

 Z = 0 because the R2 (the result) does not have value 0 in it after the
addition (R2 = 0x00000005)
S suffix and the status register
By default, the status flags of CPSR are not updated when an instruction is
executed.
If we need an instruction to update the value of status bits in CPSR, we have to
put the ‘S’ suffix at the end of the opcode.

Example: ADDS will update CPSR while ADD will not

Table 2- 2: Flag Bits Affected by

Different Instructions
Not all instructions affect the flags
Some instructions affect all the four flag bits C, Z, V,
and N
Example: ADDS
Some instructions affect no flag bits at all
Example: branch instructions
Some instructions affect only some of the flag bits
Example: logic instructions such as ANDS
Flag bits and decision making
 Most of the ARM instructions may be executed conditionally based
on the status of the flag bits in CPSR
To make an instruction conditionally executed, the desired
condition code is added to the opcode as the postfix
 The conditional branch instructions are commonly used
Table 2-4 shows some of the conditional branch instructions

Table 2- 4: ARM Branch (Jump) Instructions

Using Flag Bits
24 ARM Memory Space
 The ARM has 4G bytes of directly
accessible memory space. Addresses
0 to 0XFFFFFFFF
 On-chip peripheral and I/O registers
 On-chip data SRAM
 On-chip EEPROM
 On-chip Flash ROM
 Off-chip DRAM space

Figure 2-4 : An example of ARM Memory Allocation

 Memory System
 On-chip peripheral and I/O registers
 This area is dedicated to general purpose I/O (GPIO) and special function registers (SFRs) of
peripherals such as timers, serial communication, ADC etc
 ARM uses memory-mapped I/O.
 Memory area dedicated to registers of peripherals such as timers, serial communication, ADC,
and so on.
 The function and address location of each register is fixed by the chip vendor at the time of
design.
 The type, number and address locations for the peripherals vary among various devices.
 On-chip data static RAM (SRAM)
 Data SRAM is used for data variables and stack.
 Size ranges from 2KB to several thousands of kilobytes (KB) depending on the chip.
ARM Memory System
 On-chip EEPROM
 Can integrate in code region.
 Most often used for saving critical data.
 Size ranges from 1KB to several KB.
 Not all ARM chips have on-chip EEPROM.
 A block of memory from 1K bytes to several thousand bytes is set aside for EEPROM memory
 On-chip Flash ROM
 Used to store program code.
 Size ranges from few kilobytes (KB) to Megabytes(MB).
 Off-chip DRAM space
 Implemented for external memory connection.
 Used for high-end of the market such as servers and database computers.
 Cortex M4 Memory System
0xE00FFFFF 0xE000EFFF
0xFFFFFFFF
Private peripherals including Private System
Vendor specific
built-in interrupt controller (NVIC) Peripheral Control Space
memory 511MB
and debug components. Bus (PPB) (SCS)
0xE0000000 1.0MB
0xDFFFFFFF 0xE0000000 0xE000E000

External
1.0GB
Mainly used for external peripherals. device

0xE0000000
0xDFFFFFFF

External
Mainly used for external memory. 1.0GB
RAM 0x43FFFFFF

32MB Bit band alias

0x60000000 0x42000000
0x5FFFFFFF

Mainly used for peripherals. Peripheral 0.5GB 0x400FFFFF

1MB Bit band region
0x40000000
0x40000000
0x3FFFFFFF
0x23FFFFFF
Mainly used for data memory 0.5GB
SRAM 32MB Bit band alias
(e.g. static RAM).
0x20000000 0x22000000
Mainly used for program code. 0x1FFFFFFF
0x200FFFFF
Also used for exception vector Code 0.5GB 1MB Bit band region
0x20000000
table.
0x00000000
ARM Memory System

 High flexibility – allow memory regions to be used for other purposes.

 For example, programs can be executed from the CODE as well as the SRAM
region,
 Can also integrate SRAM blocks in CODE region.
 In practice, many microcontroller devices only use a small portion of each
region for program flash, SRAM, and peripherals.
 Some of the regions can be unused.
 Different microcontrollers have different memory sizes and peripheral address
locations.
 The memory map arrangement is consistent between all the Cortex-M
processors.
Memory System

 Although the CPU can access 4GB of locations, no ARM chips have the
entire 4GB of on-chip memory populated.

Table 2- 2: On-chip Memory Size for some ARM Chips

 Exercises
1. True or false. The GPR registers are used for storing data.
2. The R0-R12 registers are called______.
3. The GPR registers in ARM are _____-bit.
4. The R13-R15 registers are called _____.
5. The SFR registers in ARM are ______ -bit.
6. The flag register in the ARM is called the ________.
7. What is the size of the flag register in the ARM?
8. Find the C and Z flag bits for the following code:
;assume R2 = 0xFFFFFF9F
;assume R1 = 0x00000061
ADDS R2, R1, R2
9. Find the C and Z flag bit for the following code:
;assume R7 = 0x00000022
;assume R3 = 0x00000022
ADDS R7, R3, R7
10. Find the C and Z flag bits for the following code:
;assume R2 = 0x00000067
;assume R1 = 0xFFFFFFF99
ADDS R2, R1, R2