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Embedded System Design Using Vivado: After Completing This Course, You Will Be Able To

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Ahmet Haydar Erdem
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101 views4 pages

Embedded System Design Using Vivado: After Completing This Course, You Will Be Able To

Uploaded by

Ahmet Haydar Erdem
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Embedded System Design using Vivado

This material exempt per Department of Commerce license exception TSU

Course Objectives

After completing this course, you will be able to:


– Assemble an advanced embedded system and explore advanced techniques to improve system performance
– Take advantage of the various features of the Zynq AP Soc and Cortex™-A9 processor, including the AXI
interconnect, and the various memory controllers
– Apply advanced debugging techniques, including the use of the Vivado Analyzer tool for debugging an embedded
system
– Identify the steps involved in integrating a memory controller into an embedded system in Zynq SoC
– Integrate an interrupt controller and interrupt handler into an embedded design
– Design a flash memory-based system and boot load from off-chip QSPI Flash memory
– Configure and boot up system using SD card
– Profile a software application and observe the impact of porting a software function into a hardware accelerator

Course Intro 01- 2 © Copyright 2016 Xilinx


Course Outline

The course consists of the following modules:


Review of Embedded System Design in Zynq using Vivado
Lab 1: Simple Hardware Design
Zynq Architecture
Extending the Embedded System into PL
Lab 2: Adding IPs in Programmable Logic
Adding Your Own Peripheral
Lab 3: Creating and Adding Custom IP
Software Development Environment
Lab 4: Software Debugging Using SDK

Course Intro 01- 3 © Copyright 2016 Xilinx

Course Outline

Advanced Zynq Architecture


System Debugging using Vivado Logic Analyzer and SDK
Lab 5: Debugging using Vivado Logic Analyzer
Memory Interfacing
Lab 6: Extending Memory Space with BRAM
Interrupts
Low Latency High Bandwidth
Lab 7: Direct Memory Access using CDMA

Course Intro 01- 4 © Copyright 2016 Xilinx


Course Outline

Processor Configuration and Bootloader


Lab 8: Configuration and Booting
Profiling and Performance Improvement
Lab 9: Profiling and Performance Tuning

Course Intro 01- 5 © Copyright 2016 Xilinx

Prerequisites

Familiarity with the Xilinx tool set and design flow


Basic C programming
Basic understanding of processor-based system
Basic HDL knowledge

Course Intro 01- 6 © Copyright 2016 Xilinx


Platform Support

Vivado Design Suite: System Edition 2016.4


Xilinx University board
– ZedBoard or Zybo

Supported Operating Systems


– Windows 7 and 7 SP1 Professional (64 Bit)
– Windows 8.1 Professional (64 Bit)
– Windows 10 Professional (64 Bit)
– Red Hat Enterprise Linux 5.11 (64 Bit)
– Red Hat Enterprise Linux 6.6 – 6.7 (64 Bit)
– Red Hat Enterprise Linux 7.0 – 7.1 (64 Bit)
– SUSE Linux Enterprise 11.3 and 12.0 (64 Bit)
– Centos Linux 6.7 and 7.1 (64 Bit)
– Ubuntu Linux 14.04.3 LTS (64 Bit)

Course Intro 01- 7 © Copyright 2016 Xilinx

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