0% found this document useful (0 votes)
221 views3 pages

C-Mos FDC (Floppy Disk Controller)

This document contains a datasheet for a C-MOS FDC (floppy disk controller). It includes a pinout diagram showing the 64 pins of the controller and their corresponding signals. It lists the input, output, and input/output pins and provides a brief description of each signal. The block diagram shows the internal components of the controller including ROM, RAM, an ALU, timer, and interfaces to the host computer and floppy disk drive.

Uploaded by

Bos Qu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
221 views3 pages

C-Mos FDC (Floppy Disk Controller)

This document contains a datasheet for a C-MOS FDC (floppy disk controller). It includes a pinout diagram showing the 64 pins of the controller and their corresponding signals. It lists the input, output, and input/output pins and provides a brief description of each signal. The block diagram shows the internal components of the controller including ROM, RAM, an ALU, timer, and interfaces to the host computer and floppy disk drive.

Uploaded by

Bos Qu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

HD63266F (1/3)

********** IL00

C-MOS FDC (FLOPPY DISK CONTROLLER)


—TOP VIEW—
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
GND
VDD (+5V)
VDD (+5V)
VDD (+5V)
NC

NC

NC
NC
49 GND 32
50 31
51 30
52 29
53 28
54 GND 27
55 26
56 VDD(+5V) 25
57 24
58 GND 23
59 GND 22
60 21
61 20
62 19
63 18
64 GND
GND
GND

17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

(VDD = +5V)
PIN PIN PIN PIN
I/O
No. I/O SIGNAL No. I/O SIGNAL No. SIGNAL No. I/O SIGNAL

1 I 8" / 5" 17 I/O D5 33 I TRK0 49 — GND


2 I XTALSEL 18 I/O D6 34 I INDEX 50 O STEP
3 I RESET 19 I/O D7 35 I RDATA 51 O HDIR
4 I E, RD 20 O DREQ 36 I XTAL2 52 O HLOAD
5 I R/W, WR 21 O IRQ 37 — NC 53 O HSEL
6 I CS 22 I DEND 38 — NC 54 — GND
7 I DACK 23 — GND 39 I XTAL1 55 O DS0
8 I RS0 24 O 1/2EX1 40 — NC 56 O DS1
9 I RS1 25 — VDD 41 — GND 57 O DS2
10 — GND 26 I NUM1 42 — GND 58 O DS3
11 — GND 27 I NUM2 43 — NC 59 — GND
12 I/O D0 28 I IFS 44 — VDD 60 O MON0
13 I/O D1 29 I SFORM 45 — VDD 61 O MON1
14 I/O D2 30 I INP 46 — VDD 62 O MON2
15 I/O D3 31 I READY 47 O WGATE 63 O MON3
16 I/O D4 32 I WPRT 48 O WDATA 64 — GND

This datasheet has been downloaded from http://www.digchip.com at this page


HD63266F (2/3)

INPUT 12
8"/5" ; DATA TRANSFER RATE SELECT D0
13 21
CS ; CHIP SELECT D1 IRQ
DACK ; DMA ACKNOWLEDGE 14
D2
DEND ; DMA END 15
D3 20
E, RD ; ENABLE, READ DREQ
16
IFS ; INTERFACE SELECT D4
17 47
INDEX ; INDEX D5 WGATE
INP ; INPUT PORT 18 48
D6 WDATA
NUM1, 2 ; NOT USER MODE 1, 2 19
D7
R/W, WR ; READ/WRITE, WRITE
24
RDATA ; READ DATA 1/2 EX1
READY ; READY 3
RESET
RESET ; RESET 4
E, RD 50
STEP
RS0, 1 ; REGISTER SELECT 0, 1 5
R/W, WR
SFORM ; SELECT FORMAT DATA 6
CS 51
TRKO ; TRACK 00 HDIR
8
WPRT ; WRITE PROTECTED RS0 HLOAD
52
XTAL1, 2 ; XTAL 1, 2 9
RS1 53
HSEL
XTALSEL ; XTAL SELECT
7 55
OUTPUT DACK DS0
1/2EX1 ; 1/2 EXTAL1 22 56
DEND DS1
DREQ ; DMA REQUEST 57
DS0-DS3 ; DRIVE SELECT 0-3 DS2
35 58
HDIR ; HEAD DIRECTION RDATA DS3
34
HLOAD ; HEAD LOAD INDEX
HSEL ; HEAD SELECT 33 60
TRKO MON0
IRQ ; INTERRUPT REQUEST 61
MON1
MON0-MON3 ; MOTOR ON 0-3 2 62
STEP ; STEP XTALSEL MON2
26 63
WDATA ; WRITE DATA NUM1 MON3
27
WGATE ; WRITE GATE NUM2

INPUT/OUTPUT 30
D0-D7 ; DATA BUS 0-7 INP

32
WPRT

39
XTAL1
36
XTAL2

1
8"/5"
28
IFS
29
SFORM
31
READY
HD63266F (3/3)

ROM SEEK
ADDRESS CONTROL
ALU TIMER
CONTROL

INTERNAL BUS

HOST FDD

PROM RAM
WRITE
CONTROL

READ
VFO
CONTROL
HOST CLOCK
INTERFACE GENERATOR

I/O
PORT

DRIVER,
RECEIVER

ALU; ARITHMETIC LOGIC UNIT


VFO; VARIABLE FREQUENCY OSCILLATOR

You might also like