EE213

Digital Integrated Circuits II

Lecture 07-C: Dynamic Logic

Prof. Pingqiang Zhou
http://sist.shanghaitech.edu.cn/faculty/zhoupq/Teaching/Spr17/Digital-IC-2.html

ShanghaiTech University
School of Information Science and Technology

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 Materials were partly taken from
 EE141: Digital Integrated Circuits, Spring 2010.
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s
10/index.htm

Chapter 6

Chapter 8
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 Static vs. Dynamic CMOS Circuit
VDD
In1 CLK Mp
In2 PUN Out
InN In1 CL
F(In1,In2,…InN)
In2 PDN
In1
In3
In2 PDN
InN CLK Me

 Static complementary CMOS - except during switching,

output connected to either VDD or GND via a low-
resistance path.
 Dynamic CMOS - relies on temporary storage of signal
values on the capacitance of high-impedance circuit
nodes.
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 Dynamic Gate

off
CLK Mp CLK Mp on
1
Out Out
In1 CL
A
In2 PDN
C
In3
B
CLK Me
off
CLK Me on

Two phase operation

Precharge (CLK = 0)
Evaluate (CLK = 1)

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 Properties of Dynamic Gates
 Logic function only implemented by PDN
off
 number of transistors is N + 2 (versus 2N CLK Mp on
for static complementary CMOS) 1
Out
 Full swing outputs (VOL = GND, VOH = VDD) A
 Nonratioed - sizing of the devices is not C
important for proper functioning (only for B
performance) off
CLK Me on
 Faster switching speeds
 reduced load capacitance due to
- fewer transistors per gate (Cint), reduced logical effort
- smaller fan-out (Cext)
 no Isc, so all the current provided by PDN discharges CL
 Ignoring the influence of precharge time on the switching
speed of the gate, tpLH = 0, but the presence of the
evaluation transistor slows down the tpHL.
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 LE of Dynamic Gates

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 Properties of Dynamic Gates – Static VTC
 PDN starts to work as the input signals exceed VTn, so
 set VM, VIH and VIL all equal to VTn
 low noise margin (NML)

CLK
Out
In1
In2
In3

In4
CLK

#Trns VOH VOL VM NMH NML

6 2.5V 0V VTn 2.5-VTn VTn

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 Gate Parameters are Time Independent
 The amount by which the output voltage drops is a
strong function of the input voltage and the available
evaluation time.

CLK CLK
2.5
Out
In1 Vout (VG=0.45)

Voltage (V)
In2 1.5
Vout (VG=0.55)
In3 Vout (VG=0.5)
0.5
In4 VG

CLK -0.5
0 20 40 60 80 100
Time (ns)

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 Properties of Dynamic Gates – Dynamic

Evaluate
CLK 2.5
Out
In1
1.5
In2 Out
In3 0.5 In &
CLK Precharge
In4
CLK -0.5
0 0.5 1
Time, ns

#Trns VOH VOL VM NMH NML tpHL tpLH tpre

6 2.5V 0V VTn 2.5-VTn VTn 110ps 0ns 83ps

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 Properties of Dynamic Gates - Power
 Power dissipation should be better off
 consumes only dynamic power – no short CLK Mp on
circuit power consumption since the pull-up 1
Out
path is not on when evaluating
 lower CL- both Cint (since there are fewer A
transistors connected to the drain output) and
Cext (since there the output load is one per C
connected gate, not two) B
 by construction can have at most one off
transition per cycle – no glitching CLK Me on

 But power dissipation can be significantly

higher due to
 higher transition probabilities
 extra load on CLK (needs a
precharge/evaluate clock)

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 Power Consumption of Dynamic Gate

CLK Mp
Out
In1 CL
In2 PDN
In3

CLK Me

Power only dissipated when previous Out = 0

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 Dynamic Power Consumption is Data Dependent
Switching activity can be higher in dynamic gates!
转换的灵敏度 P01 = Pout=0

A B Out

Out 0 0 1

0 1 0
Out
1 0 0
1 1 0

Assume signal probabilities PA=1 = ½ PB=1 = ½

Then transition probability
P01 = Pout=0 x Pout=1 = 3/4 x 1 = 3/4

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 Issues in Dynamic Design 1: Charge Leakage

CLK
4
3
CLK Mp
Out
1

A=0 CL
2
VOut Precharge Evaluate
CLK Me

Leakage sources

Minimum clock rate of a few kHz

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 Impact of Charge Leakage
 Output settles to an intermediate voltage determined by
a resistive divider of the pull-up and pull-down networks
 Once the output drops below the switching threshold of the
fan-out logic gate, the output is interpreted as a low voltage.

CLK
4
3
2.5
CLK Mp

V o lta g e (V )
Out
1 1.5 Out
A=0 CL
2

CLK Me 0.5

-0.5
0 20 40
Time (ms)
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 A Solution to Charge Leakage
 Keeper compensates for the charge lost due to the pull-
down leakage paths.
Keeper

CLK Mp Mkp
Out
A
CL
B

CLK Me

Same approach as level restorer for pass

transistor logic

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 Issues in Dynamic Design 2: Charge Sharing

CLK Mp
Out
A CL

B=0 CA

CLK Me CB

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 Issues in Dynamic Design 2: Charge Sharing

CLK Mp
Out
A CL

B=0 CA

CLK Me CB

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 Charge Sharing Example
What is the worst case voltage drop on y? (Assume all inputs are low
during precharge and that all internal nodes are initially at 0V.)
Load
CLK inverter
y=ABC

A Cy=50fF
a

B b
Ca=15fF B
c d Cb=15fF

Cc=15fF C Cd=10fF

CLK

Vout = - VDD ((Ca + Cc)/((Ca + Cc) + Cy))

= - 2.5V*(30/(30+50)) = -0.94V
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 Solution to Charge Redistribution

CLK Mp Mkp CLK

Out
A

CLK Me

Precharge internal nodes using a clock-driven

transistor (at the cost of increased area and power)

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 Issues in Dynamic Design 3: Backgate Coupling
 Susceptible to crosstalk due to
 high impedance of the output node and
 backgate capacitive coupling

 Out2 capacitively couples with Out1 through the gate-

source and gate-drain capacitances of M4

CLK Mp M6 M5
Out1 =1
Out2 =1 ->0
A=0 M1 M4
CL1 CL2

B=0 M2 M3 In

CLK Me

Dynamic NAND Static NAND

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 Backgate Coupling Effect
 Capacitive coupling means Out1 drops significantly so
Out2 doesn’t go all the way to ground

2
Out1
1 CLK

0 Out2
In

-1
0 2 Time, ns 4 6

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 Issues in Dynamic Design 4: Clock Feedthrough
 A special case of backgate capacitive coupling between
the clock input of the precharge transistor and the
dynamic output node

CLK Mp
Coupling between Out and
Out CLK input of the precharge
A CL
device due to the gate-
drain capacitance. So
B voltage of Out can rise
above VDD. The fast rising
CLK Me
(and falling edges) of the
clock couple to Out.

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 Clock Feedthrough

CLK Clock feedthrough

Out
In1 2.5

In2
1.5
In3
In &
In4 0.5 CLK
CLK Out

-0.5
0 0.5 Time, ns 1

Clock feedthrough

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 Issues in Dynamic Design 5: Cascading Gates
V

CLK
CLK Mp
CLK Mp
Out2
Out1 In
In
VTn
Out1
CLK Me CLK Me
V
Out2

Only 0  1 transition allowed at the inputs

during the evaluation period!

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 Domino Logic

CLK Mp CLK Mp Mkp

11 Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5

CLK Me CLK Me

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 Why Domino?

CLK
10 10 10 10

In1 01 01 01 01

Ini PDN Ini PDN Ini PDN Ini PDN
Inj Inj Inj Inj
CLK

Like falling dominos!

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 Properties of Domino Logic
 Very high speed
 static inverter can be optimized to match fan-out (separation of
fan-in and fan-out capacitances)
 Only L->H transition critical
 Input capacitance reduced – smaller logical effort

CLK Mp CLK Mp Mkp

Out1 Out2
01
01
In1
In2 PDN In4 PDN
In3 In5

CLK Me CLK Me

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 Domino Logic LE

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 Domino Logic LE (Skewed Static Gate)

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 Design with Domino Logic

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 Properties of Domino Logic
 Only non-inverting logic can be implemented, fixes
include
 can reorganize the logic using Boolean transformations
 use differential logic (dual rail)
 use np-CMOS (zipper)

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 np-CMOS (Zipper)

11
10

00
01

Only 0  1 transitions allowed at inputs of PDN

Only 1  0 transitions allowed at inputs of PUN

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 np-CMOS Adder Circuit

CLK 1x
0x Sum1

1x

0x C2
CLK

CLK 1x B0
0x
A0 A0 B0 C0 A0
A0 B0 B0 1x C0
C0 CLK 0x

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 How to Choose a Logic Style?
 Must consider ease of design, robustness (noise immunity),
area, speed, power, system clocking requirements, fan-out,
functionality, ease of testing.
VDD VDD Example: 4-input NAND
In1 CLK Mp
PMOS
In2 PUN Load F
B
VSS
InN F A F In1
F
B In2 PDN
In1 In1 0
In2 PDN In3
In2 PDN In3
InN CLK Me
VSS

 Current trend is towards an increased use of

complementary static CMOS: design support through DA
tools, robust, more amenable to voltage scaling.

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 Next Lecture and Reminders
 Next lecture
 Adders

Chapter 11
Chapter 10

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